7. VLSI Architecture and System-on-Chip Design

Introduction and Context

Very-large-scale integration (VLSI) design has moved from the implementation of isolated digital circuits to the integration of complete computing, communication, sensing, and control platforms on a single die or package. A modern system-on-chip (SoC) may contain processor cores, digital signal processors, memories, accelerators, clocking circuits, security blocks, analog interfaces, and high-speed communication fabrics. The central design problem is therefore architectural: how should computation, storage, communication, and control be organized so that the required workload is completed within limits of performance, power, area (PPA), cost, reliability, and time to market?

At postgraduate level, SoC design must be viewed as a quantitative exercise rather than a catalogue of blocks. A processor that has a high peak frequency may perform poorly on a memory-bound workload. A highly parallel accelerator may reduce execution time but increase area, leakage, data movement, and verification effort. Similarly, a network-on-chip (NoC) can provide scalable communication, yet its routers and buffers consume power and introduce latency. Architecture is therefore the discipline of matching an implementation structure to workload behavior and system constraints.

This chapter develops that perspective. It examines pipelining and parallelism, processor and DSP datapaths, bus protocols and NoCs, memory hierarchies, heterogeneous integration, hardware acceleration, and AI/ML engines. It also introduces PPA-oriented analysis, practical design methods, and an illustrative case study showing how architectural decisions are made for a real-time edge-vision SoC.

Learning Objectives

After studying this chapter, the learner should be able to:

1. Explain the relationship among pipelining, parallelism, throughput, latency, and clock frequency.

2. Evaluate processor and DSP datapaths for different classes of workloads.

3. Compare shared buses, crossbars, and NoCs using bandwidth, latency, arbitration, area, and power considerations.

4. Design and analyze a memory hierarchy, including caches, scratchpad memories, and DMA-based data movement.

5. Assess heterogeneous integration involving CPUs, DSPs, GPUs, FPGA fabric, and domain-specific accelerators.

6. Apply workload and PPA analytics to architectural trade-offs.

7. Identify design, verification, security, thermal, and governance risks in complex SoCs.

8. Recommend an architecture for a constrained application using quantitative reasoning.

From Algorithm to Architecture

An architecture is an organized set of computational resources, storage elements, interconnects, and control mechanisms that realizes a system specification. The same algorithm can be mapped onto very different architectures. A finite impulse response (FIR) filter, for example, may execute on a general-purpose processor, a vector DSP, a systolic accelerator, or a dedicated multiply-accumulate (MAC) array. The selection depends on sample rate, numerical precision, response-time requirements, flexibility, and energy budget.

A useful design flow begins with workload characterization. The architect identifies operations per input, data volume, dependencies, locality, burstiness, real-time deadlines, and acceptable precision. Common metrics include:

• throughput, measured in results or transactions per second;
• latency, measured from input availability to output completion;
• initiation interval, indicating how frequently a pipelined unit can accept new inputs;
• operational intensity, defined approximately as computation operations per byte transferred;
• energy per operation or per inference;
• silicon area and estimated recurring cost; and
• utilization, which indicates how effectively resources are used.

Peak performance is meaningful only when connected to workload demand. If a kernel requires 16 operations per input and receives 100 million inputs per second, it requires 1.6 billion operations per second. A design with a nominal capability of 4 billion operations per second may still fail if memory bandwidth, synchronization, or control overhead limits sustained performance.

A simplified performance model is

Performance = min(compute capacity, memory bandwidth × operational intensity, communication capacity).

This roofline-style view distinguishes compute-bound workloads from bandwidth-bound workloads. Increasing arithmetic units helps the former, whereas improving locality, cache behavior, compression, or data reuse is more effective for the latter.

Pipelining and Parallelism as Architectural Choices

Pipelining divides a computation into stages separated by registers. While one data item is processed in a later stage, another can occupy an earlier stage. For a balanced pipeline with k stages, the latency of one item is approximately k clock periods, but the steady-state throughput can approach one item per clock period. Pipelining therefore improves throughput rather than automatically reducing the latency of an individual operation.

The maximum clock period is influenced by the slowest combinational stage, register setup and clock-to-Q delays, and clock skew. If a logic path has delay D and register overhead is tR, the approximate clock period is Tclk ≥ D + tR. Deeper pipelining reduces D per stage, but adds registers, clock power, area, control complexity, and pipeline fill and drain penalties.

Pipeline hazards are important in processor datapaths. A data hazard occurs when an instruction depends on an earlier result. A control hazard follows a branch or jump, while a structural hazard occurs when two operations require the same hardware resource. Forwarding, interlocks, branch prediction, duplicated resources, and compiler scheduling are common remedies. In an application-specific pipeline, hazards may arise from feedback loops, variable-latency memory, or resource sharing.

Parallelism can be temporal, spatial, data-level, instruction-level, or task-level. Temporal parallelism is exploited through pipelining. Spatial parallelism uses multiple functional units operating concurrently. SIMD and vector architectures apply one instruction to multiple data elements, while task parallelism assigns independent functions to separate cores or engines. The ideal speedup from N parallel units is rarely achieved because of serial portions, synchronization, memory contention, load imbalance, and communication overhead. Amdahl’s law expresses this limitation:

Speedup = 1 / [(1 − p) + p/N],

where p is the parallelizable fraction and N is the number of parallel resources.

For energy-constrained SoCs, the relevant measure is not speedup alone. A design that doubles performance while tripling power may be unacceptable. Designers therefore consider energy-delay product, performance per watt, and energy per completed task. Voltage and frequency scaling can be especially effective, but lower voltage reduces timing margin and may require architectural adaptations.

Processor and DSP Datapaths

A processor datapath contains the hardware through which operands move and are transformed. Typical components include a register file, arithmetic and logic unit, shifter, multiplier, load/store unit, program counter, instruction decode logic, and bypass paths. The control unit determines the sequence of operations, while the datapath determines the available computation and data movement.

A scalar RISC core offers programmability and relatively simple control. Superscalar or out-of-order cores exploit instruction-level parallelism but require issue logic, register renaming, reorder buffers, speculative execution, and substantial power. In an SoC, the decision is not simply whether a powerful core is available; it is whether the workload benefits enough to justify its area, verification, software, and thermal cost.

DSP datapaths are optimized for regular numerical operations. A DSP commonly includes one or more MAC units, saturating arithmetic, circular or modulo addressing, bit-reversed addressing, wide accumulators, and specialized instructions. These features are valuable in filtering, transforms, modulation, audio processing, motor control, and wireless baseband computation.

Fixed-point arithmetic reduces area, energy, and memory bandwidth compared with floating point, but introduces quantization, overflow, scaling, and signal-to-noise concerns. Saturation arithmetic prevents wraparound in many signal-processing applications. A design team must select word lengths through numerical analysis rather than habit. Excess precision wastes resources; insufficient precision can degrade system quality or destabilize a control loop.

A datapath may be organized as an accumulator architecture, a register-register architecture, a vector lane architecture, or a systolic arrangement. Systolic arrays pass data rhythmically between neighboring processing elements and are well suited to matrix multiplication because they offer regular wiring and high data reuse. Their efficiency declines when matrices are small, sparse, irregular, or poorly aligned with the array dimensions.

Interconnect: From Shared Buses to Networks-on-Chip

Interconnect determines how masters access memories and peripherals and how processing elements exchange data. A shared bus is simple and economical for a small number of low-bandwidth agents. However, all masters compete for one communication resource, and arbitration delay increases as traffic grows. A crossbar provides multiple simultaneous paths, improving concurrency, but its area and wiring complexity grow rapidly with the number of masters and slaves.

Modern SoCs commonly use layered transaction protocols. A request typically includes an address, command, attributes, and possibly data. A response reports completion, returned data, or an error. Decoupled valid-ready handshaking allows a sender and receiver to operate at different rates: a transfer occurs only when valid and ready are both asserted. This prevents data loss under backpressure but requires careful management of buffering and deadlock.

Important protocol concepts include burst transfers, outstanding transactions, ordering rules, atomic operations, cache coherency, protection attributes, and quality of service. A burst amortizes address and arbitration overhead over multiple data beats. Out-of-order completion can improve utilization but requires transaction identifiers and reordering logic. Coherent interconnects maintain consistent views of shared memory among caches; non-coherent systems are simpler but require explicit software or DMA-based synchronization.

As core counts and data movement increase, a network-on-chip becomes attractive. An NoC consists of routers, links, network interfaces, buffers, and routing and flow-control mechanisms. Topologies include mesh, torus, ring, tree, and hierarchical structures. A two-dimensional mesh is common because it scales regularly and supports layout automation.

Routing may be deterministic, such as dimension-ordered routing, or adaptive, allowing paths to change according to congestion. Wormhole flow control divides packets into flits and permits a packet to occupy several routers. Virtual channels separate traffic classes and can prevent protocol-level deadlock. NoC evaluation must include average and worst-case latency, sustainable throughput, buffer occupancy, router power, area, congestion, and fault tolerance.

Interconnect is often the hidden limit in a many-core SoC. Adding compute engines without increasing memory and network capacity can produce low utilization. Therefore, the architecture should place high-communication blocks near shared memories or use local memories and explicit data movement to reduce traffic.

Memory Hierarchy and Data Movement

Memory hierarchy exploits the fact that recently or repeatedly used data is likely to be used again. Registers are small and fast; caches provide automatic locality management; scratchpad memories offer software-managed predictable storage; local SRAMs provide high bandwidth near accelerators; and external DRAM supplies large capacity at higher latency and energy cost.

Cache performance is described using hit rate, miss penalty, and access time. Average memory access time can be approximated as

AMAT = hit time + miss rate × miss penalty.

A larger cache may improve hit rate but increase access time, leakage, area, and verification effort. Associativity reduces conflict misses but adds tag comparison and replacement complexity. Write-through caches simplify consistency but generate more traffic; write-back caches reduce traffic but require dirty-state management.

Scratchpad memories are particularly useful in DSP and accelerator designs because their timing is predictable. Software or DMA engines explicitly move tiles into local storage. Tiling divides a large computation into blocks that fit in local memory, enabling reuse of operands before they are evicted. Double buffering overlaps computation on one tile with transfer of the next tile.

DMA is essential for reducing processor involvement in bulk transfers. A DMA controller can generate bursts, perform address strides, and sometimes scatter-gather operations. However, DMA introduces coherency and ownership issues. Before a non-coherent accelerator reads data, the CPU may need to write back dirty cache lines; after completion, the CPU may need to invalidate stale lines. Incorrect synchronization can produce intermittent functional errors that are difficult to reproduce.

Memory bandwidth must be calculated from actual traffic, not only from the number of arithmetic operations. If an accelerator performs 1 tera-operation per second but requires two 16-bit operands and one 16-bit result per operation without reuse, its raw traffic is approximately 6 terabytes per second, which may be impossible for the selected memory system. Data reuse, compression, lower precision, and fused operations are architectural tools for reducing this requirement.

Heterogeneous Integration and Domain-Specific Acceleration

A heterogeneous SoC combines processing elements with different strengths. A CPU handles operating-system services, control-intensive code, and irregular tasks. A DSP handles predictable signal-processing kernels. A GPU or vector engine provides high data parallelism. An FPGA fabric offers reconfigurability and custom pipelines. Fixed-function accelerators provide excellent energy efficiency for stable algorithms.

The challenge is partitioning. A function is a good accelerator candidate when it consumes substantial execution time, has regular data flow, benefits from parallelism, and communicates with the rest of the system at manageable cost. Offloading a small function can be counterproductive if invocation, data transfer, synchronization, and context-management overhead exceed the saved computation time.

A practical partitioning method is to profile the software, identify hot kernels, measure data movement, and estimate accelerator PPA before committing to RTL. Hardware-software interfaces should specify command formats, buffer ownership, interrupts, error reporting, reset behavior, and security permissions. Driver quality is part of architecture because an unusable accelerator provides no system benefit.

Chiplets and advanced packaging extend heterogeneous integration beyond a single monolithic die. Separate dies may be optimized for logic, analog, memory, or a mature process technology and connected through high-density package links. This can improve reuse and manufacturing flexibility, but introduces thermal coupling, package-level signal integrity, test requirements, inter-die latency, and supply-chain considerations.

AI/ML Engines in the SoC

AI/ML workloads, particularly neural-network inference, emphasize matrix and convolution operations, high data reuse, and large tensor movement. An ML engine may contain MAC arrays, vector units, activation functions, accumulators, quantization logic, and local buffers. Systolic arrays and spatial dataflow architectures are common because they keep weights, activations, or partial sums close to computation.

Quantization maps floating-point values to lower-precision formats such as 8-bit or 4-bit integers. It reduces storage and bandwidth and increases arithmetic density, but may reduce accuracy. Quantization-aware training, calibration, mixed precision, and sparsity exploitation are techniques for managing this trade-off. Sparse hardware is beneficial only when the sparsity pattern can be detected and exploited at lower cost than the irregular control and indexing it introduces.

AI accelerators should be evaluated using end-to-end metrics: inference latency, throughput, energy per inference, accuracy, memory footprint, utilization, and response under multiple workloads. TOPS is a peak metric and does not reveal whether the memory hierarchy, compiler, or software stack can sustain the advertised rate. Model updates also create governance concerns: an accelerator should support controlled firmware and model deployment, authenticated updates, logging, and protection of sensitive data.

PPA Analytics and Architectural Decision-Making

PPA analysis begins with a workload specification and a set of constraints. The design team develops an analytical estimate, builds a transaction-level or cycle-accurate model, synthesizes representative RTL, and refines estimates through implementation. No single model is sufficient. Early estimates support exploration; later measurements reveal effects of physical design, clock trees, routing congestion, leakage, and process variation.

A useful comparison table includes frequency, latency, sustained throughput, area, dynamic power, leakage power, energy per task, memory bandwidth, utilization, and verification effort. These values should be measured under comparable workloads and operating conditions. A design should not be selected solely because it has the highest frequency or smallest core area.

Pareto analysis identifies alternatives for which no objective can be improved without worsening another. For example, one architecture may deliver lower energy but higher latency, while another delivers higher throughput at greater area. Weighted scoring can be used when priorities are known, but weights should be documented because they encode organizational and product assumptions.

Sensitivity analysis asks which parameters most affect the result. If performance changes strongly with memory bandwidth but weakly with arithmetic-unit count, further investment in compute is unlikely to help. Design-space exploration may vary tile size, number of lanes, cache capacity, clock frequency, voltage, precision, and interconnect topology. Automated simulation and synthesis can search these alternatives, but the results remain dependent on model quality.

Illustrative Case Study: An Edge-Vision SoC

Background

Consider an illustrative company developing a battery-powered industrial camera. The camera must capture frames, perform object detection locally, record selected events, and communicate results over a secure wireless link. The product requires low response latency, modest energy consumption, field upgradability, and protection of captured images.

Situation and Problem

A software prototype running entirely on a general-purpose processor meets functional requirements but consumes too much energy and misses the response-time target at high image rates. A proposed solution is to add a large neural-network accelerator. Preliminary analysis, however, shows that external-memory traffic and image pre-processing may dominate execution time.

Analysis

Profiling identifies four major workloads: sensor acquisition, image pre-processing, convolutional inference, and control/network software. Pre-processing involves regular filtering and resizing; inference involves matrix operations; control tasks are irregular and occasionally bursty. The camera also requires a secure boot path and encrypted storage.

An architecture consisting only of a CPU would provide flexibility but insufficient performance per watt. A large accelerator could provide peak throughput but would increase area and memory bandwidth. A small CPU, a DSP for filtering, and a moderate-intensity ML engine are more closely matched to the workload. Local SRAM and DMA can reduce repeated movement to external DRAM.

Approach and Solution

The selected architecture uses a dual-core embedded CPU for operating-system and control functions, a DSP pipeline for sensor correction and resizing, and an 8-bit ML accelerator with tiled local buffers. A coherent connection is retained between the CPUs and system memory, while the DSP and ML engine use explicit DMA transfers into local SRAM. Double buffering allows computation on one image tile while the next tile is transferred.

The interconnect uses a high-bandwidth fabric for the camera pipeline and lower-bandwidth peripheral buses for configuration registers. Traffic classes are separated so that sensor data is not blocked by non-critical software transfers. The accelerator interface exposes command queues, buffer descriptors, completion status, and error codes. Access-control checks prevent unauthorized software from reading image buffers.

The team evaluates three alternatives: CPU-only, CPU plus large accelerator, and heterogeneous CPU-DSP-moderate-accelerator. The CPU-only option has the lowest area but fails throughput and energy targets. The large accelerator has the best peak throughput but requires excessive DRAM bandwidth and has low utilization on small regions of interest. The heterogeneous design provides lower peak throughput than the large accelerator but achieves better sustained performance per watt through locality and task specialization.

Outcome

The selected design satisfies the illustrative latency and energy objectives in the modeled workload while retaining software flexibility for future algorithms. Its main benefit is not simply the presence of an accelerator; it is the coordinated design of dataflow, local memory, DMA, interconnect priority, and software scheduling.

Learning Points

First, workload decomposition is more informative than a processor-versus-accelerator debate. Second, memory movement can dominate arithmetic. Third, peak TOPS does not guarantee application performance. Fourth, security, driver behavior, and update mechanisms must be included in the architecture rather than added at the end.

Challenges, Risks, and Common Design Errors

One common error is optimizing a benchmark that does not represent field behavior. Average latency may conceal unacceptable worst-case latency caused by cache misses, arbitration, or thermal throttling. Another error is adding parallel units without estimating synchronization and memory traffic. Excessive pipeline depth can increase branch penalties and control complexity. Under-sized buffers cause backpressure; oversized buffers waste area and may hide deadlock or overflow conditions.

Coherency is a frequent source of defects in heterogeneous systems. Ownership protocols must specify who may modify a buffer and when the modification becomes visible. Reset and power-state transitions require equal attention: a partially reset accelerator can corrupt transactions or retain sensitive information.

Physical design may invalidate early architectural assumptions. Long global wires, congestion around memory macros, IR drop, clock distribution, and thermal hotspots can reduce achievable frequency. Approximate PPA models should therefore include uncertainty margins. Verification risk also grows with custom protocols, out-of-order transactions, speculative execution, and configurable accelerators.

Professional, Ethical, and Governance Considerations

SoC architects influence safety, privacy, reliability, and environmental impact. Security mechanisms should include secure boot, hardware roots of trust, privilege separation, memory protection, cryptographic acceleration, side-channel awareness, and authenticated updates. Debug interfaces must be controlled in production because unrestricted test access can expose keys or private data.

For safety-critical systems, deterministic timing, fault detection, redundancy, watchdogs, safe-state behavior, and traceability of requirements are essential. AI-enabled products require attention to data provenance, model integrity, bias in training data, explainability appropriate to the application, and the consequences of incorrect classification. Energy-efficient architecture also reduces thermal stress and operational energy consumption, although manufacturing impact and electronic waste remain broader lifecycle concerns.

Current Directions and Best Practices

Current SoC development is moving toward domain-specific architectures, chiplet-based integration, open instruction-set extensions, hardware-software co-design, near-memory processing, and increasingly automated design-space exploration. Specialized engines are becoming more programmable so that they can support changing models without sacrificing all energy efficiency. Advanced packaging is enabling tighter memory integration, but system analysis is expanding from die-level PPA to package-level thermal and reliability behavior.

Best practice is to begin with measurable workload traces, define system-level constraints, and maintain a traceable link between requirements and architectural choices. Use analytical models before detailed implementation, but calibrate those models with representative RTL and physical results. Evaluate sustained rather than peak performance, include software and verification costs, specify interfaces precisely, and test error, reset, security, and thermal conditions early. Finally, preserve architectural flexibility where algorithms are expected to evolve and specialize only where workload evidence justifies the investment.

Chapter Summary

VLSI architecture and SoC design organize computation, storage, communication, and control to satisfy workload and PPA constraints. Pipelining increases throughput by overlapping stages, while parallelism increases concurrent work; neither removes limits imposed by dependencies, memory, communication, or serial execution. Processor and DSP datapaths should be selected according to control complexity, numerical behavior, regularity, and required flexibility.

Interconnect evolves from shared buses to crossbars and NoCs as concurrency and traffic increase. Memory hierarchy, scratchpads, DMA, tiling, and double buffering often determine sustained performance more strongly than arithmetic peak. Heterogeneous SoCs combine CPUs, DSPs, GPUs, reconfigurable logic, and fixed-function accelerators, but successful integration requires careful partitioning and robust interfaces. AI/ML engines benefit from data reuse, lower precision, and local storage, while TOPS must not be confused with application performance.

PPA analytics should use workload traces, sustained metrics, energy per task, bandwidth, utilization, and Pareto trade-offs. Architectural decisions must also account for physical design, verification, security, safety, software, thermal behavior, and future adaptability.

Key Terms

Pipelining: Dividing computation into sequential stages separated by registers to overlap multiple operations.

Throughput: The rate at which completed results or transactions are produced.

Latency: The time between the initiation of an operation and its completion.

Initiation interval: The minimum time between accepting successive inputs in a pipeline.

Parallelism: Concurrent execution of multiple operations, instructions, data elements, or tasks.

Datapath: Hardware resources and connections through which operands are stored and processed.

DSP: A processor optimized for regular numerical signal-processing operations.

MAC: Multiply-accumulate operation commonly used in filters and neural networks.

AMAT: Average memory access time, including hit time and miss-related delay.

Scratchpad: Software-managed local memory with predictable access behavior.

DMA: Direct memory access mechanism that transfers data without continuous CPU participation.

Coherency: Consistency of values held in multiple caches or processing elements.

NoC: Network-on-chip providing packet-based communication among SoC components.

Virtual channel: A logical flow-control channel sharing a physical interconnect link.

Operational intensity: Computational operations performed per byte of data moved.

Heterogeneous SoC: An SoC containing processing elements with different architectural capabilities.

Systolic array: Regular interconnected processing elements that pass data rhythmically between neighbors.

Quantization: Representing numerical values with reduced precision or a restricted numeric format.

Pareto frontier: Set of design alternatives for which no objective can improve without worsening another.

Energy per task: Energy consumed to complete a specified application-level operation.

Review Questions

Short Answer Questions

1. Distinguish pipeline latency from pipeline throughput.

2. What is the purpose of a scratchpad memory in an accelerator-based SoC?

3. State two reasons why a NoC may be preferred to a shared bus.

4. Define operational intensity and explain its relevance to architecture.

5. What coherency problem can arise when a DMA engine shares memory with a CPU cache?

Long Answer Questions

1. Explain how pipelining, forwarding, branch handling, and resource duplication address hazards in a processor datapath.

2. Compare shared buses, crossbars, and NoCs with respect to scalability, latency, area, and power.

3. Discuss the role of cache, scratchpad, DMA, tiling, and double buffering in improving accelerator performance.

4. Explain the architectural characteristics of DSPs, vector processors, GPUs, and fixed-function accelerators.

5. Describe a systematic PPA-oriented design-space exploration process for a heterogeneous SoC.

Analytical / Application Questions

1. A workload is highly parallel but transfers large tensors repeatedly to external memory. Using the roofline perspective, explain why adding more arithmetic units may not improve performance and recommend two architectural changes.

2. Select a suitable processor, memory, and interconnect organization for a battery-powered real-time audio device. Justify the selection using latency, energy, locality, and flexibility.

3. An ML accelerator achieves high peak TOPS but only 35% utilization on the target application. Identify likely architectural causes and propose a measurement-driven investigation.

22. Multiple Choice Questions with Answers

Question 1

Which statement most accurately describes the principal benefit of pipelining?

A. It always reduces the latency of an individual operation

B. It increases steady-state throughput by overlapping operations

C. It eliminates all data and control hazards

D. It removes the need for clocked storage elements

Correct Answer: B. It increases steady-state throughput by overlapping operations

Question 2

A workload has low computational demand but repeatedly transfers data to external DRAM. Which change is most likely to improve performance per watt?

A. Adding more arithmetic units without changing memory

B. Increasing branch-prediction table size

C. Using tiling and local SRAM to increase data reuse

D. Deepening every pipeline stage

Correct Answer: C. Using tiling and local SRAM to increase data reuse

Question 3

What is a major advantage of a scratchpad memory over a conventional cache in an accelerator?

A. It provides software-controlled and predictable storage

B. It automatically maintains coherency across all processors

C. It has unlimited capacity

D. It requires no data movement management

Correct Answer: A. It provides software-controlled and predictable storage

Question 4

In a valid-ready transaction interface, when does a transfer normally occur?

A. When valid is asserted, regardless of ready

B. When ready is asserted, regardless of valid

C. When both valid and ready are asserted

D. Only after an interrupt is generated

Correct Answer: C. When both valid and ready are asserted

Question 5

Why can a large neural-network accelerator deliver poor application performance despite high peak TOPS?

A. Peak TOPS directly measures software quality

B. Memory bandwidth, data movement, or low utilization may limit sustained performance

C. More MAC units always increase control latency proportionally

D. Neural networks cannot use local storage

Correct Answer: B. Memory bandwidth, data movement, or low utilization may limit sustained performance

Question 6

Which architecture is generally most appropriate for regular filtering with repeated multiply-accumulate operations?

A. A DSP datapath with MAC and specialized addressing support

B. A peripheral-only microcontroller with no multiplier

C. A large branch-prediction unit

D. A cache controller without processing elements

Correct Answer: A. A DSP datapath with MAC and specialized addressing support

Question 7

What does a Pareto frontier represent in architectural design?

A. Designs having identical frequency and area

B. Designs for which every objective is simultaneously maximized

C. Alternatives where improving one objective requires worsening another

D. Only the design with the lowest power

Correct Answer: C. Alternatives where improving one objective requires worsening another

Question 8

Which situation most directly creates a CPU-DMA coherency problem?

A. The CPU and DMA use separate clock frequencies

B. The CPU reads a stale cached copy after DMA has updated main memory

C. The DMA controller uses burst transfers

D. The processor executes fixed-point arithmetic

Correct Answer: B. The CPU reads a stale cached copy after DMA has updated main memory

Question 9

Why are virtual channels used in some networks-on-chip?

A. To eliminate all router buffers

B. To support traffic separation and help manage deadlock or congestion

C. To convert analog signals into digital signals

D. To guarantee zero latency

Correct Answer: B. To support traffic separation and help manage deadlock or congestion

Question 10

For an edge-vision SoC, why might a moderate accelerator combined with a DSP and local SRAM outperform a larger accelerator?

A. The larger accelerator cannot perform arithmetic

B. Specialized processing and reduced data movement can improve sustained performance per watt

C. A DSP always has greater peak throughput than an accelerator

D. Local SRAM increases external-memory traffic

Correct Answer: B. Specialized processing and reduced data movement can improve sustained performance per watt