Timing, Signal Integrity, Power Integrity, and Variation

Introduction

Modern VLSI systems rarely fail because a logic function is incorrect. They fail because a correct function cannot be delivered at the required speed, voltage, noise margin, or lifetime. As feature sizes decrease and interconnects dominate delay, timing closure becomes inseparable from signal integrity, power integrity, process variation, and reliability. A design may satisfy nominal static timing analysis yet fail in silicon because crosstalk changes delay, supply noise alters cell performance, or local variation causes an unexpected setup or hold violation.

This chapter develops an integrated methodology for electrical and timing closure. It covers static timing analysis (STA), multi-mode multi-corner (MMMC) analysis, on-chip variation (OCV), crosstalk, electromigration (EM), IR drop, decoupling, and statistical approaches. The emphasis is on assumptions, interpretation, design trade-offs, and practical sign-off decisions rather than on isolated tool commands.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Formulate setup and hold timing checks and interpret timing slack.

2. Construct and evaluate timing paths under multiple operating modes and process corners.

3. Explain OCV, advanced OCV, and parametric statistical timing models.

4. Analyze crosstalk-induced delay and noise and distinguish aggressor effects from functional logic behavior.

5. Explain IR drop, electromigration, and the role of power-grid design and decoupling.

6. Select appropriate analysis views and prioritize timing, noise, and power-integrity fixes.

7. Evaluate the limitations of deterministic sign-off and the value of statistical methods.

1. Timing Closure as a System Problem

A synchronous path consists of a launching sequential element, combinational logic, interconnect, and a capturing sequential element. The principal timing constraints are setup and hold. Setup requires data to arrive sufficiently before the active capture edge; hold requires data to remain stable sufficiently after that edge.

For a simplified setup check, the required arrival time is

\[

T_{clk}+T_{skew}-t_{setup}-U

\]

and the arrival time is

\[

t_{cq,max}+t_{comb,max}+t_{uncertainty}.

\]

Thus, setup slack may be written as

\[

S_{setup}=T_{clk}+T_{skew}-t_{setup}-U-(t_{cq,max}+t_{comb,max}).

\]

Here, \(T_{clk}\) is the clock period, \(T_{skew}=t_{capture\ clock}-t_{launch\ clock}\), \(t_{setup}\) is the capture flip-flop setup time, \(U\) represents applicable clock uncertainty, \(t_{cq,max}\) is maximum clock-to-Q delay, and \(t_{comb,max}\) includes cell and interconnect delay. A path passes setup if slack is non-negative. The expression assumes a single-cycle path, a common reference clock, and explicit treatment of skew and uncertainty.

For a same-edge hold check, a useful simplified expression is

\[

S_{hold}=t_{cq,min}+t_{comb,min}-\left(t_{skew}+t_{hold}+U_h\right),

\]

where \(t_{cq,min}\) and \(t_{comb,min}\) are minimum delays, \(t_{hold}\) is the receiving element hold requirement, and \(U_h\) is hold uncertainty. Positive skew, in which the capture clock arrives later than the launch clock, generally makes setup easier but hold harder. This opposing behavior is central to clock-tree optimization.

Timing analysis must distinguish the data path from the clock path. Clock latency, skew, jitter, duty-cycle distortion, and clock reconvergence all affect the check. A timing report should therefore be read as a physical argument: which cells and wires dominate delay, which clock edges are compared, what derates were applied, and whether the path is functionally valid?

Timing Terminology

• Arrival time: time at which a signal reaches a timing point.
• Required arrival time: latest or earliest permitted arrival, depending on the check.
• Slack: required time minus arrival time for setup-style checks; the sign convention must be verified in the tool report.
• Critical path: path with the most limiting slack under a specified analysis view.
• False path: a path excluded because no valid functional transition can propagate between its endpoints under the stated operating assumptions.
• Multicycle path: a path intentionally allowed more than one clock cycle, with correctly specified setup and hold relationships.
• Clock uncertainty: margin representing jitter, modeling error, and other clock-related uncertainty.

False-path and multicycle constraints are not performance fixes. An incorrect exception can hide a silicon failure and is therefore a design-governance issue requiring functional justification, review, and regression testing.

2. Static Timing Analysis and Timing Graphs

STA represents a circuit as a directed graph. Pins and timing points are vertices, while timing arcs are edges with delay and constraint information. Unlike dynamic simulation, STA does not require a set of input vectors to enumerate paths. It propagates timing bounds through all graph paths subject to clock and exception constraints.

For each timing point, STA propagates early and late arrival times. Maximum-delay analysis is used primarily for setup; minimum-delay analysis is used primarily for hold. Cell delay is characterized as a function of input slew, output capacitance, voltage, temperature, and sometimes input transition state. Interconnect delay is extracted from parasitic resistance and capacitance, often using distributed RC models.

A timing engine must also account for reconvergent clocks and data. Common-path pessimism removal (CPPR) recognizes that a common clock segment cannot simultaneously experience the worst launch and worst capture variations when the physical segment is shared. Removing this artificial pessimism can recover realistic slack, but it must be applied consistently with the variation model.

Timing optimization has several levers:

• cell upsizing reduces delay but increases area, leakage, input capacitance, and power;
• buffering improves transition and fanout but adds delay, area, and dynamic power;
• logic restructuring can reduce logic depth but may increase switching activity or verification complexity;
• useful clock skew deliberately changes clock arrival times;
• placement and routing reduce wire length, coupling, and resistance;
• threshold-voltage selection trades speed against leakage.

A robust optimization addresses the physical cause rather than merely inserting large cells. For example, repeated upsizing of a driver may fail when the dominant problem is long resistive interconnect or excessive coupling.

3. Multi-Mode Multi-Corner Analysis

A design operates in several functional modes: mission operation, scan shift, scan capture, memory test, low-power states, retention, and sometimes safety or debug modes. Each mode changes clocks, constraints, power states, and legal activity. A process-voltage-temperature (PVT) corner describes manufacturing and environmental conditions, while an analysis view combines a mode with a corner and a timing methodology.

Typical setup analysis uses a slow process, low voltage, and high temperature because transistor drive is reduced and interconnect behavior may be unfavorable. Typical hold analysis uses a fast process, high voltage, and low temperature because minimum delays are small. These are tendencies, not universal laws: advanced interconnect models, temperature inversion, low-voltage behavior, and library characterization can change the worst corner.

An MMMC setup should include:

1. all functional and test modes that can be active in silicon;

2. setup and hold views for each relevant PVT condition;

3. RC corners representing minimum, typical, and maximum parasitic conditions;

4. voltage-domain and power-state assumptions;

5. OCV or statistical derating methodology;

6. clock definitions, generated clocks, exceptions, and uncertainty;

7. sign-off criteria for timing, noise, and reliability.

The number of views can become large. View reduction is acceptable only when an equivalence argument shows that omitted views cannot be worse for the metric being checked. Correlation between corners should not be assumed without physical or statistical justification.

Worked Example: Setup and Hold

Consider a single-cycle path with a 1.00 ns clock period. The launch clock reaches its register at 0.08 ns and the capture clock at 0.12 ns, so skew is +0.04 ns. Let \(t_{cq,max}=0.12\) ns, combinational maximum delay be 0.70 ns, setup time be 0.08 ns, and setup uncertainty be 0.05 ns. Then

\[

S_{setup}=1.00+0.04-0.08-0.05-(0.12+0.70)=0.09\text{ ns}.

\]

The setup check passes with 90 ps slack.

For hold, suppose \(t_{cq,min}=0.06\) ns, minimum combinational delay is 0.03 ns, hold time is 0.04 ns, hold uncertainty is 0.02 ns, and skew remains 0.04 ns:

\[

S_{hold}=0.06+0.03-(0.04+0.04+0.02)=-0.01\text{ ns}.

\]

The path has a 10 ps hold violation despite passing setup. Adding a small delay element to the data path, or modifying clock skew, may repair hold; simply increasing the clock period will not repair a same-edge hold violation.

4. Variation and On-Chip Variation Models

Manufacturing variation includes die-to-die variation, wafer-level variation, within-die spatial variation, and random local variation. Environmental variables such as voltage and temperature also vary spatially and temporally. Timing sign-off must model both systematic and random components.

A basic OCV method applies early and late derating factors to cell and interconnect delays. For a setup path, launch-side and capture-side clock delays may receive different derates from data delays. The exact assignment is methodology-dependent; the essential principle is to represent a physically plausible combination of fast and slow conditions rather than apply one undifferentiated margin.

Advanced OCV (AOCV) makes derates dependent on logic depth and sometimes physical distance. Random variation averages partially across multiple stages, whereas systematic variation may remain correlated. Parametric OCV (POCV) expresses delay as a nominal value plus a variation distribution, commonly using a mean and standard deviation or a sensitivity-based model. A simplified linear model is

\[

D=D_0+\sum_i s_i\Delta p_i,

\]

where \(D_0\) is nominal delay, \(p_i\) are physical or electrical parameters, \(\Delta p_i\) are their deviations, and \(s_i=\partial D/\partial p_i\) are sensitivities. If parameter deviations are jointly Gaussian with covariance matrix \(\Sigma\), the approximate delay variance is

\[

\sigma_D^2=\mathbf{s}^{T}\Sigma\mathbf{s}.

\]

This first-order model assumes sufficiently small perturbations and locally linear delay response. It is not a substitute for Monte Carlo simulation when distributions are strongly non-Gaussian or nonlinear.

Statistical timing treats arrival and required times as random variables. A path mean and variance depend on shared sources: two paths with common clock segments are correlated. Ignoring correlation can produce either excessive pessimism or unsafe optimism. Quantile-based sign-off also requires a stated target, such as a specified tail probability, and a validated distributional model. “Three sigma” is not automatically a universal guarantee, particularly when many millions of timing endpoints are considered or when distributions have heavy tails.

Variation-aware design practices include regular placement, matched clock structures, reduced sensitivity to supply noise, adequate voltage margin, local decoupling, and avoidance of unnecessarily deep logic on critical paths. Designers should track whether a violation is dominated by global corner uncertainty, local random variation, or a systematic spatial gradient because each cause suggests a different remedy.

5. Crosstalk and Signal Integrity

Crosstalk is capacitive or inductive interaction between neighboring interconnects. In most contemporary on-chip designs, capacitive coupling is the dominant concern. A switching aggressor changes the effective load seen by a victim net. Depending on transition direction and timing, crosstalk can cause a victim glitch or alter its transition time.

For a simplified capacitive model, the coupling current is

\[

i_c=C_c\frac{d(V_a-V_v)}{dt},

\]

where \(C_c\) is coupling capacitance, and \(V_a\) and \(V_v\) are aggressor and victim voltages. If the victim is temporarily quiet, a fast aggressor transition can inject charge and produce a noise pulse. The pulse magnitude depends on coupling capacitance, victim capacitance, driver impedance, neighboring transitions, and the duration of alignment.

Crosstalk effects are classified as:

• functional noise: a glitch large enough to be interpreted by a receiving gate or storage element;
• crosstalk delay: an aggressor transition slows or speeds a victim transition, changing timing;
• clock noise: coupling affects clock arrival, duty cycle, or jitter;
• false switching and power impact: glitches create unnecessary dynamic power.

Worst delay often occurs when an aggressor switches in the opposite direction to the victim, increasing the effective capacitive burden. Best delay can occur when both switch in the same direction. Timing analysis must use transition windows: an aggressor that switches far outside the victim’s sensitive interval may have little effect.

Signal-integrity remedies include increased spacing, shielding, shorter parallel runs, layer changes, controlled routing order, stronger or weaker drivers where appropriate, and victim or aggressor buffering. Shielding reduces coupling but consumes routing resources and may increase capacitance. Upsizing an aggressor can worsen noise by increasing edge rate, even if it improves its own delay. Therefore, noise repair must evaluate both amplitude and timing consequences.

Noise analysis should distinguish a physically possible glitch from a logically observable failure. Noise margins, inertial filtering, receiving-cell behavior, pulse width, and sequential aperture all matter. Nevertheless, relying on functional masking without a characterized and reviewed argument is unsafe for clocks, resets, asynchronous controls, and safety-critical signals.

6. Power Integrity: IR Drop and Ground Bounce

A power distribution network (PDN) delivers current from package and bumps through metal layers to standard cells, memories, and analog blocks. Voltage drop occurs because the PDN has resistance and inductance. The resistive component is commonly expressed as

\[

V_{IR}=IR,

\]

where \(I\) is current through a segment and \(R\) is its resistance. For a uniform metal segment,

\[

R=\rho\frac{L}{Wt},

\]

where \(\rho\) is resistivity, \(L\) is length, \(W\) is width, and \(t\) is thickness. This expression assumes approximately uniform temperature and material properties and neglects contact-specific effects.

Dynamic supply noise also includes inductive behavior, approximated by \(V_L=L\,di/dt\), where \(L\) is effective inductance. Package parasitics, bumps, vias, and simultaneous switching determine the actual waveform. Static IR analysis uses average or steady-state current; dynamic IR analysis uses time-varying activity and is essential for bursty logic, clock edges, memories, and power-domain transitions.

Voltage loss reduces logic noise margin and usually increases propagation delay. It can also increase short-circuit current, worsen clock skew, corrupt memories, and cause analog performance degradation. A timing sign-off that uses ideal supply voltage can therefore be materially optimistic.

PDN design practices include wide upper metal straps, sufficient via arrays, distributed power rings, robust bump assignment, balanced current paths, and early floorplanning. Macros create blockages and current concentrations; power planning must examine both average current density and transient hotspots.

Decoupling Capacitors

A decoupling capacitor supplies short-duration current locally. The idealized relation is

\[

\Delta V=\frac{\Delta Q}{C}=\frac{I\Delta t}{C},

\]

where \(C\) is capacitance, \(I\) is transient current, and \(\Delta t\) is the interval over which the capacitor supplies that current. Real effectiveness is limited by equivalent series resistance, inductance, self-resonant frequency, leakage, area, and connection impedance. On-chip decaps are valuable for high-frequency local noise but consume area and may increase leakage or reduce routing flexibility. They are not a replacement for adequate grid resistance and package design.

7. Electromigration and Reliability

Electromigration is the movement of metal atoms caused by momentum transfer from conducting electrons. It can create voids, increasing resistance and eventually causing an open circuit, or hillocks that create shorts. Risk increases with current density, temperature, line geometry, material properties, and stress duration.

A commonly used empirical relationship is Black’s equation:

\[

\text{MTTF}=A J^{-n}\exp\left(\frac{E_a}{kT}\right),

\]

where MTTF is mean time to failure, \(A\) is a technology-dependent constant, \(J\) is current density, \(n\) is an empirically fitted exponent, \(E_a\) is activation energy, \(k\) is Boltzmann’s constant, and \(T\) is absolute temperature. The equation is an empirical lifetime model, not a universal physical law; its parameters and allowable use are found from technology qualification data.

EM analysis must consider average current, RMS current, peak current, bidirectional effects, temperature, via arrays, and current crowding. Foundry rules may specify separate limits for signal wires, clock wires, power rails, and vias. A wider wire, parallel strap, additional via, reduced current, or lower temperature can improve margin. However, simply widening one segment may move the hotspot to a neighboring bottleneck.

Self-heating and EM are coupled: higher current raises temperature, which accelerates degradation and changes resistance. Sign-off should therefore use the foundry’s approved reliability methodology and lifetime target rather than extrapolate casually from generic equations.

8. Integrated Closure Methodology

Timing, noise, and power integrity should be closed iteratively. A practical sequence is:

1. validate clocks, modes, exceptions, libraries, parasitics, and voltage domains;

2. perform preliminary STA and identify dominant path classes;

3. build and analyze the PDN before late physical optimization;

4. extract realistic RC and run crosstalk-aware timing and noise analysis;

5. apply variation, CPPR, voltage-drop-aware libraries, and reliability checks;

6. repair violations using the smallest physically credible intervention;

7. rerun all affected views and regression checks;

8. review residual risk, not merely worst slack.

A useful triage table classifies a violation by symptom and cause. A setup failure with large wire delay suggests placement, routing, or buffering. A hold failure concentrated in fast corners suggests minimum-delay balancing or clock methodology. A path that fails only with dynamic IR drop suggests PDN weakness or activity concentration. A noise failure on a long parallel route suggests shielding or spacing. An EM failure at a via array suggests current crowding rather than insufficient transistor sizing.

Fixes must be checked for side effects. A stronger driver may improve setup while increasing coupling and dynamic power. A delay buffer may repair hold but worsen IR drop and area. A clock-skew adjustment may improve one endpoint while harming another. Decap insertion may reduce noise but increase leakage and congestion. Closure is consequently a constrained optimization problem, not a single-slack maximization exercise.

9. Illustrative Case Study: High-Speed Network Processor Block

Background

Consider an illustrative 5 nm network-processor block operating at 1.2 GHz, with a nominal period of 833 ps. The block contains wide datapaths, large register files, multiple clock domains, and a dense mesh of local interconnect. It must pass mission, scan-capture, and low-power retention modes.

Problem

Initial sign-off showed +18 ps nominal setup slack on the worst path but -42 ps setup slack under variation-aware, crosstalk-enabled analysis with dynamic IR drop. A separate scan-capture view showed -27 ps hold slack. Noise analysis identified glitches on a reset-control net, and EM analysis found excessive current density in a narrow via stack near a memory macro.

Analysis

Path tracing showed that the setup failure was not caused mainly by logic depth. The path crossed a congested channel with long parallel routing. An aggressor switching in the opposite direction increased victim delay. The local supply waveform simultaneously dropped by 55 mV during a clock-aligned burst. Library characterization indicated that this voltage loss increased the critical cell delay. The nominal analysis had included neither effect.

The hold failure occurred only in a fast scan corner. Positive capture skew and a very short data path combined to violate the minimum-delay requirement. The reset glitch was caused by capacitive coupling from a high-activity clock-enable bus. The EM hotspot was concentrated at a via transition rather than uniformly distributed along the metal wire.

Approach and Solution

The physical design team shortened the critical parallel run, added spacing near the victim, and moved a shield to a higher-quality reference connection. A moderate driver adjustment, rather than aggressive upsizing, restored transition quality without creating excessive noise. Two local power straps and an additional via array reduced the dynamic drop. Targeted decap was added near the burst-active logic after checking leakage and placement blockage.

For scan hold, a small delay cell was inserted on the data path, and the scan clock tree was rebalanced. The reset net was rerouted with shielding and verified for pulse width at all receiving elements. The memory-adjacent via stack was widened and supplemented with parallel vias, followed by renewed EM extraction.

Outcome

The final analysis produced +11 ps worst setup slack, +8 ps worst hold slack, acceptable noise margins, and EM compliance at the required lifetime. Importantly, the nominal setup slack decreased slightly because the solution added capacitance, but the robust worst-case margin improved substantially. This illustrates why sign-off quality should be judged across all required views rather than by nominal timing alone.

Learning Points

1. Crosstalk and IR drop can interact and must not always be analyzed independently.

2. The most effective repair often targets routing topology or the PDN rather than cell size.

3. A timing exception or optimistic nominal corner cannot replace physically justified sign-off.

4. Localized EM failures require current-path analysis, including vias and transitions.

5. Every fix requires regression over timing, noise, power, area, leakage, and reliability.

10. Challenges, Governance, and Contemporary Developments

Advanced nodes increase modeling uncertainty. Finite library characterization grids, incomplete activity information, package-model uncertainty, temperature gradients, and aging make precise prediction difficult. Correlated variation and common-path effects complicate statistical analysis. Designers must document assumptions, tool versions, sign-off decks, waivers, and ownership of exceptions.

AI and machine learning are increasingly used to rank timing paths, predict congestion, select cells, optimize floorplans, and identify likely IR-drop hotspots. Such systems can accelerate exploration, but their recommendations require constraint-aware verification. A model trained on one technology or design style may not generalize, and an apparently good objective value can hide an unexamined reliability or test-mode failure. Human review remains essential for safety, security, and sign-off accountability.

Contemporary methodologies increasingly combine voltage-drop-aware timing, aging-aware timing, spatially correlated variation, package-chip co-analysis, and statistical yield estimation. Chiplet systems and advanced packaging add inter-die power and timing interactions. Standards and foundry rules should govern allowable current density, reliability targets, derating, and sign-off evidence; generic textbook limits must never override qualified process documentation.

Best Practices

• Define clocks, modes, exceptions, and voltage states early and review them functionally.
• Use extracted parasitics and variation-aware analysis before declaring closure.
• Analyze setup, hold, noise, IR drop, and EM as coupled constraints.
• Prefer root-cause physical fixes over indiscriminate cell upsizing.
• Apply CPPR and statistical correlation consistently with the approved methodology.
• Treat waivers as controlled engineering decisions with documented evidence.
• Validate dynamic activity assumptions and include realistic package models.
• Recheck all views after every significant ECO.
• Preserve reproducibility through versioned libraries, scripts, constraints, and reports.

Chapter Summary

Robust VLSI closure requires more than nominal timing analysis. STA evaluates setup and hold through arrival and required times, while MMMC extends the analysis across functional modes, PVT conditions, parasitic corners, and reliability assumptions. OCV, AOCV, and statistical models represent the spatial and random nature of variation; correlation and CPPR are necessary to avoid misleading pessimism or optimism.

Crosstalk changes signal delay and can create functional noise. IR drop and package inductance alter the voltage delivered to cells, thereby affecting delay, noise margin, and reliability. Decoupling helps transient behavior but cannot compensate for a weak power grid. Electromigration imposes lifetime limits that depend on current density and temperature. The most reliable closure strategy is iterative and integrated: realistic extraction, variation-aware timing, crosstalk analysis, voltage-drop-aware libraries, EM checking, targeted physical repair, and complete regression across all views.

Key Terms

Static timing analysis: Vectorless timing analysis using a timing graph and library constraints.

Setup time: Minimum interval by which data must precede the active capture edge.

Hold time: Minimum interval for which data must remain stable after the capture edge.

Slack: Difference between permitted timing and analyzed timing.

MMMC: Analysis across multiple modes, process-voltage-temperature corners, and constraint views.

OCV: On-chip variation modeling using early and late timing derates.

AOCV: Variation modeling whose derates depend on depth or physical context.

POCV: Parametric variation modeling based on sensitivities and statistical distributions.

CPPR: Removal of artificial pessimism on shared clock paths.

Crosstalk: Electrical interaction between neighboring interconnects.

Aggressor: Net whose transition influences a neighboring victim.

Victim: Net affected by coupling from another net.

IR drop: Voltage loss caused primarily by current flowing through PDN resistance.

Ground bounce: Supply or ground fluctuation caused by transient current and inductance.

Decoupling capacitor: Local charge reservoir that reduces transient voltage disturbance.

Electromigration: Current-driven movement of metal atoms that can cause failure.

Current density: Current per unit conductor cross-sectional area.

Noise margin: Tolerable voltage disturbance before logic interpretation fails.

Timing exception: Constraint such as a false path or multicycle path that modifies path analysis.

Statistical timing: Timing analysis that represents delay and constraints as random variables.

Review Questions

Short Answer Questions

1. Why can a path pass setup while failing hold?

2. What is the purpose of MMMC analysis?

3. Distinguish crosstalk noise from crosstalk delay.

4. Why is CPPR used in clock analysis?

5. State two limitations of on-chip decoupling capacitors.

Long Answer Questions

1. Derive the simplified setup-slack expression and explain the role of skew and uncertainty.

2. Compare OCV, AOCV, and POCV, including their assumptions and appropriate applications.

3. Explain how power-distribution resistance, inductance, and activity affect timing and logic reliability.

4. Discuss the mechanisms of crosstalk and evaluate physical design remedies.

5. Develop an integrated sign-off methodology for a high-performance SoC.

Analytical / Application Questions

1. A path has a 1.25 ns period, +0.05 ns skew, 0.10 ns setup time, 0.06 ns uncertainty, 0.15 ns clock-to-Q delay, and 0.91 ns combinational delay. Calculate setup slack and determine whether the path passes.

2. A local burst draws 180 mA for 20 ps from an idealized 90 pF decoupling capacitor. Estimate the voltage change, ignoring ESR and ESL, and explain why the practical value may differ.

3. A setup violation appears only after crosstalk and dynamic IR-drop analysis. Propose a diagnostic sequence that separates routing coupling, PDN weakness, clock effects, and variation as possible causes.

Multiple Choice Questions with Answers

Question 1

Which condition generally makes a same-edge hold check more difficult?

A. Positive clock skew

B. A longer clock period

C. Lower capture-clock latency with unchanged launch latency

D. Increasing minimum data-path delay

Correct Answer: A. Positive clock skew

Question 2

What does CPPR primarily remove?

A. Real combinational delay

B. Artificial pessimism on a shared clock path

C. All process variation

D. Crosstalk noise on data nets

Correct Answer: B. Artificial pessimism on a shared clock path

Question 3

For a simplified setup check, which delay is normally critical?

A. Minimum combinational delay

B. Maximum combinational delay

C. Minimum hold time only

D. Average leakage current

Correct Answer: B. Maximum combinational delay

Question 4

In capacitive crosstalk, the coupling current is proportional to:

A. The integral of voltage divided by resistance

B. The derivative of the voltage difference between aggressor and victim

C. The absolute victim voltage only

D. The clock period only

Correct Answer: B. The derivative of the voltage difference between aggressor and victim

Question 5

Which expression represents resistive IR drop?

A. V=IR

B. V=I/R

C. V=R/I

D. V=I+R

Correct Answer: A. V=IR

Question 6

A decoupling capacitor supplies 100 mA for 10 ps. Ignoring parasitics, what capacitance limits the voltage change to 10 mV?

A. 10 pF

B. 50 pF

C. 100 pF

D. 1 nF

Correct Answer: C. 100 pF

Question 7

Which model makes variation derates dependent on logic depth or physical context?

A. Ideal-delay modeling

B. AOCV

C. Boolean minimization

D. Nominal RC extraction

Correct Answer: B. AOCV

Question 8

What is a likely consequence of excessive electromigration?

A. Permanent reduction in metal resistance through healing

B. Void formation and eventual open-circuit failure

C. Elimination of supply noise

D. Improved clock duty cycle

Correct Answer: B. Void formation and eventual open-circuit failure

Question 9

Which repair is most directly appropriate for a short-data-path hold violation?

A. Increase the clock period

B. Insert controlled delay in the data path

C. Reduce all wire spacing

D. Remove clock uncertainty without justification

Correct Answer: B. Insert controlled delay in the data path

Question 10

If a timing path fails only when dynamic IR drop is enabled, the first physical concern should be:

A. The Boolean truth table

B. The local power-delivery network and activity concentration

C. The number of scan test patterns only

D. The absence of a false-path constraint in every mode

Correct Answer: B. The local power-delivery network and activity concentration