5. Sequential Circuits, Clocking, and On-Chip Memory

Introduction and Context

Digital systems are not composed only of logic that computes an output from present inputs. Processors, communication controllers, digital filters, memories, and control units must also retain information, recognize sequences, and change state at controlled instants. These functions are provided by sequential circuits. Unlike combinational circuits, whose outputs depend only on current inputs, sequential circuits depend on both current inputs and stored history.

Storage introduces an essential timing dimension into VLSI design. A circuit must determine when data is captured, how long it must remain stable, how clocks are delivered, and how independently timed subsystems exchange information. At the physical level, these requirements are affected by propagation delay, clock skew, jitter, process variation, supply voltage, temperature, and noise. At the architectural level, the designer must choose suitable storage elements and memory organizations while balancing speed, area, power, reliability, and testability.

This chapter develops the behavior and implementation of latches, flip-flops, registers, finite-state machines, clock networks, clock-domain crossings, and commonly used on-chip memories. SRAM, DRAM, ROM, register files, and memory peripheral circuits are considered not as isolated devices but as components of complete VLSI systems.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Distinguish latches, flip-flops, registers, and state machines and explain their operating behavior.

2. Derive and interpret setup-time, hold-time, clock-to-Q, skew, and jitter constraints.

3. Explain metastability and design safe clock-domain crossing structures.

4. Analyze clock-distribution architectures and their power, skew, and reliability implications.

5. Compare SRAM, DRAM, ROM, and register-file organizations.

6. Explain the operation of bit cells, sense amplifiers, decoders, precharge circuits, and write drivers.

7. Select sequential and memory structures for practical VLSI applications.

8. Evaluate design risks, verification requirements, and emerging implementation trends.

Storage Elements: From Transparency to Edge-Controlled State

Latches

A latch is level-sensitive. When its enable signal is active, the latch is transparent: changes at the input can propagate to the output. When the enable becomes inactive, the last input value is retained. A commonly used positive-level D latch can be described as

Q(next) = D when CLK = 1; Q(next) = Q when CLK = 0.

A CMOS latch is often constructed from transmission gates and inverters, or from feedback inverter structures. The transmission-gate implementation provides a relatively direct relationship between transistor sizing, delay, and signal integrity. Latches can be efficient in area and can support time borrowing, because data arriving during part of the active clock phase may still be captured. Their transparency, however, complicates timing analysis and may permit unintended race paths if the design is not carefully constrained.

Flip-flops

A flip-flop is generally edge-triggered. It samples its input near a clock transition and retains the sampled value until the next active edge. The classic master-slave flip-flop consists of two latches controlled by complementary clock phases. A positive-edge-triggered device uses a master latch that is transparent during the low phase and a slave latch that is transparent during the high phase. The resulting structure prevents the input from continuously propagating to the output during the active phase.

Practical flip-flops may use transmission gates, dynamic nodes, pulse-triggered structures, or compact static topologies. Important implementation metrics include clock-to-Q delay, setup and hold time, data-to-output delay, clock pin capacitance, area, leakage, energy per transition, and robustness to low voltage. A smaller flip-flop may have lower area but greater delay or reduced noise margin. High-performance libraries therefore provide multiple variants, including low-power, high-speed, scan-enabled, and high-drive cells.

Registers and specialized storage

A register is an array of storage elements operated under a common control scheme. An n-bit register contains n latches or flip-flops and may include synchronous load, reset, enable, or arithmetic functions. Shift registers move data serially and are used in serial interfaces, delay lines, scan testing, and pipeline control. Counters are registers with feedback logic that generates a prescribed sequence.

Reset may be synchronous or asynchronous. A synchronous reset changes state only at the active clock edge and is usually easier to integrate into a synchronous timing methodology. An asynchronous reset acts independently of the clock and is useful for bringing a system to a known state, but its release must be synchronized; otherwise, different storage elements can leave reset at different effective times.

Finite-State Machines

A finite-state machine (FSM) represents a system whose future behavior depends on its current state and inputs. The state register stores the current state, combinational logic computes the next state, and output logic produces outputs. In a Moore machine, outputs depend only on state; in a Mealy machine, outputs depend on state and current inputs.

The basic synchronous timing relationship is

Tclk ≥ tCQ + tcomb,max + tsetup + tskew + tjitter,

where Tclk is the clock period, tCQ is the launching flip-flop clock-to-Q delay, tcomb,max is the maximum combinational delay, tsetup is the receiving flip-flop setup time, and tskew and tjitter represent timing uncertainty. State encoding affects area, switching power, output decoding, and fault behavior. Binary encoding minimizes the number of state bits for many-state machines, while one-hot encoding can simplify next-state logic and improve speed at the expense of more storage elements. Gray encoding is useful when only one state bit should change between adjacent states, particularly in some counter and clock-domain crossing applications.

FSM design should include explicit treatment of illegal states, reset behavior, input synchronization, and output glitches. In safety-critical or highly reliable systems, illegal-state recovery logic can force the machine back to a valid state. Formal verification is especially valuable for checking reachability, deadlock, mutual exclusion, and protocol properties.

Timing Constraints and Metastability

Setup and hold requirements

A receiving storage element requires the data input to be stable for a period before the active clock edge, called setup time, and for a period after that edge, called hold time. If either condition is violated, the output may be delayed, incorrect, or metastable.

For a same-clock path, the setup constraint is commonly expressed as

Tclk ≥ tCQ,max + tPD,max + tsetup − tskew,

with sign conventions depending on the definition of skew. A clock arriving later at the receiving element generally gives additional setup margin but can reduce hold margin. The hold constraint is approximately

tCQ,min + tPD,min ≥ thold + tskew.

Unlike setup violations, hold violations cannot normally be repaired by reducing the clock frequency. They require changes to the data path, clock skew, or cell selection. Typical remedies include inserting delay buffers, using slower cells, increasing routing length deliberately, or modifying the clock tree.

Clock uncertainty includes both skew and jitter. Skew is the difference in clock arrival time between two sequential elements. Jitter is temporal variation of a clock edge relative to its ideal position. Process, voltage, and temperature variations make these quantities dependent on operating conditions, so sign-off must use appropriate corners and modes.

Metastability

When an asynchronous or insufficiently timed input is sampled, the internal regenerative node of a flip-flop can enter a state between logic zero and one. It may eventually resolve to either value after an unpredictable time. This phenomenon is metastability. It cannot be eliminated completely by circuit design, but its probability can be reduced to an acceptable level.

A standard mitigation for a single-bit control signal is a two-flip-flop synchronizer. The first flip-flop may become metastable, while the second samples it after approximately one clock period, allowing additional resolution time. The mean time between observable failures increases approximately exponentially with the available resolution time and depends on the receiving clock frequency, input transition rate, and flip-flop technology. Synchronizer flip-flops should be physically placed close together and characterized for metastability performance.

A synchronizer is not sufficient for a multi-bit data bus, because individual bits can resolve in different cycles. Multi-bit transfer requires a protocol such as a handshake, source-synchronous transfer, asynchronous FIFO, or Gray-coded pointer scheme. A pulse crossing clock domains may be missed if it is narrower than the receiving clock period; pulse stretching, toggle synchronizers, or request-acknowledge handshakes are safer alternatives.

Clock Generation and Distribution

The clock is one of the largest sources of dynamic power in a modern VLSI system because it drives many capacitive inputs and switches every cycle. A clock network includes a source, possibly a phase-locked loop or clock-generation circuit, buffers, interconnect, and gating structures.

A clock tree distributes the source through branching buffers. Balanced trees seek to minimize skew, while useful-skew methodologies intentionally adjust arrival times to improve critical-path performance. Clock meshes distribute the signal through a dense network and can offer strong tolerance to local variation, but they require substantial routing resources and power. Hybrid tree-mesh structures combine these properties.

Clock gating reduces dynamic power by preventing unnecessary switching in inactive blocks. An integrated clock-gating cell typically latches the enable signal during the inactive clock phase and then gates the clock with an AND or OR function. Directly gating a clock with an ordinary combinational signal can create glitches and is unsafe. Clock gating must also be verified for minimum pulse width, test operation, wake-up behavior, and interactions with reset.

Clock distribution is affected by interconnect resistance and capacitance, buffer delay, electromagnetic coupling, supply noise, and on-chip variation. A professional clock-tree design therefore considers skew, insertion delay, slew, duty-cycle distortion, local variation, electromigration, and power integrity rather than frequency alone.

Clock-Domain Crossing

A clock-domain crossing (CDC) occurs when information passes between circuits driven by unrelated or differently phased clocks. CDC errors can be intermittent and difficult to reproduce in simulation because metastability is analog and timing-dependent.

For a one-way control transfer, a two-flop synchronizer is suitable when latency is acceptable. For event transfer, a toggle-based synchronizer converts an event into a state change that remains present until detected. For reliable data transfer, a four-phase or two-phase handshake provides explicit request and acknowledgment. Asynchronous FIFOs are preferred for streams because they decouple source and destination rates and provide buffering. Their read and write pointers are commonly Gray-coded so that only one bit changes at each increment; synchronized pointers then allow safe full and empty detection.

CDC design requires architectural intent. The designer should identify every crossing, classify the transferred object, select a protocol, constrain false or asynchronous paths appropriately, and verify the protocol using structural CDC tools and formal assertions. Marking a path as false without providing a safe protocol only hides a defect.

On-Chip Memory Architectures

Memory design is a balance between density, speed, retention, voltage tolerance, power, and accessibility. A memory array is organized into rows and columns. Row decoders select word lines, column circuits select or multiplex bit lines, and peripheral circuits perform precharge, sensing, writing, timing, and error handling.

SRAM

A conventional six-transistor (6T) SRAM cell contains two cross-coupled inverters and two access transistors. The inverters store complementary values, while the access devices connect the internal nodes to complementary bit lines when the word line is asserted. In standby, the cross-coupled inverters reinforce the stored state without refresh.

During a read, bit lines are usually precharged. Activating the word line causes one bit line to discharge slightly, and a differential sense amplifier detects the small voltage difference. The cell must be strong enough to retain its value during read; this is the read-stability requirement. During a write, the bit-line drivers force the internal nodes to the new state. The access and pull-up transistor strengths must permit write completion. These competing requirements are often summarized using cell ratio and pull-up ratio metrics.

SRAM offers low latency and easy random access, making it suitable for caches, register files, buffers, and small embedded memories. Its area per bit is larger than that of dense dynamic memories, and leakage can be significant in large arrays. Assist techniques, such as word-line boosting, negative bit-line writing, or reduced cell supply during operation, improve low-voltage read and write margins but increase design complexity.

DRAM

A one-transistor, one-capacitor (1T1C) DRAM cell stores charge on a capacitor. The access transistor connects the capacitor to a bit line when the word line is selected. Reading is destructive because charge sharing changes the cell voltage; a sense amplifier detects the small difference and restores the charge. DRAM therefore requires periodic refresh.

The high density of DRAM results from its compact cell, but the sense operation is timing-sensitive and the storage capacitor is vulnerable to leakage. Row activation, precharge, sensing, restoration, and refresh must be coordinated. Embedded DRAM can provide greater density than SRAM, but process integration, retention, refresh power, and manufacturing complexity are important considerations.

ROM and nonvolatile memory distinctions

A mask ROM stores information through fixed device or wiring choices established during fabrication. It offers high density and low standby power for fixed firmware or lookup tables but cannot be modified after manufacture. Programmable ROM families introduce fuses, antifuses, floating-gate devices, or other mechanisms, depending on the technology. Their programming and read mechanisms differ from those of volatile SRAM and DRAM, and their endurance and retention must be evaluated when they are rewritable.

Register files

A register file is a small, fast, multiported memory used in processors and digital signal processors. A two-read, one-write register file may use separate read paths and a write port. Multiporting improves instruction throughput but increases area, bit-line capacitance, and energy. Some register files use replicated arrays, multiplexed bit lines, or specialized multiport cells. Timing, bypass paths, write-through behavior, and simultaneous read/write semantics must be specified precisely.

Memory Peripheral Circuits

The memory cell alone does not determine system performance. Row decoders convert an address into a selected word line. Hierarchical decoders reduce wiring capacitance by dividing selection into predecode and final decode stages. Word-line drivers must provide sufficient voltage and current while limiting transition time and disturbance.

Bit-line precharge circuits establish a known initial condition before a read. Equalization transistors may force complementary bit lines to the same voltage. Sense amplifiers then convert a small differential signal into a full logic level. Latch-type differential sense amplifiers are fast and energy-efficient but require suitable input timing and offset control. Offset, mismatch, noise, and variation can cause sensing errors.

Write drivers impose complementary values on bit lines. Column multiplexers connect selected columns to shared sense and write circuitry, reducing peripheral area at the cost of additional capacitance and delay. Timing generators sequence precharge, word-line activation, sensing, writing, and recovery. Replica bit lines or replica cells can track array delay and generate robust internal timing.

Error-correcting codes are increasingly used in memories. A single-error-correct, double-error-detect code can correct one erroneous bit and identify many two-bit errors. ECC adds storage and encoding/decoding latency, but it improves reliability against soft errors, variation, and aging. Redundancy circuits can replace defective rows or columns using spare elements and programmable repair information.

Applied Scenario: Low-Power Sensor-Processing SoC

Background

Consider an illustrative postgraduate design case: a battery-powered sensor-processing SoC contains a low-frequency sensor interface, a moderate-speed processor, an SRAM scratchpad, and a wireless communication block. The sensor operates from a 32-kHz clock, while the processor and radio use independently generated clocks.

Problem

Sensor events must wake the processor without loss. Sample data must be transferred into the processor domain, and the SRAM must support low-voltage operation. Uncontrolled clock activity would significantly reduce battery life. Initial simulation shows occasional missed events and rare corrupted samples.

Analysis

The sensor event is asynchronous to the processor clock, so a direct pulse connection is unsafe. The sample stream is multi-bit and cannot be synchronized bit by bit. The SRAM operates near the lower supply limit, where read stability and sense-amplifier offset are reduced. Finally, the radio clock continues switching even when no transmission is pending.

Approach

The event is converted into a toggle in the sensor domain and passed through a two-flop synchronizer. The processor detects a change in the synchronized toggle. Sample data is transferred using a request-acknowledge handshake, with the source holding data stable until acknowledgment. For burst transfers, an asynchronous FIFO is used instead. The SRAM employs a characterized low-voltage bit cell, conservative read timing, and, where required, an ECC-protected organization. Clock-gating cells disable the radio and processor sub-blocks when their enables are inactive; wake-up controls are synchronized into each destination domain.

CDC structural checks verify that every crossing has an approved protocol. Static timing analysis covers synchronous paths, while asynchronous paths are constrained according to their protocols rather than simply ignored. Assertions check that requests remain asserted until acknowledgment and that FIFO full and empty conditions are not violated.

Outcome and learning points

The architecture eliminates pulse-loss risk, makes multi-bit transfer explicit, and reduces unnecessary clock switching. The case demonstrates that CDC, clock gating, memory reliability, and timing closure are architectural issues, not merely implementation details. A local fix—such as adding more synchronizer flops to each data bit—would not have solved the fundamental coherency problem.

Design Challenges and Professional Practice

Sequential designs commonly fail because of incomplete reset analysis, accidental combinational feedback, incorrect latch inference, optimistic simulation models, or inadequate timing constraints. Metastability should not be treated as a digital logic value that simulation can faithfully reproduce. CDC review, synchronizer recognition, protocol assertions, and silicon-oriented margin analysis are essential.

Memory design faces additional risks: read disturb, write failure, half-select disturbance, leakage, bit-line coupling, sense-amplifier offset, soft errors, and manufacturing defects. Designers must use statistical variation analysis and memory-specific characterization rather than relying solely on nominal corner simulation.

Professional sign-off requires cooperation among architecture, RTL, physical design, circuit design, verification, test, and reliability teams. Clock and memory structures must be testable. Scan insertion, built-in self-test, redundancy repair, at-speed testing, and diagnosis support manufacturing quality. Security considerations are also relevant: memory contents may leak through side channels, remanence, or fault injection, while clock and reset manipulation can create exploitable states. Appropriate access control, secure initialization, error monitoring, and fault response should be considered in systems handling sensitive information.

Current Developments

Advanced VLSI systems increasingly use multiple voltage and frequency domains, making CDC, power intent, retention, and level shifting central design concerns. Three-dimensional integration and chiplet-based architectures increase the importance of reliable die-to-die clocking and data protocols. Embedded memories are being optimized with assist circuits, adaptive timing, variation-aware sensing, and error correction. Near-memory processing and memory-compute structures seek to reduce data movement, although they introduce new issues in programmability, analog variation, verification, and thermal management.

Machine-learning-assisted design tools are being applied to clock-tree synthesis, placement, memory compiler optimization, and failure prediction. Such tools can improve exploration, but their results still require engineering constraints, formal verification, characterization, and human review. The fundamental principles of stable storage, safe timing, and explicit communication protocols remain unchanged.

Best Practices

A robust sequential and memory design generally follows these practices:

• Define clock, reset, power, and data-transfer domains at the architecture stage.
• Use characterized library cells and approved synchronizer, gating, and memory macros.
• Treat setup and hold analysis as separate obligations.
• Use explicit CDC protocols for every asynchronous crossing.
• Avoid direct combinational clock gating and uncontrolled generated clocks.
• Specify memory read-during-write behavior, initialization, latency, and fault response.
• Verify illegal FSM states, reset release, FIFO boundaries, and handshake persistence.
• Include variation, aging, low-voltage operation, test modes, and reliability in sign-off.
• Use ECC or redundancy when the application requires higher data integrity.

Chapter Summary

Sequential circuits retain state and make digital systems capable of sequencing, control, and computation over time. Latches are level-sensitive, whereas flip-flops capture data at clock edges; registers combine multiple storage elements, and FSMs use state registers with next-state and output logic. Correct operation depends on setup and hold constraints, clock-to-Q delay, skew, jitter, and controlled reset behavior.

Metastability arises when timing requirements are violated, especially during asynchronous transfers. Synchronizers protect single-bit controls, while handshakes, toggles, and asynchronous FIFOs are needed for events and multi-bit data. Clock networks must balance skew, power, slew, reliability, and variation; safe clock gating is an important low-power technique.

SRAM provides fast, stable random access but consumes more area per bit than dense dynamic memory. DRAM achieves high density using charge storage and requires refresh. ROM stores fixed or programmable information, while register files provide fast multiport access. Decoders, precharge circuits, sense amplifiers, write drivers, timing generators, ECC, and redundancy are essential to practical memory operation. Successful VLSI design integrates these circuit techniques with architectural protocols, physical implementation, verification, test, and reliability engineering.

Key Terms

Latch: A level-sensitive storage element that is transparent during an enable phase.

Flip-flop: An edge-triggered storage element that samples data near a clock transition.

Register: An array of storage elements operated as a unit.

Finite-state machine: A synchronous model consisting of states, transitions, inputs, and outputs.

Setup time: The minimum interval for which data must be stable before the active clock edge.

Hold time: The minimum interval for which data must remain stable after the active clock edge.

Clock-to-Q delay: The delay from an active clock edge to a valid flip-flop output.

Clock skew: The difference in clock arrival time at two sequential elements.

Clock jitter: Variation of clock-edge timing from its ideal position.

Metastability: A temporary, unpredictable analog state caused by inadequate sampling timing.

Synchronizer: A circuit that reduces the probability of metastability propagation.

Clock-domain crossing: Transfer of information between circuits using different clocks.

SRAM: Static random-access memory that stores data using a bistable cell.

DRAM: Dynamic random-access memory that stores charge and requires refresh.

ROM: Read-only memory whose stored information is fixed or programmed through a technology-specific mechanism.

Sense amplifier: A circuit that detects and amplifies a small memory bit-line signal.

Precharge: The operation of establishing a known voltage on memory bit lines before access.

Register file: A small, fast memory with one or more read and write ports.

ECC: Error-correcting code used to detect and/or correct memory errors.

Clock gating: A technique that disables clock switching in inactive logic to reduce dynamic power.

Review Questions

Short Answer Questions

1. How does a level-sensitive latch differ from an edge-triggered flip-flop?

2. Define setup time, hold time, clock skew, and clock jitter.

3. Why is a two-flip-flop synchronizer unsuitable for a multi-bit data bus?

4. What is the purpose of precharge in an SRAM read operation?

5. Why does DRAM require refresh?

Long Answer Questions

1. Explain the operation of a master-slave flip-flop and discuss its timing characteristics.

2. Derive the principal setup and hold constraints for a synchronous data path and explain how violations are repaired.

3. Compare binary, one-hot, and Gray state encoding for finite-state machines.

4. Describe the organization and operation of a 6T SRAM cell, including read stability and write ability.

5. Explain the roles of decoders, word-line drivers, sense amplifiers, write drivers, and timing circuits in a memory array.

Analytical / Application Questions

1. A control pulse is generated in a 10-MHz domain and must be observed by a 40-MHz unrelated domain. Select a safe transfer method and justify it in terms of pulse width and metastability.

2. A processor requires two independent reads and one write per cycle from a register file. Discuss at least two implementation choices and analyze their area, timing, and power trade-offs.

3. An SRAM begins failing at low supply voltage during reads but not writes. Identify likely circuit-level causes and propose characterization or assist techniques to diagnose and improve the design.

22. Multiple Choice Questions with Answers

Question 1

Which statement best distinguishes a latch from an edge-triggered flip-flop?

A. A latch stores only analog values, whereas a flip-flop stores digital values.

B. A latch can be transparent during an active level, whereas a flip-flop samples near a clock edge.

C. A latch always requires two clocks, whereas a flip-flop requires one.

D. A latch cannot be used in a register.

Correct Answer: B. A latch can be transparent during an active level, whereas a flip-flop samples near a clock edge.

Question 2

A hold-time violation in a synchronous path is most directly addressed by which change?

A. Reducing the clock frequency

B. Increasing the data-path minimum delay

C. Increasing the functional input frequency

D. Removing the receiving flip-flop

Correct Answer: B. Increasing the data-path minimum delay

Question 3

Why is synchronizing each bit of a multi-bit bus independently unsafe?

A. The bus cannot be connected to flip-flops

B. Each bit may be observed in a different clock cycle

C. Synchronizers work only with analog signals

D. The receiving clock stops during synchronization

Correct Answer: B. Each bit may be observed in a different clock cycle

Question 4

Which circuit is most appropriate for transferring a sustained stream of data between unrelated clock domains?

A. An asynchronous FIFO

B. A single inverter

C. A combinational multiplexer only

D. A single synchronizer on one data bit

Correct Answer: A. An asynchronous FIFO

Question 5

What is the principal reason that an integrated clock-gating cell latches its enable signal?

A. To increase data-path arithmetic precision

B. To prevent glitches from appearing on the gated clock

C. To convert SRAM into DRAM

D. To eliminate setup time from the design

Correct Answer: B. To prevent glitches from appearing on the gated clock

Question 6

During a typical SRAM read, why are complementary bit lines precharged before word-line activation?

A. To establish a known initial condition for differential sensing

B. To erase the stored value permanently

C. To refresh the DRAM capacitor

D. To disable the sense amplifier

Correct Answer: A. To establish a known initial condition for differential sensing

Question 7

Which memory type normally requires periodic refresh because it stores information as capacitor charge?

A. 6T SRAM

B. Mask ROM

C. DRAM

D. Static register file

Correct Answer: C. DRAM

Question 8

In an asynchronous FIFO, Gray-coded pointers are useful because they:

A. Make all pointer bits change simultaneously

B. Ensure only one pointer bit changes between adjacent values

C. Eliminate the need for storage cells

D. Convert a FIFO into a ROM

Correct Answer: B. Ensure only one pointer bit changes between adjacent values

Question 9

Which timing change generally improves setup margin but may worsen hold margin?

A. Making the receiving clock arrive later than the launching clock

B. Increasing the receiving flip-flop hold time only

C. Reducing the data-path delay to zero

D. Removing clock uncertainty from analysis without justification

Correct Answer: A. Making the receiving clock arrive later than the launching clock

Question 10

A memory read occasionally fails at low voltage while the write operation remains reliable. Which issue is especially relevant?

A. Read stability and sense-amplifier offset

B. ROM mask programming temperature only

C. FSM state encoding only

D. Clock-domain frequency ratio only

Correct Answer: A. Read stability and sense-amplifier offset