2. Semiconductor Devices, Fabrication, and Scaling

Introduction and Context

The metal–oxide–semiconductor field-effect transistor (MOSFET) is the basic device underlying modern digital integrated circuits. Logic gates, memories, microprocessors, analog interfaces, sensors, and many mixed-signal systems are constructed from networks of MOS transistors. Consequently, VLSI design cannot be separated from semiconductor-device behavior and manufacturing technology. A circuit designer who treats transistors as ideal switches may obtain a logically correct design that nevertheless fails because of delay, leakage, noise, variability, reliability, or layout constraints.

This chapter develops the device and process concepts needed to connect circuit-level design with physical implementation. It begins with MOS structure and current–voltage behavior, then considers capacitance and dynamic operation. It proceeds to short-channel effects, CMOS fabrication, process design kits, layout rules, interconnect scaling, and advanced transistor structures such as FinFETs and gate-all-around devices. The discussion also emphasizes model limitations and variability, because technology models are abstractions of complex physical processes rather than exact descriptions of every manufactured transistor.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain MOS capacitor operation and the formation of an inversion channel.

2. Derive and interpret the long-channel MOSFET current equations.

3. Relate device capacitances, resistance, and switching delay.

4. Explain short-channel effects and their consequences for VLSI design.

5. Describe the principal steps in a CMOS fabrication flow.

6. Interpret the role of a process design kit and design rules.

7. Analyze the influence of interconnect scaling on circuit performance.

8. Compare planar MOSFETs, FinFETs, and gate-all-around devices.

9. Identify sources of process variability and limitations of compact models.

10. Apply these ideas to practical technology-selection and layout decisions.

From MOS Capacitor to MOSFET

A MOS structure consists of a metal or conducting gate, an insulating oxide or dielectric, and a semiconductor body. For a p-type substrate, a positive gate voltage repels holes from the semiconductor surface. At a sufficiently large voltage, electrons are attracted to the surface, producing an n-type inversion layer. The gate voltage at which strong inversion begins is the threshold voltage, denoted by V_T.

The gate controls the surface potential through the electric field across the oxide. The oxide capacitance per unit area is

C_ox = ε_ox/t_ox,

where ε_ox is the dielectric permittivity and t_ox is the oxide thickness. A thinner dielectric produces stronger electrostatic coupling between gate and channel, although excessively thin dielectrics can increase gate leakage. High-k dielectrics allow a large effective capacitance without requiring a physically ultrathin dielectric.

An n-channel MOSFET is formed by placing two n+ regions, source and drain, in a p-type body. When V_GS is below threshold, no continuous inversion path exists between source and drain. When V_GS exceeds V_T, an electron channel connects the source and drain. The drain-to-source voltage establishes a lateral electric field that causes carriers to move through the channel.

The threshold voltage is influenced by substrate doping, oxide thickness, work-function difference, body bias, and fixed charge. A simplified body-effect relation is

V_T = V_T0 + γ(√(2φ_F + V_SB) − √(2φ_F)),

where V_T0 is the threshold voltage at zero source-to-body bias, γ is the body-effect coefficient, φ_F is the Fermi potential, and V_SB is the source-to-body voltage. Reverse body bias generally increases the threshold voltage of an nMOS device and reduces leakage, while forward body bias can improve speed at the cost of increased leakage and reduced reliability margin.

Long-Channel Current–Voltage Models

The classical square-law model is useful for developing intuition, even though advanced technologies require more sophisticated models. In the gradual-channel approximation, the drain current depends on the local channel charge and electric field.

For an nMOS transistor in the cutoff region, when V_GS < V_T,

I_D ≈ 0,

apart from subthreshold and leakage currents. In the linear or triode region, where V_GS > V_T and 0 ≤ V_DS < V_GS − V_T,

I_D = μ_n C_ox (W/L)[(V_GS − V_T)V_DS − V_DS²/2].

Here μ_n is electron mobility, W is channel width, and L is channel length. The equation shows why increasing W raises current and increasing L reduces current. It also shows that the transistor behaves approximately as a voltage-controlled resistor when V_DS is small.

When V_DS reaches V_GS − V_T, the channel pinches off near the drain. The device enters saturation, and the ideal long-channel current is

I_D = (1/2) μ_n C_ox (W/L)(V_GS − V_T)².

The term V_OV = V_GS − V_T is called the overdrive voltage. Saturation does not mean that the current is independent of all voltages; it means that, in the ideal model, the current is relatively insensitive to further increases in V_DS. Channel-length modulation introduces a dependence on drain voltage:

I_D = (1/2) μ_n C_ox (W/L)(V_GS − V_T)²(1 + λV_DS),

where λ is the channel-length-modulation coefficient. The corresponding output resistance is approximately r_o = 1/(λI_D). Channel-length modulation is important in analog design because it reduces voltage gain.

For a pMOS transistor, the same principles apply with reversed voltage polarities and hole mobility μ_p. Since hole mobility is lower than electron mobility, a pMOS device normally requires greater width than an nMOS device to provide comparable drive strength. This asymmetry influences CMOS inverter sizing.

The square-law model is valuable for hand analysis, first-order sizing, and examination of operating regions. It becomes inaccurate when channel length is short, velocity saturation occurs, mobility depends strongly on field, source and drain series resistance is significant, or quantum and confinement effects become important.

Subthreshold Operation, Leakage, and Power

Even when V_GS is below V_T, a diffusion current flows. In the subthreshold region, the drain current is approximately exponential in gate voltage:

I_D ∝ exp[(V_GS − V_T)/(nV_Thermal)],

where n is the subthreshold-slope factor and V_Thermal is the thermal voltage. The subthreshold slope indicates how effectively the gate turns the device off. A steeper subthreshold characteristic permits lower supply voltage and lower standby leakage, but practical electrostatic limits prevent arbitrary improvement.

Other leakage mechanisms include gate-oxide tunneling, junction leakage, band-to-band tunneling, and gate-induced drain leakage. Leakage becomes especially significant as threshold voltages are reduced to maintain performance at lower supply voltages. In large systems, leakage contributes to standby power and can create thermal feedback: increased temperature raises leakage, which raises power and temperature further.

Dynamic power is commonly approximated by

P_dynamic = α C_L V_DD² f,

where α is the activity factor, C_L is switched capacitance, V_DD is supply voltage, and f is switching frequency. Short-circuit power occurs briefly when both pull-up and pull-down networks conduct during a transition. Total power therefore reflects device currents, capacitances, switching activity, supply voltage, and temperature rather than transistor count alone.

Capacitances and Switching Behavior

MOS capacitances arise from the gate oxide, depletion region, and source/drain junctions. The gate-to-source and gate-to-drain capacitances are bias-dependent because the inversion channel changes with operating region. Overlap capacitances remain even when the channel is absent, because the gate overlaps the source and drain extensions. Junction capacitances are associated with reverse-biased source/body and drain/body junctions.

In the linear region, channel charge is distributed between source and drain. In saturation, pinch-off shifts most incremental channel charge toward the source, changing the effective gate capacitances. This behavior is represented in compact models by bias-dependent capacitance expressions rather than by a single fixed capacitor.

A simple estimate of inverter delay is

t_p ≈ 0.69 R_eq C_L,

where R_eq is an effective conducting resistance and C_L includes gate, diffusion, wire, and load capacitance. This relationship explains several important design strategies: reducing capacitance, increasing drive current, shortening wires, and selecting suitable transistor widths can improve speed. However, increasing width reduces resistance but increases gate and diffusion capacitance. Transistor sizing is therefore an optimization problem rather than a monotonic pursuit of maximum width.

The Miller effect can make the effective capacitance associated with a voltage gain stage substantially larger than its physical capacitance. In digital circuits, capacitive coupling between adjacent wires may produce crosstalk, delay variation, or false switching. Shielding, spacing, buffering, and appropriate layer assignment are common remedies.

Short-Channel Effects

The long-channel model assumes that the electric field along the channel is small compared with the vertical field and that the gate fully controls the channel. As channel length is reduced, these assumptions fail.

Drain-induced barrier lowering (DIBL) occurs when a high drain voltage lowers the source-channel potential barrier. The transistor then conducts more current at a given gate voltage, and the apparent threshold voltage decreases with increasing drain voltage. DIBL increases off-state leakage and reduces noise margins.

Velocity saturation occurs when carrier velocity approaches a maximum imposed by the electric field. In this regime, current does not increase according to the square-law prediction. The benefit of increasing gate overdrive becomes smaller, and delay scaling differs from the long-channel expectation.

Channel-length modulation becomes stronger as the pinch-off region occupies a larger fraction of the channel. Subthreshold leakage rises because the drain has greater electrostatic influence over the source barrier. Gate-induced drain leakage and hot-carrier effects may also become important under high-field conditions.

Short-channel devices may exhibit threshold-voltage roll-off, mobility degradation, source/drain resistance effects, and nonuniform current distribution. These phenomena affect timing, analog gain, leakage, matching, and reliability. At advanced dimensions, variability in line-edge roughness, fin dimensions, metal gates, and random dopant or charge distributions can cause substantial device-to-device differences.

Electrostatic control is a central design objective. The characteristic length of the device should be small relative to the gate length so that the gate, rather than the drain, controls the channel. This motivation led from planar transistors to multi-gate structures.

CMOS Fabrication: From Wafer to Interconnected Circuit

CMOS fabrication uses repeated cycles of deposition, oxidation or dielectric formation, lithography, etching, implantation or diffusion, and cleaning. A simplified process begins with a silicon wafer. Well regions are formed to provide appropriate bodies for nMOS and pMOS devices. Isolation structures, commonly shallow trench isolation, separate neighboring active regions.

Gate dielectric formation is followed by deposition and patterning of the gate material. The gate serves as a self-aligned mask for source and drain formation, which helps maintain precise alignment between the channel and junctions. Lightly doped extensions, sidewall spacers, and heavily doped source/drain regions are formed in sequence to manage electric fields and resistance.

After transistor formation, a silicide may be added to reduce contact and sheet resistance. An interlayer dielectric separates device regions from the first metal layer. Contacts connect source, drain, and gate structures to metal interconnects. Several metal layers, separated by dielectric and connected through vias, distribute signals, power, and clock networks. The final stages include passivation, wafer testing, dicing, packaging, and product testing.

Modern processes use complex patterning schemes, including multiple patterning and extreme ultraviolet lithography in selected layers. Manufacturing is not merely a geometric shrinking exercise. Changes in materials, thermal budgets, stress engineering, contact architecture, and interconnect stacks can affect circuit behavior as much as nominal transistor dimensions.

Process Design Kits and Design Rules

A process design kit (PDK) is the interface between a semiconductor process and electronic-design-automation tools. It normally contains technology files, design-rule decks, device symbols, parameterized cells, compact models, layout-versus-schematic rules, parasitic-extraction rules, and reliability information.

Design rules express manufacturability constraints such as minimum width, minimum spacing, enclosure, extension, contact dimensions, well requirements, density, and antenna restrictions. They are not arbitrary drawing conventions. Each rule reflects lithographic resolution, overlay accuracy, etch behavior, electrical isolation, reliability, or yield considerations.

A typical design flow includes schematic capture, simulation, layout, design-rule checking (DRC), layout-versus-schematic (LVS) verification, parasitic extraction, post-layout simulation, and signoff checks. Electrical-rule checking may identify floating nodes, excessive current density, voltage violations, or well-tap problems. Timing, power integrity, electromigration, antenna, and thermal analyses may also be required for a production design.

The PDK enables portability within a process generation but does not make a design independent of technology. A circuit optimized for one PDK may require substantial redesign for another because transistor models, supply voltages, metal pitches, variability, and reliability limits differ.

Scaling and the Growing Role of Interconnect

Classical scaling aimed to reduce transistor dimensions while lowering supply voltage and maintaining electric-field limits. Dennard scaling predicted simultaneous improvements in density, speed, and power per device under ideal scaling assumptions. In practice, supply voltage and threshold voltage could not continue decreasing proportionally because noise margins, leakage, variability, and reliability imposed constraints.

As transistors became faster, interconnect increasingly dominated system delay. Wire resistance rises as cross-sectional dimensions shrink, while coupling capacitance depends on spacing, dielectric properties, and neighboring activity. A long global wire may therefore become slower than a transistor transition. Repeater insertion, wire sizing, low-k dielectrics, layer selection, and physical floorplanning are essential responses.

Interconnect reliability includes electromigration, stress migration, time-dependent dielectric breakdown, and self-heating. Electromigration is driven by high current density and temperature and can produce voids or hillocks. Power and clock networks require special attention because they carry large currents and influence the behavior of many circuits simultaneously.

Scaling also increases design density and manufacturing sensitivity. A smaller feature may improve area but increase variability or reduce voltage headroom. Technology decisions must therefore balance performance, power, area, manufacturability, reliability, and design cost.

FinFETs and Gate-All-Around Devices

A FinFET uses a thin vertical silicon fin as the channel, with the gate controlling multiple sides of the fin. This multi-gate geometry improves electrostatic control compared with a planar transistor. Effective width is related to the fin height and width, and circuit designers often use quantized numbers of fins rather than arbitrary continuous widths.

FinFETs reduce leakage and short-channel effects, but they introduce new considerations: fin quantization, orientation-dependent mobility, parasitic capacitance, self-heating, fin-width variability, and restricted layout patterns. Standard-cell architecture and transistor sizing must account for these constraints.

Gate-all-around (GAA) devices surround the channel with the gate on all sides. Nanosheet and nanowire structures are prominent implementations. GAA architecture provides stronger electrostatic control and offers flexibility in nanosheet width. It is attractive for continued scaling, although fabrication complexity, contact resistance, thermal management, variability, and design enablement remain significant challenges.

The transition from planar devices to FinFETs and GAA devices illustrates an important principle: scaling changes the design abstraction. A transistor is no longer characterized only by W and L. Geometry, orientation, number of fins or sheets, local interconnect, thermal environment, and layout context all influence performance.

Variability and Model Limitations

Process variability may be systematic or random. Systematic variation results from spatial gradients, lithographic distortion, wafer-level process conditions, and layout-dependent effects. Random variation arises from microscopic fluctuations in dopants, line edges, work function, defects, and material thickness. Temperature and supply variation add further uncertainty during operation.

Important layout-dependent effects include well proximity, shallow-trench isolation stress, implant shadowing, density effects, local interconnect variation, and dummy-feature requirements. In analog circuits, mismatch between nominally identical devices can limit offset, gain, and precision. Common-centroid layout, interdigitation, symmetry, dummy devices, and matched routing reduce systematic mismatch but cannot eliminate random variation.

Compact models such as BSIM represent device behavior using many fitted parameters. They are calibrated against measurements or detailed physical simulations over specified voltage, temperature, geometry, and frequency ranges. A model is therefore valid only within its intended domain. Extrapolating a model to unsupported dimensions or operating conditions can produce misleading results.

Model corners represent combinations such as fast, slow, and typical transistors, process extremes, voltage variation, and temperature. Monte Carlo analysis samples statistical parameter distributions to estimate yield. Neither method guarantees perfect prediction: corners may omit correlations, while statistical results depend on the quality of the assumed distributions and the number of samples.

Applied Case Study: Choosing a Technology for a Low-Power Sensor Interface

Background

Consider an illustrative design team developing a battery-operated sensor interface. The circuit includes a low-noise analog front end, a small digital controller, and an on-chip data converter. The initial specification requires low standby power, moderate sampling speed, reliable operation across temperature, and a compact die area.

Situation and Problem

A nominally advanced technology offers higher transistor density and faster digital logic, but it has lower supply voltage, greater leakage sensitivity, more restrictive layout rules, and limited analog voltage headroom. An older technology offers thicker-oxide devices, larger voltage tolerance, and more mature analog models, but requires greater area and has slower digital logic.

Analysis

The team first identifies the dominant constraints. The sensor remains active for long periods, so leakage and bias-current accuracy matter more than peak digital speed. The analog front end requires sufficient signal swing and transistor output resistance. The digital controller has modest computational requirements. Interconnect length is limited by the small die, so global-wire delay is not the primary concern.

The team compares PDK models across process corners and temperature. It evaluates threshold variation, low-frequency noise, device matching, available passive components, metal resistance, and reliability rules. It also checks whether the advanced process provides suitable thick-oxide or high-voltage devices.

Approach and Solution

The team selects the mature technology for the analog-dominated product and uses low-leakage device options for always-on circuitry. Layout employs common-centroid matching, guard rings where substrate noise requires them, adequate well contacts, and separate supply routing for sensitive analog blocks. Digital logic is sized conservatively rather than optimized for maximum speed. Post-layout extraction is included before final noise and settling simulations.

Outcome

The selected technology produces a larger die but meets standby-current, noise, and temperature requirements with lower design risk. The advanced process remains attractive for a future high-volume version if the digital workload increases or if a suitable analog option becomes available.

Learning Points

Technology selection should be driven by the complete system objective rather than transistor density alone. PDK maturity, model quality, device options, voltage headroom, matching, reliability, and design schedule can outweigh nominal geometric advantage. The case also demonstrates that scaling decisions are architectural and economic decisions, not merely physical ones.

Challenges, Professional Practice, and Emerging Directions

Common mistakes include using square-law equations outside their valid range, ignoring body effect, treating capacitance as constant, estimating delay without extracted interconnect, assuming typical-corner simulation proves yield, and drawing layout that passes schematic simulation but violates density or reliability requirements. Another frequent error is to optimize individual transistor speed while overlooking wire congestion, power delivery, thermal gradients, and clock distribution.

Professional practice requires disciplined version control for PDKs, documented model assumptions, reproducible simulation environments, and clear signoff criteria. Designers must respect foundry confidentiality and licensing restrictions. Safety-critical and high-reliability products require traceable verification, conservative derating, qualification, and compliance with applicable standards. Ethical engineering requires reporting uncertainty and known model limitations rather than presenting nominal simulation as guaranteed product behavior.

Automation is increasingly used in design-rule checking, parasitic extraction, placement, routing, transistor sizing, and statistical optimization. Machine-learning methods can assist surrogate modeling and design-space exploration, but they must be validated against trusted simulations and measurements. An optimization tool may exploit a model error or produce a layout that is mathematically valid but difficult to manufacture. Human review remains necessary for interpretation, corner selection, reliability, and physical plausibility.

Current device development emphasizes gate-all-around architectures, backside power delivery, advanced contact schemes, three-dimensional integration, chiplets, and improved interconnect materials. These developments extend scaling beyond the isolated transistor. Future VLSI engineers must reason simultaneously about device electrostatics, process integration, physical design, packaging, thermal behavior, and system architecture.

Best-Practice Framework for Device-Aware VLSI Design

A robust design approach can be organized as follows:

1. Define performance, power, area, reliability, and yield objectives before selecting a technology.

2. Study the PDK device options, voltage limits, models, design rules, and known restrictions.

3. Use analytical models for intuition, but use validated compact models for quantitative design.

4. Examine all relevant process, voltage, temperature, mismatch, and aging conditions.

5. Include parasitic extraction early enough that physical effects influence architecture.

6. Treat interconnect and power delivery as first-class design objects.

7. Use layout techniques appropriate to matching, noise isolation, density, and reliability.

8. Verify both nominal functionality and statistical manufacturing robustness.

9. Document assumptions, model versions, design margins, and unresolved risks.

10. Reassess technology choice when system priorities change; smaller geometry is not automatically the best choice.

Chapter Summary

MOSFET operation begins with electrostatic control of an inversion channel. The long-channel equations describe cutoff, triode, and saturation behavior and provide useful first-order intuition for current, resistance, and sizing. Real devices exhibit subthreshold conduction, leakage, bias-dependent capacitance, channel-length modulation, velocity saturation, DIBL, and other short-channel effects. These effects influence delay, power, gain, noise, and reliability.

CMOS fabrication combines lithography, deposition, etching, doping, dielectric formation, contacts, and multilayer interconnect. PDKs translate process capabilities into models, cells, rules, and verification tools. Scaling improves density but makes variability, interconnect delay, power delivery, and reliability increasingly important. FinFET and gate-all-around structures improve electrostatic control while introducing new geometric and design constraints. Because compact models and corners are abstractions, sound design requires statistical analysis, extracted simulation, professional judgment, and awareness of model limitations.

Key Terms

MOSFET: A voltage-controlled semiconductor transistor using a gate, oxide, and channel.

Inversion layer: A carrier-rich surface region whose conductivity type is opposite to that of the substrate.

Threshold voltage: The gate-to-source voltage at which strong channel inversion begins.

Body effect: The change in threshold voltage caused by source-to-body bias.

Triode region: MOSFET operating region in which the channel exists from source to drain and current is approximately resistive.

Saturation region: Operating region in which channel pinch-off occurs near the drain.

Overdrive voltage: The quantity V_GS − V_T.

Channel-length modulation: Increase of saturation current with drain voltage due to effective channel shortening.

Subthreshold current: Current flowing when gate voltage is below threshold.

DIBL: Drain-induced lowering of the source-channel barrier, causing threshold reduction and leakage increase.

Velocity saturation: Limitation of carrier velocity at high lateral electric field.

Parasitic capacitance: Unintended or unavoidable capacitance associated with device and interconnect geometry.

CMOS fabrication: Manufacturing sequence used to form complementary nMOS and pMOS circuits.

Process design kit: Foundry-provided models, cells, rules, and files supporting IC design.

Design-rule checking: Verification that layout geometry satisfies manufacturing constraints.

Layout-versus-schematic: Verification that the extracted layout connectivity matches the circuit schematic.

FinFET: A multi-gate transistor in which the channel forms a vertical fin controlled by the gate.

Gate-all-around transistor: A device whose gate surrounds the channel on all sides.

Process variability: Statistical and systematic variation in device and interconnect properties.

Compact model: Mathematical representation of device behavior used in circuit simulation.

Review Questions

Short Answer Questions

1. What physical mechanism produces an inversion layer in a MOS capacitor?

2. Distinguish the triode and saturation regions of an nMOS transistor.

3. Why does body bias affect threshold voltage?

4. Name two sources of MOSFET parasitic capacitance.

5. What are the principal purposes of DRC and LVS?

Long Answer Questions

1. Derive the long-channel nMOS current equations for the triode and saturation regions and state their assumptions.

2. Explain how short-channel effects alter leakage, gain, and digital switching behavior.

3. Describe a representative CMOS fabrication flow from wafer preparation through multilayer interconnect.

4. Explain the role of a PDK in schematic, layout, extraction, and signoff activities.

5. Compare planar MOSFETs, FinFETs, and gate-all-around devices with respect to electrostatic control and design implications.

Analytical / Application Questions

1. A designer doubles transistor width to reduce delay but observes little improvement after extraction. Analyze possible causes involving capacitance, interconnect, and parasitic resistance.

2. For a battery-operated circuit, evaluate the trade-off between lowering threshold voltage for speed and increasing threshold voltage for leakage reduction.

3. A compact model predicts acceptable nominal performance but large Monte Carlo yield loss. Propose a systematic investigation involving variability sources, layout, corners, and model validation.

22. Multiple Choice Questions with Answers

Question 1

For a long-channel nMOS transistor in the triode region, which condition is correct?

A. VGS < VT and VDS = 0

B. VGS > VT and VDS < VGS − VT

C. VGS > VT and VDS > VGS + VT

D. VGS = VT and the channel is strongly inverted

Correct Answer: B. VGS > VT and VDS < VGS − VT

Question 2

What is the principal effect of channel-length modulation in saturation?

A. It makes drain current exactly zero

B. It removes body effect

C. It causes drain current to increase with drain voltage

D. It eliminates parasitic capacitance

Correct Answer: C. It causes drain current to increase with drain voltage

Question 3

Which change most directly increases ideal gate-oxide capacitance per unit area?

A. Increasing oxide thickness

B. Reducing oxide thickness

C. Increasing channel length

D. Reducing substrate doping to zero

Correct Answer: B. Reducing oxide thickness

Question 4

A high drain voltage lowers the source-channel barrier and increases off-state current. This is known as:

A. Velocity saturation

B. DIBL

C. Body effect

D. Electromigration

Correct Answer: B. DIBL

Question 5

Which expression best represents first-order dynamic switching power?

A. αCVDD²f

B. VDD/R only

C. λVDS²/W

D. μCoxL/W

Correct Answer: A. αCVDD²f

Question 6

Why can increasing transistor width fail to produce a proportional delay improvement?

A. Width always increases threshold voltage to infinity

B. The added drive current may be offset by increased gate and diffusion capacitance

C. Width eliminates the load capacitance

D. Wider transistors cannot operate in saturation

Correct Answer: B. The added drive current may be offset by increased gate and diffusion capacitance

Question 7

What is the main electrostatic advantage of a FinFET over a planar MOSFET?

A. The gate controls multiple sides of the channel

B. It requires no source or drain

C. It eliminates all interconnect resistance

D. It operates without a threshold voltage

Correct Answer: A. The gate controls multiple sides of the channel

Question 8

Which PDK function verifies that extracted layout connectivity corresponds to the schematic?

A. DRC

B. LVS

C. Monte Carlo sampling

D. Clock-tree synthesis

Correct Answer: B. LVS

Question 9

Why is interconnect increasingly important in scaled technologies?

A. Wire resistance and coupling can dominate delay and signal integrity

B. Transistors no longer have capacitance

C. Supply voltage increases without limit

D. Metal layers become superconducting

Correct Answer: A. Wire resistance and coupling can dominate delay and signal integrity

Question 10

Which layout technique is particularly useful for reducing systematic mismatch between analog devices?

A. Leaving devices without well contacts

B. Common-centroid placement with suitable dummy devices

C. Maximizing random routing asymmetry

D. Removing all substrate connections

Correct Answer: B. Common-centroid placement with suitable dummy devices