9. Physical Design and Sign-Off

Introduction and Context

Physical design is the stage at which a synthesized digital circuit is transformed into a manufacturable geometric representation of silicon. Logic synthesis describes what the circuit must do; physical design determines where its cells, memories, power structures, clock networks, and interconnections will be placed and how they will be fabricated. The quality of this transformation affects performance, power, area, reliability, yield, and ultimately product cost.

At advanced process nodes, physical design is not a simple sequence in which one task ends before the next begins. Floorplan decisions influence congestion, congestion influences timing, timing optimization changes power, power-grid design affects routability, and routing determines parasitic capacitance and resistance. Consequently, implementation is an iterative optimization process governed by design constraints and manufacturing rules.

Sign-off is the final evidence-based determination that the design satisfies functional, timing, power, physical, reliability, and manufacturability requirements. A design is not ready for tape-out merely because it has been routed. It must pass a collection of independent and cross-correlated checks using approved libraries, process rules, extraction models, and sign-off tools.

Learning Objectives

After studying this chapter, the student should be able to:

1. Explain the physical-design flow from partitioning through tape-out.

2. Develop and evaluate floorplans, power plans, placement, clock trees, and routing strategies.

3. Interpret timing, congestion, parasitic, design-rule, and manufacturability reports.

4. Distinguish implementation optimization from sign-off verification.

5. Apply engineering change orders while controlling functional and physical risk.

6. Diagnose common causes of timing and physical-design failure.

7. Describe professional, automation, governance, and reliability considerations in sign-off.

From Netlist to Geometric Layout

The input to physical design is usually a gate-level netlist, technology files, standard-cell and macro abstracts, timing libraries, power-intent descriptions, and design constraints. The principal outputs are a routed database and a final layout file, commonly represented in a format such as GDSII or OASIS. Between these endpoints, the design passes through several transformations.

Partitioning and Hierarchy

Large systems may be divided into blocks according to functionality, physical locality, clock domains, power domains, or organizational ownership. Partitioning reduces the complexity of optimization and allows teams to work in parallel. Good partitions minimize the number and length of signals crossing boundaries while preserving useful interfaces and manageable block sizes.

Partition boundaries are not merely logical boundaries. They require physical abstracts, timing budgets, placement blockages, feedthrough planning, and agreed power interfaces. A poor partition can create excessive top-level wiring, unbalanced timing budgets, and difficult integration. Hierarchical implementation is therefore a trade-off between local optimization and global visibility.

Floorplanning

Floorplanning establishes the physical canvas. It includes die and core dimensions, aspect ratio, macro locations, standard-cell regions, input/output placement, blockages, channels, and preliminary routing resources. The floorplan should provide short and predictable paths for high-traffic connections, adequate spacing around memories and analog interfaces, and sufficient resources for power and clock distribution.

Important floorplan objectives include area utilization, congestion control, timing feasibility, thermal distribution, and power-delivery integrity. High utilization may reduce area but leaves little whitespace for optimization and routing. Macro placement deserves particular care because large memories create obstacles that cannot be moved by ordinary placement algorithms. A practical approach is to place macros according to connectivity and data flow, reserve channels for major buses, and avoid narrow notches that trap standard cells.

Power Planning

The power network distributes power and ground from package connections to standard cells and macros. It normally contains rings, straps, mesh structures, and local rails. The network must limit voltage drop and electromigration while preserving routing resources.

Static voltage drop results from sustained average current, whereas dynamic voltage drop is associated with time-varying switching activity and package or on-chip inductive effects. Electromigration is the gradual movement of metal atoms caused by excessive current density. Power planning therefore requires appropriate metal widths, via arrays, strap pitch, domain connections, decoupling capacitors, and, in some designs, power-gating structures.

Power intent is often expressed using a low-power methodology such as UPF. Multiple voltage domains may require level shifters, isolation cells, retention elements, and always-on supplies. These structures must be physically placed near domain boundaries and verified for both connectivity and intent.

Placement and Optimization

Placement assigns locations to standard cells. Global placement initially seeks an approximate arrangement satisfying density and connectivity objectives. Legalization moves cells onto valid rows and sites, removes overlaps, and observes orientation and spacing rules. Detailed placement then improves local wirelength, timing, congestion, and power.

Placement is usually timing-driven. Cells on critical paths may be upsized, moved closer together, buffered, or assigned to lower-threshold-voltage variants. Such actions improve delay but can increase leakage, dynamic power, or congestion. Hold-time repair commonly inserts delay cells or buffers, but excessive repair can increase area and load on the power network.

Useful placement metrics include total negative slack, worst negative slack, total wirelength, overflow, utilization, and buffer count. No single metric is sufficient. A placement with excellent wirelength but severe congestion is not a successful placement because later routing may fail.

Clock-Tree Synthesis

Clock-tree synthesis (CTS) constructs a network that delivers clock transitions to sequential elements. Its objectives include controlled skew, acceptable insertion delay, transition limits, clock power, and robustness across operating modes and process corners. A clock network may use a balanced tree, a mesh, or a hybrid structure.

Clock skew is the difference in clock arrival time between two endpoints. It can be useful or harmful: intentional useful skew may improve setup timing, but it can reduce hold margin or complicate variation analysis. CTS inserts buffers or inverters, selects routing layers, and applies non-default rules where necessary. The clock network must be analyzed with clock uncertainty, jitter, source latency, and on-chip variation.

CTS changes the timing environment substantially. Before CTS, clock arrival is often idealized; after CTS, real insertion delays and skew are present. Post-CTS optimization therefore addresses setup and hold violations, clock transition, clock capacitance, and excessive clock power.

Routing

Routing connects placed pins using metal layers and vias. Global routing estimates paths and identifies congestion, while detailed routing assigns exact tracks and geometries. Routers must obey spacing, width, enclosure, antenna, via, and layer-direction rules. Critical nets may receive shielding, wider wires, extra spacing, or preferred layers.

Routing parasitics strongly influence delay and signal integrity. Long parallel wires can produce capacitive coupling, causing crosstalk-induced delay shifts or glitches. Crosstalk-aware optimization may change spacing, buffering, layer assignment, or victim aggressor relationships. Antenna effects arise when a long conductor connected to a gate accumulates charge during fabrication; antenna diodes, jumper routes, or layer changes may be used for protection.

Timing Closure as an Iterative Discipline

Static timing analysis (STA) verifies timing without applying simulation vectors. It models paths from launch points to capture points and checks setup, hold, recovery, removal, pulse width, and transition constraints. For a setup path, data must arrive before the capture edge with sufficient margin. For a hold path, data must not arrive too early after the capture edge.

Slack is the difference between required arrival time and actual arrival time. Positive slack indicates margin; negative slack indicates a violation. Worst negative slack describes the most severe endpoint violation, while total negative slack summarizes the aggregate problem. Timing must be checked across modes and corners, including functional, test, low-power, voltage, temperature, and process conditions.

A typical closure sequence is:

• verify constraints and clock definitions;
• establish pre-route timing;
• perform placement optimization;
• build and optimize the clock tree;
• extract post-route parasitics;
• perform signal-integrity-aware STA;
• repair setup and hold violations;
• recheck power, area, and physical legality after every major change.

Timing repair options include cell sizing, buffering, gate restructuring, threshold-voltage selection, useful skew, placement refinement, route modification, and localized logic changes. Setup repair generally reduces data-path delay or increases available time. Hold repair intentionally delays data or changes clock relationships. Because setup and hold fixes can oppose one another, closure requires analysis across all relevant corners rather than optimizing a single report.

Extraction, ECOs, and Sign-Off Evidence

Parasitic extraction converts routed geometry into resistance and capacitance models. These models may be stored in formats such as SPEF and are back-annotated into STA. Extraction accuracy depends on technology models, layer geometry, coupling treatment, and the chosen reduction strategy. Early implementation may use estimates; final sign-off uses approved extraction settings.

An engineering change order (ECO) modifies an implemented design after a baseline has been established. Functional ECOs alter logic, while metal-only ECOs modify limited routing layers and preserve lower-level devices where possible. ECOs are valuable late in the schedule, but they can introduce new timing, congestion, formal-equivalence, power, or design-rule problems. Every ECO requires clear ownership, version control, impact analysis, and re-verification.

Sign-off is a convergence of complementary checks:

• STA confirms timing under defined modes and corners.
• Design-rule checking (DRC) confirms compliance with manufacturing geometry rules.
• Layout-versus-schematic (LVS) verifies that extracted connectivity matches the intended netlist.
• Parasitic extraction supplies realistic interconnect models.
• Electrical-rule checking examines issues such as opens, shorts, antenna, and well or substrate conditions.
• Power-integrity analysis evaluates voltage drop and electromigration.
• Reliability checks may include thermal, aging, noise, and voltage-stress analysis.
• Formal or simulation-based checks confirm that ECOs preserve intended behavior.
• Density, fill, lithography, and manufacturability checks assess process readiness.

DRC errors may involve minimum width, spacing, enclosure, density, via, or pattern restrictions. LVS errors are categorized as shorts, opens, missing devices, extra devices, or parameter mismatches. Passing LVS does not imply timing correctness, and passing STA does not imply geometric correctness; each check answers a different question.

Manufacturability and Design for Yield

Design for manufacturability (DFM) extends beyond minimum rule compliance. A layout can pass binary DRC and still have poor yield because of restrictive patterns, weak redundant-via coverage, unfavorable lithographic interactions, density variation, or sensitive critical dimensions. Modern processes may require recommended rules, pattern matching, multi-patterning compliance, coloring consistency, and metal-density control.

Metal fill is inserted to meet density requirements and improve process uniformity. However, fill adds capacitance and can alter timing, especially on sensitive nets. Therefore, fill-aware extraction and final timing analysis are essential. Redundant vias improve resistance to single-via defects, while careful critical-area reduction can improve defect tolerance.

An Illustrative Case: Closing a Network-Processing Block

Background

Consider a fictional 7-nanometre network-processing block containing embedded memories, multiple clock domains, and separate core and always-on voltage domains. Its initial placement met the area target but failed post-route timing and power-integrity objectives.

Problem

The worst setup path had negative slack because a high-bandwidth bus crossed a memory cluster. Hold violations appeared after CTS, and dynamic voltage drop was concentrated near the memory periphery. Routing overflow occurred in two narrow channels. A late functional ECO further increased congestion.

Analysis

The team first verified that the violations were not caused by incorrect constraints. Connectivity analysis showed that the bus crossing was a floorplan problem rather than merely a cell-sizing problem. The power report showed insufficient strap access around the memories, while CTS analysis showed excessive local clock insertion delay. The ECO had also created a long detour on a critical control net.

Strategy and Solution

The memory cluster was shifted to shorten the bus and widen one routing channel. A reserved macro halo was adjusted, and selected standard-cell rows were removed to create power and clock access. Additional upper-metal power straps and via arrays were added. CTS was rerun with a refined skew target and better clock-buffer placement. The ECO was reimplemented using a localized spare-cell structure, followed by incremental placement and routing.

Post-route extraction was then performed with coupling enabled. Setup repair used selective cell upsizing and a route-layer change, while hold repair used small delay cells only on affected endpoints. Metal fill was inserted before final extraction. The block was finally rechecked for STA, DRC, LVS, antenna, electromigration, voltage drop, and formal equivalence.

Outcome and Learning Points

The block achieved timing closure without exceeding its area target, and power integrity improved after the strap revision. More importantly, the team learned that late timing problems often originate in early floorplan and power-network choices. Incremental ECOs are effective only when their physical context is understood. Sign-off must be performed after final fill and extraction, not on an earlier routed database.

Professional Practice, Automation, and Governance

Physical design is performed through scripts, databases, and tool flows rather than isolated graphical operations. Version-controlled constraints, reproducible run configurations, automated report collection, and checklists reduce human error. Continuous integration can launch incremental DRC, STA, equivalence, and power checks after controlled changes.

Machine-learning techniques are increasingly used for congestion prediction, macro placement exploration, parameter tuning, and optimization guidance. Such systems can accelerate search, but their recommendations require engineering review. An optimization that improves a proxy metric may damage an unmodeled sign-off requirement. Traceability, deterministic reruns, and independent verification remain essential.

Professional governance includes controlled technology files, approved library versions, access permissions, waiver management, and documented sign-off ownership. Waivers should identify the rule, rationale, risk, approving authority, and conditions under which the waiver remains valid. Suppressing errors without technical justification is unacceptable because it transfers risk to manufacturing and customers.

Challenges and Common Failure Modes

Several recurring mistakes undermine physical-design quality:

1. Treating utilization as the only floorplan metric and ignoring congestion or power access.

2. Delaying power planning until after signal routing.

3. Using incomplete or incorrect timing constraints.

4. Fixing setup at one corner while creating hold failures at another.

5. Ignoring coupling, fill, or extraction-model changes near the end of the flow.

6. Accepting DRC-clean layout without checking LVS, antenna, density, and reliability.

7. Applying ECOs without formal equivalence and complete regression.

8. Allowing excessive waivers or undocumented manual database edits.

The central limitation of any implementation tool is that it optimizes the objectives and models supplied to it. Missing constraints, inaccurate libraries, unrealistic activity assumptions, or incomplete corners can produce a falsely reassuring result.

Best-Practice Sign-Off Flow

A disciplined sign-off flow begins with input validation: netlist, libraries, constraints, power intent, technology rules, and design versions must be consistent. The team then establishes baseline reports, performs implementation with milestone checks, and maintains a single source of truth for the database. After routing, final extraction, fill, and ECO activity, sign-off analyses must be rerun using release-quality settings.

Before tape-out, organizations should require clean or approved reports for timing, DRC, LVS, electrical rules, antenna, density, power integrity, reliability, equivalence, and manufacturability. Results should be reviewed by appropriately independent engineers, with all assumptions and waivers recorded. Sign-off is therefore both a technical conclusion and a governance decision.

Current Developments

Advanced-node implementation increasingly uses restrictive design rules, multi-patterning or advanced lithography constraints, buried or backside power-delivery concepts, three-dimensional integration, chiplets, and increasingly complex package interactions. These developments blur the boundary between chip, package, and system design. Thermal analysis, package-aware timing, die-to-die interface verification, and early co-optimization are becoming more important.

At the same time, hierarchical flows, cloud-scale computation, and AI-assisted optimization are expanding the search space. The lasting engineering principle remains unchanged: automation can explore and optimize, but sign-off requires explainable evidence against authoritative models.

Chapter Summary

Physical design converts a logical netlist into a manufacturable layout through partitioning, floorplanning, power planning, placement, CTS, routing, extraction, and iterative optimization. Timing closure uses STA across modes and corners, while ECOs provide controlled late-stage correction. Final sign-off combines timing, DRC, LVS, extraction, power integrity, reliability, equivalence, and manufacturability checks. Floorplan and power decisions have consequences throughout the flow, and no individual check proves complete correctness. Modern practice depends on automation, version control, documented waivers, independent review, and final verification after fill and extraction.

Key Terms

Partitioning: Dividing a large design into manageable physical or functional blocks.

Floorplan: The arrangement of die, core, macros, cells, interfaces, and physical constraints.

Utilization: The proportion of available core area occupied by placed standard cells.

Congestion: Insufficient routing capacity for the connections demanded in a region.

Power grid: The network of rings, straps, mesh, rails, and vias distributing supply and ground.

IR drop: Supply-voltage loss caused by resistance and current in the power network.

Electromigration: Current-induced movement of metal atoms that can damage interconnects.

Placement: Assignment of physical locations to standard cells.

Clock skew: Difference in clock arrival time between two endpoints.

Clock-tree synthesis: Construction and optimization of the clock-distribution network.

Routing: Assignment of metal geometries and vias to connect placed pins.

Parasitic extraction: Derivation of resistance and capacitance from layout geometry.

Static timing analysis: Vectorless analysis of timing paths under specified conditions.

Slack: Difference between required and actual arrival time.

ECO: A controlled engineering change made after an implementation baseline exists.

DRC: Verification that layout geometries obey manufacturing design rules.

LVS: Verification that layout-extracted connectivity matches the intended schematic or netlist.

DFM: Techniques that improve manufacturability, yield, and process robustness beyond minimum rules.

Sign-off: The documented determination that all required implementation and verification criteria are satisfied.

Review Questions

Short Answer Questions

1. Why is partitioning a physical as well as a logical decision?

2. Distinguish static and dynamic voltage drop.

3. What is the purpose of clock-tree synthesis?

4. Why is final parasitic extraction needed for timing sign-off?

5. What does LVS verify?

Long Answer Questions

1. Explain the physical-design flow from floorplanning to final routing, including the principal objectives of each stage.

2. Discuss the interaction among placement, congestion, timing, power, and area.

3. Explain setup and hold closure across multiple modes and process corners.

4. Describe the roles of DRC, LVS, extraction, power-integrity analysis, and manufacturability checks in sign-off.

5. Discuss how ECOs should be managed to minimize functional and physical risk.

Analytical / Application Questions

1. A design has good post-placement timing but severe post-route congestion around memories. Identify likely root causes and propose floorplan remedies.

2. A setup fix improves the slow corner but creates hold violations in a fast corner. Develop a systematic closure strategy.

3. A final metal-fill step causes a critical path to fail timing. Explain why this can occur and recommend corrective actions.

22. Multiple Choice Questions with Answers

Question 1

Which floorplanning decision most directly reduces long interconnect on a high-bandwidth bus?

A. Increasing clock uncertainty

B. Placing strongly connected macros near one another

C. Adding hold buffers to all endpoints

D. Reducing the number of timing corners

Correct Answer: B. Placing strongly connected macros near one another

Question 2

Dynamic voltage drop is primarily associated with which condition?

A. Time-varying switching current

B. A permanent LVS mismatch

C. Minimum metal spacing

D. Static cell placement density only

Correct Answer: A. Time-varying switching current

Question 3

What is the principal purpose of clock-tree synthesis?

A. To extract final parasitics

B. To distribute clock signals with controlled skew and transition

C. To verify transistor connectivity

D. To insert metal fill

Correct Answer: B. To distribute clock signals with controlled skew and transition

Question 4

A negative slack value in static timing analysis indicates that:

A. The path has excess timing margin

B. The required timing constraint is violated

C. The layout automatically fails LVS

D. The power grid is too wide

Correct Answer: B. The required timing constraint is violated

Question 5

Why must timing commonly be checked after metal fill?

A. Fill can alter parasitic capacitance and therefore delay

B. Fill changes the logical function of every gate

C. Fill eliminates all clock skew

D. Fill replaces the need for extraction

Correct Answer: A. Fill can alter parasitic capacitance and therefore delay

Question 6

Which sign-off check determines whether extracted layout connectivity matches the intended netlist?

A. STA

B. DRC

C. LVS

D. IR-drop analysis

Correct Answer: C. LVS

Question 7

A metal-only ECO is generally attractive late in the flow because it:

A. Requires no verification

B. Can limit changes to selected routing layers

C. Automatically fixes all setup and hold violations

D. Removes the need for formal equivalence

Correct Answer: B. Can limit changes to selected routing layers

Question 8

A routed design passes minimum DRC but has poor yield risk due to restrictive patterns and weak via structures. Which activity addresses this concern?

A. Design for manufacturability analysis

B. Ideal-clock timing analysis only

C. Logic simulation only

D. Clock-domain crossing analysis only

Correct Answer: A. Design for manufacturability analysis

Question 9

Which sequence best represents a credible late-stage sign-off practice?

A. Route, ignore fill, and tape out after one timing report

B. Insert fill, extract final parasitics, then rerun required sign-off checks

C. Perform LVS before placement and never repeat it

D. Fix setup at one corner without checking hold

Correct Answer: B. Insert fill, extract final parasitics, then rerun required sign-off checks

Question 10

Why can a high-utilization floorplan be risky even when it meets the area target?

A. It always increases logical gate count

B. It leaves less whitespace for routing and optimization

C. It prevents all power connections

D. It makes clock signals ideal by definition

Correct Answer: B. It leaves less whitespace for routing and optimization