Low-Power and Thermal-Aware VLSI Design

Introduction and Context

Power and temperature have become first-order design constraints in modern VLSI systems. In earlier technology generations, performance and area were often dominant objectives, while power was treated mainly as a packaging concern. Deep-submicrometre CMOS changed this situation. Portable systems require long battery life, data centres face severe energy and cooling costs, and high-performance processors are increasingly limited by temperature rather than by transistor switching speed alone.

Low-power design is therefore not equivalent to merely reducing supply voltage. It is a coordinated activity involving circuit topology, architecture, physical implementation, operating modes, power-intent specification, software activity, packaging and thermal management. The designer must minimize energy while preserving timing, reliability, functionality and verification quality.

This chapter develops methods for estimating and optimizing dynamic, short-circuit and leakage power. It also examines clock gating, power gating, multi-voltage design, dynamic voltage and frequency scaling (DVFS), state retention, isolation, activity analysis, UPF-based intent, thermal modelling and energy-efficiency metrics.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Decompose CMOS power into dynamic, short-circuit and leakage components.

2. Estimate power using capacitance, voltage, frequency and activity information.

3. Select suitable clock-gating, power-gating, voltage-scaling and retention strategies.

4. Explain level shifters, isolation cells and power-domain crossings.

5. Use UPF concepts to express power intent and support implementation and verification.

6. Construct first-order thermal models and interpret temperature-related design limits.

7. Evaluate designs using energy, energy-delay, power-performance and thermal-efficiency metrics.

8. Critically assess practical trade-offs, limitations and emerging low-power techniques.

1. Sources of Power in CMOS Circuits

The total power of a digital circuit is commonly represented as

P_total = P_dynamic + P_short-circuit + P_leakage + P_other.

Here, P_dynamic is the power associated with charging and discharging capacitances, P_short-circuit is the transient current flowing directly from supply to ground during input transitions, P_leakage is the current consumed when the circuit is nominally not switching, and P_other includes memory effects, I/O drivers, analog blocks, regulator losses and power delivered to external loads. The categories are not perfectly independent in detailed models, but the decomposition is highly useful for design decisions.

1.1 Dynamic switching power

When a CMOS node with capacitance C is charged from 0 to V_DD, the supply delivers energy C V_DD^2. Half of this energy is stored temporarily on the capacitor and half is dissipated in the pull-up network. During discharge, the stored energy is dissipated in the pull-down network. For a node that makes a complete 0-to-1 transition with probability alpha per clock cycle and operates at frequency f,

P_dynamic = alpha C V_DD^2 f.

In this expression, alpha is the switching activity factor in transitions per cycle, C is the effective switched capacitance in farads, V_DD is the supply voltage in volts, and f is the transition reference frequency in hertz. The formula assumes a full voltage swing, lumped capacitance and negligible recovery of stored charge. If alpha is defined as the probability of a 0-to-1 transition per cycle, the expression is directly applicable. If activity is instead specified as total transitions per cycle, a factor of one-half may be required depending on the convention.

For a circuit containing many nodes,

P_dynamic = V_DD^2 f Σ_i alpha_i C_i.

This equation shows three powerful levers: reduce switching activity, reduce capacitance and reduce voltage. Voltage reduction is especially effective because power varies quadratically with V_DD, although timing degradation and noise-margin reduction impose limits.

The effective capacitance includes gate capacitance, diffusion and interconnect capacitance, fan-out capacitance, and the input capacitance of driven cells. At advanced nodes, interconnect capacitance may dominate, so logic minimization alone does not guarantee a substantial power reduction.

1.2 Short-circuit power

During a finite-rise-time input transition, both the PMOS and NMOS networks of a CMOS gate can conduct simultaneously. A transient path then exists from V_DD to ground. The resulting short-circuit power depends on input slew, output load, transistor sizing, supply voltage and threshold voltage. A precise closed-form expression is technology- and topology-dependent; therefore, library characterization or transistor-level simulation is normally used.

Short-circuit power generally increases when input transitions are slow and when the output load is small relative to the driving strength. It is reduced by balanced rise and fall times, appropriate transistor sizing, controlled input slew and avoiding unnecessarily large devices. Lowering V_DD can reduce short-circuit current, although the relationship is not simply identical to the dynamic-power relationship.

1.3 Leakage power

Leakage exists even when no logic transition occurs. Major components include subthreshold leakage, gate-oxide or gate tunnelling leakage, and reverse-biased junction leakage. A first-order estimate is

P_leakage = V_DD I_leak,total,

where I_leak,total is the aggregate leakage current under the relevant input state, temperature and process condition. Leakage is strongly dependent on threshold voltage, temperature, transistor dimensions, body bias and process variation. It is also state-dependent: different input combinations can produce substantially different leakage currents.

Subthreshold leakage tends to increase exponentially as threshold voltage is reduced and rises strongly with temperature. Consequently, techniques that improve active-mode speed by using low-threshold-voltage cells may increase standby power. High-threshold-voltage cells are useful on noncritical paths, whereas low-threshold-voltage cells should be reserved for timing-critical paths.

2. Power Estimation and Activity Analysis

Power estimation must match the design stage. At architectural level, switching factors and capacitance estimates are coarse, but alternative algorithms and operating modes can be compared quickly. At RTL, simulation-derived activity provides better information. At gate level, parasitic extraction and cell-library power models improve accuracy. Silicon measurements remain essential because package, regulator, workload and environmental effects are difficult to model completely.

A practical flow is:

1. Define operating modes, workloads, voltage rails, clock frequencies and environmental conditions.

2. Estimate or obtain switching activity for primary inputs, registers, memories and clock networks.

3. Map activity to capacitance using RTL synthesis, gate-level netlists or physical parasitics.

4. Include internal cell power, short-circuit power, leakage and clock-tree power.

5. Analyse peak, average and mode-specific power rather than relying only on a single average.

6. Correlate estimates with emulation, FPGA prototypes or silicon measurements.

Activity propagation from RTL simulation must be interpreted carefully. Zero-delay simulation can miss glitches. Gate-level simulation may reveal hazards but is computationally expensive. Vectorless estimation can cover untested states but depends on probabilistic assumptions. A robust methodology combines representative traces with statistical or formal analysis of rare operating modes.

Glitch power is dynamic power caused by multiple transitions before a node settles. It can be significant in unbalanced combinational logic, asynchronous interfaces and arithmetic datapaths. Logic restructuring, balanced paths, operand isolation and registering intermediate results can reduce glitch activity, though extra registers introduce area, clock and leakage costs.

The clock network deserves special attention. It switches every cycle in active operation and drives a large capacitance. Clock-tree power includes the clock buffers, interconnect and sequential-cell clock pins. Clock gating is consequently one of the most effective system-level techniques.

3. Major Low-Power Design Techniques

3.1 Clock gating

Clock gating prevents a clock from reaching inactive sequential logic. A safe integrated clock-gating cell generally contains a level-sensitive latch followed by an AND gate for active-high clocks, or an equivalent structure for other clock polarities. The enable signal is sampled during the inactive phase of the clock, preventing glitches on the gated clock.

If a block would otherwise consume clock-related power P_clk and is disabled for fraction d of the observation interval, the ideal saving is approximately dP_clk. Actual saving is lower because the gating cell itself consumes power, control logic switches, and some downstream circuitry may still be active.

Clock gating may be applied at module, register-bank or fine-grain levels. Coarse gating provides substantial savings with modest control overhead. Fine-grain gating offers greater opportunity but increases enable complexity, verification effort and potential timing problems. Enables must be designed to avoid unintended state loss and must satisfy clock-domain and test requirements.

3.2 Operand isolation

A datapath may remain clocked while its inputs are held constant when its result is not required. Operand isolation prevents unnecessary internal transitions without stopping the clock. It is especially useful for multipliers, shifters and arithmetic units whose internal switching is high. Isolation gates add capacitance and delay, so the saving must be established through activity analysis.

3.3 Power gating

Power gating disconnects an inactive block from a supply rail. A high-side header transistor disconnects V_DD, while a low-side footer transistor disconnects ground. The resulting virtual supply node is not ideal: its voltage varies with current, switch resistance and wake-up behaviour.

A power-gated block can be in active, idle-retention, sleep or wake-up states. Sleep transistors must be sized to balance IR drop, area, leakage reduction and wake-up current. Large sleep devices reduce active voltage drop but increase area and residual leakage. Distributed switches may improve current density and electromigration reliability.

Power gating removes leakage effectively, but it introduces state-management requirements. If internal state is lost, the block must be reset or reinitialized. If state must survive, retention registers or an explicit save-and-restore mechanism are required.

3.4 Multi-voltage design and level shifting

Different blocks may operate at different supply voltages. High-performance logic can use a higher voltage, while noncritical logic uses a lower voltage to reduce energy. A signal crossing from a lower-voltage domain to a higher-voltage domain may require a level shifter to ensure adequate logic recognition and prevent reliability problems. Down-conversion also requires an appropriate cell when the receiving domain cannot tolerate the higher input voltage.

Voltage islands complicate physical design because they require multiple power grids, placement constraints, level shifters, isolation cells and power-state verification. The energy benefit must be weighed against area, routing, delay and conversion overhead.

3.5 Dynamic voltage and frequency scaling

DVFS adjusts voltage and frequency according to workload demand. Lowering frequency generally permits a lower supply voltage, reducing dynamic power. A simplified active-power relationship is

P_active approximately proportional to alpha C V_DD^2 f.

The proportionality is not exact because leakage, short-circuit power, voltage-dependent delay and regulator efficiency also change. A common first-order delay model is

t_pd proportional to V_DD/(V_DD - V_T)^m,

where V_T is threshold voltage and m is a technology-dependent positive exponent used in an empirical approximation. This relation is valid only over an appropriate voltage range and should not replace characterized timing models.

DVFS controllers must account for workload prediction, voltage-transition latency, regulator efficiency, timing margins and minimum operating voltage. Near-threshold operation can provide excellent energy efficiency for throughput-tolerant applications but is highly sensitive to process, voltage and temperature variation.

3.6 Retention and isolation

Retention registers preserve selected architectural or control state while the main logic supply is removed. A retention cell commonly contains a storage element powered by an always-on or retention supply, together with save and restore controls. Retention increases cell area, leakage and control complexity; therefore, only necessary state should be retained.

Isolation cells prevent invalid or indeterminate values from a powered-down domain from propagating into an active domain. An isolation strategy specifies the clamp value, control signal, controlling power domain and sequencing. Isolation must be asserted before power removal and released only after the source domain has a valid supply and stable state.

A typical shutdown sequence is: stop new transactions, quiesce interfaces, save retention state, assert isolation, disable the domain supply, and confirm power-good status. Wake-up reverses the sequence with suitable settling delays.

4. UPF-Based Power Intent

RTL describes functional behaviour but does not fully specify power domains, supply networks, isolation, retention or power states. The Unified Power Format (UPF), standardized through IEEE 1801, expresses this power intent separately from the RTL implementation.

A UPF-based design typically defines:

• power domains and the design elements belonging to them;
• supply ports, supply nets and supply sets;
• primary, retention and always-on supplies;
• level-shifter and isolation strategies;
• retention strategies and control signals;
• legal power states and transitions;
• power-state tables describing combinations of domain and supply states.

The exact commands and syntax depend on the IEEE 1801 revision and tool flow. The important engineering principle is that power intent becomes machine-readable and can be used during synthesis, implementation, simulation, static checking and verification.

Power-aware verification should test legal and illegal sequences, isolation correctness, retention save/restore, level-shifter insertion, X-propagation and control-signal availability during shutdown. A common failure is an isolation enable generated inside the domain that is being powered off. Such a control signal cannot remain reliable unless it is generated by an always-on domain or otherwise retained.

UPF does not automatically guarantee a correct low-power design. Intent may be syntactically valid but architecturally incomplete. Power-state definitions, reset behaviour, software protocols and physical assumptions must be reviewed together.

5. Thermal Modelling and Thermal-Aware Design

Electrical power becomes heat. Temperature influences mobility, threshold voltage, leakage, timing, electromigration, package reliability and long-term failure rate. Thermal design is therefore coupled to power management.

A first-order lumped thermal model is

T_j = T_ambient + P R_theta,

where T_j is junction temperature, T_ambient is ambient temperature, P is dissipated power in watts and R_theta is effective thermal resistance in degrees Celsius per watt. This steady-state equation assumes a single uniform thermal node and a constant thermal resistance. It is useful for early estimates but cannot represent spatial hotspots or transient heating.

For transient behaviour, a lumped thermal RC model can be written as

C_theta dT/dt = P(t) - (T - T_ambient)/R_theta,

where C_theta is thermal capacitance in joules per degree Celsius. The thermal time constant is tau_theta = R_theta C_theta. A step in constant power produces

T(t) = T_ambient + P R_theta [1 - exp(-t/tau_theta)]

when the initial temperature equals ambient. This model is applicable to a single-node approximation with constant parameters. Real packages require compact multi-node networks or finite-element methods to model die, package, heat spreader and heat sink interactions.

Spatial thermal gradients create hotspots in processor cores, memories and power-management circuits. Thermal-aware floorplanning separates high-power blocks, improves heat spreading and avoids placing temperature-sensitive circuits near hotspots. Runtime thermal management may use sensors, workload migration, clock throttling, DVFS and power capping.

Temperature also increases leakage, creating a possible positive feedback loop: higher temperature increases leakage, which increases power and may further increase temperature. Thermal runaway is not inevitable, but it must be assessed under worst-case process, voltage, activity and cooling conditions.

6. Energy-Efficiency Metrics and Trade-offs

Power and energy are different quantities. Power is the rate of energy consumption, measured in watts; energy is measured in joules. For an interval of duration t with constant power, E = Pt. For time-varying power, E = integral of P(t) dt.

Useful metrics include:

• Energy per operation: E_op = E_total/N_op, where N_op is the number of completed operations.
• Energy-delay product (EDP): EDP = E_total t_delay.
• Energy-delay-squared product: ED^2P = E_total t_delay^2, used when delay is weighted more strongly.
• Performance per watt: throughput/P.
• Energy efficiency: useful work/E_total, with the definition of useful work chosen explicitly.

No metric is universally superior. EDP favours balanced energy and delay, whereas performance per watt may favour high throughput even at greater energy per operation. A fair comparison must state workload, precision, throughput, latency, technology, voltage, temperature and measurement boundary.

Low-power design involves trade-offs. Clock gating can increase control complexity. Power gating saves leakage but causes wake-up latency and inrush current. Lower voltage reduces dynamic power but increases delay and susceptibility to variation. Retention preserves state but costs area and leakage. Aggressive optimization can reduce robustness, complicate verification or violate safety margins.

7. Worked Example: Activity and Voltage Scaling

Consider a logic block with effective switched capacitance of 20 pF, activity factor 0.25 and operating frequency 500 MHz at 1.0 V. Its estimated dynamic power is

P = alpha C V^2 f

= 0.25 × 20×10^-12 × (1.0)^2 × 500×10^6

= 2.5×10^-3 W

= 2.5 mW.

Suppose clock and operand gating reduce the activity factor to 0.10, while DVFS reduces the supply to 0.8 V and frequency to 400 MHz. Assuming the same effective capacitance and ignoring leakage, the new power is

P_new = 0.10 × 20×10^-12 × (0.8)^2 × 400×10^6

= 0.512 mW.

The ideal dynamic-power reduction is approximately 79.5%. This result does not imply that total chip power falls by the same amount: leakage, regulator losses, level-shifter power, control overhead and timing-dependent changes must be included in a complete estimate.

8. Illustrative Case Study: Low-Power Vision-Processing SoC

Background

Consider an illustrative battery-powered vision SoC containing an image sensor interface, a programmable vision processor, SRAM, a display subsystem and a security controller. The processor is active during image analysis, while the display and security blocks have independent duty cycles.

Problem

Initial measurements show unacceptable battery drain and a junction-temperature hotspot near the processor-memory interface. Average power is acceptable during simple scenes but rises sharply during complex image workloads. Standby leakage is also significant when the display is off.

Analysis

Activity traces show that the processor clock continues to toggle during periods when input frames are unavailable. The image-processing pipeline has a high switching factor because operands propagate through multipliers even when a feature-extraction stage is disabled. SRAM banks remain powered during long idle periods. Thermal analysis reveals that the processor and adjacent SRAM create a localized hotspot rather than a uniform die temperature.

Approach

The design team introduces hierarchical clock gating for idle pipeline stages and operand isolation for inactive multipliers. SRAM is divided into power domains, with retention applied only to configuration registers and checkpoint state. Data arrays are power-gated when not required. Isolation cells clamp outputs before shutdown. The display subsystem uses a lower voltage island, with level shifters at crossings. A DVFS controller selects voltage-frequency operating points based on frame rate demand.

UPF specifies domains, supplies, isolation, retention and legal power states. Power-aware simulation verifies that a sleeping SRAM cannot drive active logic and that state restoration occurs before transactions resume. Thermal-aware floorplanning separates the highest-power arithmetic units and improves heat-spreader coupling in the hotspot region.

Outcome

The resulting design reduces switching power during idle and moderate workloads, greatly lowers standby leakage, and reduces peak temperature through workload-aware throttling. The improvement is not obtained from one technique; it results from coordinated activity reduction, power-domain control, voltage scaling and thermal management. The principal cost is increased verification effort, extra cells and more complex firmware sequencing.

Learning Points

1. Workload measurement must precede optimization.

2. Peak power and hotspot temperature can be more restrictive than average power.

3. State retention should be selective rather than universal.

4. Power intent must be verified as a system-level protocol.

5. Thermal and electrical decisions should be made together.

9. Challenges, Reliability and Governance

Low-power systems introduce reliability concerns, including power noise, ground bounce, IR drop, electromigration, inrush current, timing uncertainty and thermal cycling. Power-gated blocks can cause supply transients when many cells wake simultaneously. Staggered wake-up, controlled slew and adequate decoupling capacitors reduce these effects.

Safety-critical systems require traceable power-state behaviour. A failure to assert isolation, retain a safety control bit or respect a thermal limit can cause hazardous operation. Verification plans should define assumptions, safety mechanisms, diagnostic coverage and fail-safe states. Security also matters: power-state transitions can expose side channels, cause denial of service through thermal throttling, or create vulnerabilities if sensitive state is retained in inadequately protected structures.

Environmental responsibility extends beyond operating power. Designers should consider manufacturing energy, embodied carbon, service life, repairability and end-of-life recycling. A lower-power chip is not automatically more sustainable if it substantially increases material use or shortens product life.

10. Contemporary Developments and Best Practices

Current research and industry practice include near-threshold computing, adaptive body bias, power-performance monitors, 3D integration, chiplet-based systems, advanced backside power delivery and machine-learning-assisted workload prediction. Three-dimensional integration improves communication density but intensifies thermal challenges because inner tiers have limited heat-removal paths. AI accelerators increasingly use dataflow optimization, sparsity, approximate arithmetic and memory-locality techniques to reduce data movement, which often dominates arithmetic energy.

Machine learning can predict workload demand and select DVFS states, but prediction errors must be bounded. A controller should preserve timing and thermal safety even when its prediction is wrong. Explainability and verification are especially important in safety-sensitive systems.

Best practices include:

• establish power, performance and temperature budgets at architecture level;
• measure realistic workloads and include worst-case activity;
• distinguish average, peak, leakage and thermal power;
• use high-threshold cells on noncritical paths and low-threshold cells selectively;
• apply clock gating and operand isolation where activity analysis demonstrates benefit;
• define power domains and legal states early using UPF;
• verify isolation, retention, level shifting and sequencing formally or through power-aware simulation;
• include regulator, package and thermal effects in system estimates;
• validate estimates against silicon measurements;
• document assumptions, units, corners and measurement boundaries.

Chapter Summary

CMOS power consists primarily of dynamic, short-circuit and leakage components. Dynamic power is governed by activity, capacitance, supply voltage and frequency, while leakage depends strongly on threshold voltage, temperature and process conditions. Effective optimization reduces unnecessary transitions through clock gating and operand isolation, removes standby leakage through power gating, and uses multi-voltage design and DVFS to exploit workload-dependent energy opportunities.

Power-domain techniques require level shifters, isolation cells, retention elements and carefully sequenced control. UPF provides a standard way to express these requirements, but correct intent, implementation and verification remain essential. Thermal models range from simple steady-state resistance equations to transient RC networks and detailed spatial simulations. Temperature affects performance, leakage and reliability, so thermal design must be integrated with electrical power management.

Energy-efficiency metrics such as energy per operation, EDP and performance per watt support quantitative comparison, but each has limitations. A successful low-power VLSI design balances energy, performance, area, reliability, verification complexity, security and thermal safety across realistic workloads and operating conditions.

Key Terms

Dynamic power: Power caused mainly by charging and discharging capacitances.

Switching activity factor: Average number or probability of relevant transitions per cycle.

Short-circuit power: Power dissipated when pull-up and pull-down networks conduct simultaneously.

Leakage power: Power consumed by nonideal current in a nominally static circuit.

Clock gating: Disabling a clock signal to inactive sequential logic.

Operand isolation: Preventing inactive datapath inputs from causing internal switching.

Power gating: Disconnecting a circuit from a supply to reduce standby leakage.

Voltage island: A physical or logical region operating from a designated supply voltage.

Level shifter: A cell that safely translates signals between voltage domains.

Isolation cell: A cell that clamps signals from an inactive or powered-down domain.

Retention register: A state-holding cell that preserves information during power shutdown.

DVFS: Dynamic adjustment of voltage and frequency according to workload.

UPF: IEEE 1801-based language and methodology for specifying power intent.

Power state: A defined combination of supply, isolation, retention and functional conditions.

Thermal resistance: Temperature rise per unit dissipated power.

Thermal capacitance: Ability of a thermal system to store heat.

Hotspot: Localized region with substantially higher temperature than surrounding areas.

Energy-delay product: Energy multiplied by delay, used as a combined efficiency metric.

Near-threshold operation: Operation with supply voltage close to transistor threshold voltage.

Power intent: Explicit specification of power domains, supplies, controls and low-power structures.

Review Questions

Short Answer Questions

1. What are the principal components of CMOS power?

2. Why does dynamic power have a quadratic dependence on supply voltage?

3. What is the purpose of an isolation cell?

4. Why are retention registers required in some power-gated domains?

5. Define thermal resistance and state its unit.

Long Answer Questions

1. Explain clock gating, operand isolation and power gating, including their benefits and implementation costs.

2. Discuss multi-voltage design, level shifters and isolation requirements in a power-domain architecture.

3. Explain how UPF supports low-power implementation and verification.

4. Compare steady-state thermal-resistance models with transient thermal RC models.

5. Discuss the trade-offs among leakage, performance, voltage scaling, retention and reliability.

Analytical / Application Questions

1. A block has alpha = 0.2, C = 30 pF, V_DD = 0.9 V and f = 600 MHz. Estimate its dynamic power using the stated model. Then explain which nonideal effects must be added for a total-power estimate.

2. Design a shutdown and wake-up sequence for a power-gated processor domain containing retained control registers and nonretained datapath state. Identify the required isolation and verification checks.

3. A package has effective thermal resistance of 4 °C/W and ambient temperature of 35 °C. Determine the steady-state junction temperature at 8 W, and explain why this estimate may be inadequate for a chip with localized hotspots.

Multiple Choice Questions with Answers

Question 1

Which expression represents the first-order dynamic power of a CMOS node when alpha denotes 0-to-1 transitions per cycle?

A. alpha C V_DD^2 f

B. C V_DD f^2

C. V_DD/I_leak

D. alpha C V_DD/f

Correct Answer: A. alpha C V_DD^2 f

Question 2

Which technique primarily reduces clock-network switching in an inactive sequential block?

A. Level shifting

B. Clock gating

C. Retention

D. Thermal spreading

Correct Answer: B. Clock gating

Question 3

What is the principal purpose of an isolation cell at a powered-down domain boundary?

A. Increase the source-domain voltage

B. Store all datapath state

C. Clamp invalid boundary signals to a known value

D. Measure junction temperature

Correct Answer: C. Clamp invalid boundary signals to a known value

Question 4

A block has alpha = 0.1, C = 10 pF, V_DD = 1 V and f = 1 GHz. What is its estimated dynamic power?

A. 0.1 mW

B. 1 mW

C. 10 mW

D. 100 mW

Correct Answer: B. 1 mW

Question 5

Which statement about power gating is correct?

A. It eliminates all wake-up latency

B. It can reduce standby leakage but may require retention and controlled wake-up

C. It always reduces active-mode delay

D. It makes isolation unnecessary

Correct Answer: B. It can reduce standby leakage but may require retention and controlled wake-up

Question 6

What does UPF primarily specify?

A. Instruction-set semantics

B. Transistor doping concentrations

C. Power domains, supplies, isolation, retention and power states

D. Package mechanical dimensions only

Correct Answer: C. Power domains, supplies, isolation, retention and power states

Question 7

For a lumped steady-state thermal model, junction temperature is estimated by which relation?

A. T_j = T_ambient - P R_theta

B. T_j = P/(T_ambient R_theta)

C. T_j = T_ambient + P R_theta

D. T_j = R_theta/P

Correct Answer: C. T_j = T_ambient + P R_theta

Question 8

Why are high-threshold-voltage cells commonly used on noncritical paths?

A. They generally reduce leakage compared with low-threshold cells

B. They always provide the highest switching speed

C. They eliminate dynamic power

D. They replace level shifters

Correct Answer: A. They generally reduce leakage compared with low-threshold cells

Question 9

Which metric multiplies total energy by delay?

A. Performance per watt

B. Energy-delay product

C. Thermal resistance

D. Switching activity

Correct Answer: B. Energy-delay product

Question 10

In a typical shutdown sequence, which action should occur before removing the domain supply?

A. Release isolation

B. Assert isolation after quiescing interfaces

C. Disable all always-on supplies

D. Restore nonretained state

Correct Answer: B. Assert isolation after quiescing interfaces