4. Combinational and High-Performance Arithmetic Circuits

Introduction and Context

Combinational circuits produce outputs determined only by their present inputs. Unlike sequential circuits, they do not store information internally, although practical implementations may exhibit propagation delay, glitches, and temporary charge storage. They form the computational core of processors, digital signal-processing systems, controllers, memories, communication hardware, and application-specific integrated circuits. Multiplexers select data, decoders generate control signals, adders perform address and arithmetic operations, and multipliers dominate many datapaths in terms of area and energy.

At postgraduate level, the design of a combinational circuit cannot be judged solely by its Boolean correctness. A circuit that implements the correct truth table may still be unsuitable because of excessive delay, power dissipation, silicon area, noise sensitivity, poor signal restoration, or inadequate compatibility with the surrounding logic. VLSI design therefore requires simultaneous consideration of logic function, transistor-level realization, electrical behavior, physical implementation, and workload.

This chapter develops static CMOS, dynamic logic, pass-transistor logic, and transmission-gate logic, followed by their application to multiplexers, decoders, adders, multipliers, and high-performance datapaths. The central theme is design trade-off: speed is often obtained at the expense of power, area, robustness, or design complexity. A suitable architecture is consequently determined by the constraints of the complete system rather than by a single best logic family.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the operation and design trade-offs of static CMOS, dynamic, pass-transistor, and transmission-gate logic.

2. Analyze propagation delay, power dissipation, logical effort, noise margin, signal integrity, and transistor sizing in combinational circuits.

3. Design and compare multiplexers, decoders, adders, and multipliers at gate and transistor levels.

4. Select suitable arithmetic architectures for speed, power, area, and scalability requirements.

5. Identify hazards, charge-sharing effects, threshold-voltage degradation, leakage, and other reliability concerns.

6. Apply structured optimization methods to high-performance datapaths.

From Boolean Function to Transistor Network

A Boolean expression is an abstract specification. Its VLSI implementation consists of interconnected transistors and parasitic capacitances. The designer must map the expression into a circuit whose pull-up and pull-down behavior is complementary, electrically valid, and physically realizable.

In static CMOS, the pull-up network (PUN) uses pMOS transistors to connect the output to the positive supply when the output should be logic 1, while the pull-down network (PDN) uses nMOS transistors to connect it to ground when the output should be logic 0. Series transistors represent logical AND conditions in a conducting path; parallel transistors represent logical OR conditions. A complementary CMOS gate has, ideally, no direct dc path from supply to ground in either stable logic state.

For example, a two-input NAND gate uses parallel pMOS transistors and series nMOS transistors. A two-input NOR gate uses series pMOS transistors and parallel nMOS transistors. The NOR gate is generally slower for comparable sizing because series pMOS devices have relatively poor drive strength due to lower hole mobility. This illustrates why Boolean simplicity does not directly imply equal electrical performance.

The delay of a CMOS gate can be approximated by the product of effective resistance and load capacitance. A first-order model is

t_p ≈ 0.69 R_eq C_L,

where R_eq represents the conducting network and C_L includes gate, diffusion, wire, and input capacitances of subsequent gates. Increasing transistor width reduces resistance but increases parasitic capacitance. Consequently, indiscriminate sizing can increase rather than decrease delay.

Dynamic power is commonly approximated by

P_dyn = α C_L V_DD² f,

where α is the switching activity factor, C_L is switched capacitance, V_DD is supply voltage, and f is the operating frequency. Leakage power becomes increasingly important at low supply voltage and small feature size. Short-circuit power is produced briefly when both pull-up and pull-down networks conduct during an input transition.

Logic Families and Their Electrical Consequences

Static CMOS Logic

Static CMOS is the reference logic family for robust digital design. Its principal advantages are high noise margins, rail-to-rail output levels, negligible static power in the ideal steady state, and tolerance of cascaded logic. The main disadvantages are transistor count, input capacitance, and potentially large diffusion capacitance in complex gates.

A complex CMOS gate can often implement a function in one stage. For example, the function Y = ¬(AB + CD) can be implemented with two series branches, each containing two nMOS devices in series, connected in parallel. The pMOS network is the dual of the nMOS network. Such a gate may be more compact and faster than a realization using several elementary gates, but stacked transistors increase delay and internal capacitance.

Transistor sizing should compensate, within reason, for series stacks. If an nMOS path contains k identical series devices and the reference inverter has width W, each device may initially be sized near kW to maintain a similar effective resistance. This increases input capacitance and does not account fully for internal nodes, layout parasitics, or unequal input arrival times; simulation and physical extraction remain necessary.

Dynamic Logic

Dynamic logic uses a clocked precharge phase and an evaluation phase. In a standard n-type dynamic gate, a pMOS transistor precharges the dynamic node to V_DD when the clock is low. During evaluation, an nMOS evaluation transistor enables a conditional pull-down network. The node either retains its precharged value or discharges according to the input function.

Dynamic logic can be faster and smaller than static CMOS because the evaluation network contains only nMOS transistors and the output need not drive a complementary pMOS network within the same stage. However, the dynamic node is vulnerable to leakage, charge sharing, clock feedthrough, noise, and monotonicity constraints. Inputs to an n-type dynamic gate should generally make only low-to-high transitions during evaluation; a falling input cannot restore a node that has already discharged.

Domino logic adds an inverting static CMOS buffer to a dynamic stage. It guarantees a noninverting stage-to-stage behavior and improves signal restoration. A domino pipeline must be carefully clocked because the dynamic node is evaluated only during a defined phase. Keeper transistors are often added to weakly hold the dynamic node high, but an excessively strong keeper slows legitimate discharge.

Charge sharing occurs when charge initially stored on the dynamic output redistributes to internal capacitances when evaluation begins. If the internal capacitance is C_x and the output capacitance is C_o, a simplified voltage estimate after charge sharing is

V_out ≈ V_DD C_o/(C_o + C_x).

If this voltage falls below the receiving gate's noise tolerance, an erroneous transition may occur. Precharge devices, keeper circuits, transistor ordering, and careful layout can reduce this risk.

Pass-Transistor Logic

Pass-transistor logic uses transistors as switches that pass signals between nodes. It can implement multiplexing and selected Boolean functions with fewer transistors than complementary CMOS. An nMOS passes a strong zero but a degraded one, with the high level limited approximately to V_DD − V_Tn. A pMOS passes a strong one but a degraded zero. Threshold degradation reduces noise margins and may cause severe delay in cascaded stages.

Complementary pass-transistor logic (CPL) uses complementary signal pairs and nMOS networks. It can provide compact and fast implementations for some arithmetic functions, although it often requires input and output inverters and suffers from internal switching activity. Reduced-swing circuits may lower dynamic power but demand restoration stages and careful control of voltage variation.

Transmission-Gate Logic

A transmission gate consists of parallel nMOS and pMOS devices controlled by complementary signals. The nMOS efficiently passes zero, and the pMOS efficiently passes one; together they pass both logic levels with low degradation. Transmission gates are particularly useful in multiplexers, latches, and bus switches.

Their cost includes complementary control generation, two transistors per switch, and a resistance that depends on signal level and transistor sizing. A transmission-gate multiplexer can be more compact than a gate-based multiplexer, but its delay is strongly influenced by the resistance of the selected path and the capacitance at the output.

Comparative Design View

Static CMOS is usually preferred when robustness, noise margin, and straightforward verification dominate. Dynamic logic is attractive in carefully controlled high-speed datapaths. Pass-transistor logic can reduce transistor count in selected structures but requires attention to signal restoration. Transmission gates are well suited to bidirectional or full-swing selection functions. The relevant comparison is not merely transistor count; it includes input capacitance, internal activity, leakage, clock overhead, layout regularity, process variation, and verification burden.

Multiplexers and Decoders as Datapath Primitives

A 2:1 multiplexer implements Y = S̅D_0 + SD_1. A static CMOS implementation may use AND-OR logic, while a transmission-gate implementation uses two switches controlled by S and S̅. The latter often offers a short data path and is naturally extended to larger multiplexers through a tree. A large multiplexer should not usually be built as one enormous complex gate because the resulting transistor stacks and capacitance create poor delay. Balanced trees reduce worst-case path length.

Multiplexer delay depends on data arrival, select arrival, switch resistance, and output capacitance. If select signals are shared across many multiplexers, their capacitance can become a significant clock-like load. Buffering and hierarchical selection are therefore important.

A decoder activates one of several output lines for a given binary input. An n-to-2ⁿ decoder may be formed from predecoders followed by final NAND or NOR stages. Predecoding reduces fan-in and can improve speed and area. However, decoder outputs may glitch when input bits do not change simultaneously. In memory and control applications, such glitches can produce unwanted word-line activity or dynamic power. Enable signals, monotonic dynamic logic, and carefully balanced paths are commonly used to control this behavior.

Adders: From Ripple Carry to Prefix Structures

The one-bit full adder is the basic arithmetic cell. With inputs A, B, and carry-in C_i, its outputs are

S = A ⊕ B ⊕ C_i

C_{i+1} = AB + C_i(A ⊕ B).

The carry equation can also be expressed using generate and propagate signals:

G_i = A_iB_i, P_i = A_i ⊕ B_i,

C_{i+1} = G_i + P_iC_i.

A ripple-carry adder (RCA) connects full adders in series. Its area is approximately linear in word length, and its layout is regular, but the worst-case carry delay also grows approximately linearly. The RCA is often suitable for low-area or low-frequency designs.

A carry-lookahead adder computes carries using group generate and propagate terms. For example,

C_2 = G_1 + P_1G_0 + P_1P_0C_0.

Expanding these expressions reduces carry delay but increases wiring and fan-in. A tree-based prefix adder represents the carry computation with the associative operator

(G,P) ∘ (G',P') = (G + PG', PP').

Kogge–Stone, Brent–Kung, and Han–Carlson adders are examples of prefix structures. Kogge–Stone offers low logic depth and high speed but uses substantial wiring and area. Brent–Kung uses fewer nodes and less wiring, generally at the cost of greater depth. Han–Carlson and related hybrids seek a compromise.

Carry-select adders divide the word into blocks and compute each block twice, once assuming carry-in zero and once assuming carry-in one. Multiplexers select the correct result when the actual carry arrives. The method reduces carry delay but duplicates hardware. Square-root carry-select arrangements balance block sizes so that local computation and selection delays are more evenly distributed.

Carry-skip adders allow a carry to bypass a block when all bits propagate. They use less duplicated hardware than carry-select structures and can be effective when block-level propagation is common. The choice among RCA, carry-lookahead, prefix, carry-select, and carry-skip architectures should be made using word length, timing target, area, routing congestion, power budget, and expected input activity.

The XOR implementation is especially important in adders. A compact XOR may have poor voltage swing or increased sensitivity to input order, whereas a static CMOS XOR is robust but may use more transistors. Full-adder design must therefore evaluate not only transistor count but also carry drive, sum delay, internal glitches, and compatibility with the selected adder architecture.

Multiplication and Partial-Product Reduction

Binary multiplication begins by generating partial products with AND operations. For an n-bit multiplier, the partial products must then be shifted and summed. A straightforward array multiplier has regular layout and predictable wiring, but its delay and area grow significantly with operand size.

The main optimization problem is partial-product reduction. A carry-save adder (CSA) compresses three numbers into two without propagating carries across the entire word. At each bit position, a full adder produces a sum and a carry; the carry is passed to the next column, while the sum remains in its column. Several CSA levels can reduce many partial products to two operands, which are finally added by a carry-propagating adder.

Wallace and Dadda trees are common compressor structures. A Wallace tree reduces the number of rows as aggressively as possible at each level, minimizing approximate reduction depth but often producing irregular wiring. A Dadda tree uses a more controlled schedule, usually reducing hardware and wiring while maintaining comparable performance. Regular array structures are easier to lay out, whereas tree structures generally offer better speed.

Booth recoding reduces the number of partial products by encoding groups of multiplier bits. Radix-2 Booth recoding represents signed multiplication efficiently but provides limited reduction. Higher-radix schemes, such as radix-4, examine overlapping groups and generate multiples such as 0, ±A, and ±2A. The additional encoding and multiple-generation circuitry must be justified by the reduction in partial-product rows.

In low-power applications, operand isolation, clock gating of sequential boundaries, truncated multiplication, and approximate arithmetic may be considered. Such methods are acceptable only when the application-level error tolerance is specified and verified.

High-Performance Datapath Optimization

A datapath is a network of arithmetic and selection elements linked by registers or interface boundaries. Its performance is determined by the longest combinational path, or critical path. Optimization begins by identifying whether the limiting factor is logic depth, fan-out, wire delay, input arrival imbalance, or output loading.

Logical effort provides a useful first-order method for comparing gate structures. A path delay can be represented approximately as

d = gh + p,

where g is logical effort, h is electrical effort or fan-out, and p is parasitic delay. For a multistage path with fixed input and output capacitances, distributing effort across stages near the optimum value can reduce delay. Excessive buffering is not automatically beneficial; each buffer adds area, power, and intrinsic delay.

Pipelining inserts registers to divide a long path into shorter stages. It can increase clock frequency but introduces latency, clock power, area, and possible throughput-control complexity. Retiming moves registers across combinational logic while preserving functional behavior, potentially balancing stage delays. In a multiplier or prefix adder, pipeline placement must also account for operand alignment and control-signal timing.

Wire delay becomes dominant in advanced technologies. A theoretically shallow prefix adder may perform poorly if its long-range generate and propagate wires create routing congestion. Physical-aware synthesis, local prefix structures, wire buffering, placement constraints, and hierarchical datapath organization are therefore essential. Power optimization includes reducing switching capacitance, suppressing glitches, lowering voltage where timing permits, and avoiding unnecessary internal transitions.

Signal integrity requires full-swing logic where cascades demand it, adequate noise margins, controlled slew rates, and protection against coupling. Dynamic nodes should be shielded or physically isolated when sensitive. Clocked dynamic circuits require disciplined clock distribution because clock skew can alter the effective precharge and evaluation intervals.

Applied Case Study: Selecting a 32-Bit Adder for a DSP Datapath

Background

Consider an illustrative design project for a 32-bit fixed-point digital signal processor. The adder lies in the feedback path of a filter and must operate within a short clock period. The design team has a moderate area budget and seeks to limit dynamic power because the circuit is battery operated.

Situation and Problem

A ripple-carry implementation meets the area target but fails timing under worst-case process, voltage, and temperature conditions. A Kogge–Stone prefix adder meets timing in logic-level estimation but produces substantial routing congestion and switching activity after physical implementation. The team must select and optimize an architecture rather than simply choosing the theoretically fastest carry network.

Analysis

The ripple adder has a long serial carry path. The Kogge–Stone adder has low logical depth but many prefix nodes and long interconnects. A Brent–Kung structure has greater logical depth but lower wiring demand. A hybrid Han–Carlson structure offers intermediate characteristics. The team also observes that the sum output is not required in every cycle because a preceding enable signal frequently disables the filter update.

Approach and Solution

The designers select a hybrid prefix adder with localized prefix computation and a final sparse carry generation stage. They use static CMOS for the core arithmetic cells to preserve signal integrity and apply selective transistor sizing to the carry path rather than uniformly enlarging every gate. Operand isolation prevents unnecessary toggling when the update is disabled. The physical design is constrained so that neighboring prefix groups remain close, reducing long wires. Post-layout extraction is used to re-evaluate delay and power.

The team also balances input arrival times to reduce glitches at the sum outputs. Instead of using aggressive dynamic logic, which would require clocked evaluation and additional robustness analysis, the design retains static logic because the timing margin is sufficient after physical optimization.

Outcome

The selected structure provides a better system-level compromise than either extreme. It avoids the ripple adder's serial delay and reduces the routing and switching penalties of a fully expanded Kogge–Stone network. The case illustrates that architecture, circuit style, and physical layout must be optimized together.

Learning Points

The fastest Boolean topology is not necessarily the fastest placed-and-routed circuit. Timing closure must include parasitic extraction, input activity, fan-out, and variation. Power-saving techniques are most effective when applied to inactive operands and high-capacitance nodes. Finally, a robust static implementation may be preferable to a more aggressive logic family when verification and signal integrity are important system constraints.

Challenges, Failure Modes, and Professional Practice

Common mistakes include treating transistor count as a complete measure of area, ignoring internal capacitance, cascading degraded pass-transistor outputs, using dynamic logic without analyzing leakage, and estimating delay without post-layout parasitics. Another frequent error is optimizing nominal delay while neglecting worst-case corners. Low supply voltage, elevated temperature, process variation, aging, and IR drop can all reduce noise margin and drive strength.

Hazards arise when unequal path delays cause temporary output transitions. In synchronous systems, a hazard may be harmless if it settles before sampling, but it still consumes power and can become dangerous in asynchronous control or dynamic circuits. Boolean simplification should therefore be combined with timing analysis rather than performed solely at the symbolic level.

Professional design flows use logic synthesis, static timing analysis, power analysis, transistor-level simulation for critical cells, physical design, parasitic extraction, and corner-based sign-off. Assertions and formal equivalence checking help ensure that high-performance restructuring has not changed functionality. Designers must document assumptions about clock phases, input monotonicity, signal ranges, and acceptable arithmetic error.

Technology Trends and Emerging Directions

FinFET and gate-all-around transistor technologies improve electrostatic control but introduce new parasitic, layout, and variability considerations. Standard-cell libraries increasingly provide multiple threshold-voltage options and drive strengths, enabling selective speed-power optimization. Advanced synthesis tools perform physical-aware mapping, gate sizing, buffer insertion, and multibit arithmetic optimization.

Approximate adders and multipliers are being investigated for machine-learning inference, image processing, and sensor analytics, where bounded numerical error may be preferable to high energy consumption. Emerging accelerators use compressor trees, fused multiply-add units, sparsity-aware datapaths, and data gating to reduce movement and switching. Such approaches require application-level validation; an arithmetic approximation is appropriate only when its error, bias, and corner behavior are understood.

Machine-learning-assisted electronic design automation can predict congestion, suggest arithmetic architectures, and guide placement or sizing. These tools do not eliminate engineering responsibility. Their results must be checked against formal functionality, timing, power, reliability, and manufacturability requirements.

Best-Practice Design Method

A disciplined design process begins with a precise specification of word length, signedness, throughput, latency, voltage, operating corners, and error tolerance. The designer then evaluates several architectures using analytical estimates before implementing representative RTL and critical transistor-level cells. The process should include:

• identifying the critical path and its dominant capacitances;
• selecting a logic family appropriate to robustness and clocking constraints;
• limiting fan-in and stack height where they compromise delay;
• using balanced trees and hierarchical structures for large selection or carry networks;
• preserving full signal swing or adding restoration where necessary;
• evaluating glitches, leakage, charge sharing, and switching activity;
• performing post-layout timing and power analysis at relevant corners; and
• validating arithmetic correctness, overflow behavior, signed operation, and exceptional cases.

The most reliable optimization is usually selective rather than global: improve the actual bottleneck while avoiding unnecessary switching and capacitance elsewhere.

Chapter Summary

Combinational VLSI circuits must be evaluated as electrical systems as well as Boolean networks. Static CMOS provides strong noise margins and full-swing operation, while dynamic, pass-transistor, and transmission-gate logic offer speed or transistor-count benefits with additional constraints. Multiplexers and decoders benefit from hierarchical and balanced organization. Adders range from compact ripple structures to fast but wiring-intensive prefix networks, and multipliers rely on partial-product reduction, carry-save compression, and recoding. High-performance datapath design requires joint optimization of logic depth, transistor sizing, capacitance, wire delay, switching activity, physical layout, and variation. Robust design practice combines architecture-level comparison with post-layout verification and explicit attention to hazards, signal integrity, leakage, and application requirements.

Key Terms

Static CMOS: Complementary logic using pMOS pull-up and nMOS pull-down networks with a stable output in both logic states.

Pull-up network: The transistor network that connects a CMOS output to the positive supply.

Pull-down network: The transistor network that connects a CMOS output to ground.

Dynamic logic: Clocked logic that stores a precharged value on a capacitance and conditionally evaluates it.

Domino logic: Dynamic logic followed by a static inverter, normally used in cascaded noninverting stages.

Pass-transistor logic: Logic that uses transistors as switches to pass signals between circuit nodes.

Transmission gate: Parallel nMOS and pMOS pass devices controlled by complementary signals.

Charge sharing: Redistribution of stored charge between a dynamic node and internal capacitances.

Noise margin: The allowable noise voltage that can be tolerated without incorrect logic interpretation.

Logical effort: A method for estimating and optimizing gate delay relative to a reference inverter.

Ripple-carry adder: An adder in which each carry waits for the preceding bit's carry output.

Generate signal: A signal indicating that a bit position produces a carry independently of its input carry.

Propagate signal: A signal indicating that a bit position passes an incoming carry to the next position.

Prefix adder: An adder that computes group generate and propagate signals using a parallel associative network.

Carry-save adder: A circuit that reduces three operands to two without immediate global carry propagation.

Wallace tree: An aggressive partial-product reduction tree for multiplication.

Booth recoding: A multiplier encoding technique that reduces the number of partial products, especially for signed operands.

Critical path: The longest or most timing-limiting combinational path in a design.

Operand isolation: A technique that prevents inactive data from switching internal datapath circuitry.

Review Questions

Short Answer Questions

1. Why does a NOR gate generally have greater delay than a NAND gate with the same number of inputs?

2. What is the purpose of a keeper transistor in domino logic?

3. Why does an nMOS pass a strong zero but a degraded one?

4. Define generate and propagate signals in an adder.

5. What is the principal function of a carry-save adder in a multiplier?

Long Answer Questions

1. Explain static CMOS, dynamic logic, pass-transistor logic, and transmission-gate logic, comparing their speed, power, area, and robustness.

2. Derive the operation of a full adder and discuss how ripple-carry, carry-lookahead, and prefix adders differ in delay and implementation cost.

3. Describe charge sharing, leakage, clock feedthrough, and monotonicity constraints in dynamic logic.

4. Explain the organization of a high-performance binary multiplier using partial-product generation, compressor trees, and a final carry-propagating adder.

5. Discuss how logical effort, pipelining, transistor sizing, buffering, and physical-aware design contribute to datapath optimization.

Analytical / Application Questions

1. A 32-bit adder must meet a strict timing target but has limited routing resources. Compare a Kogge–Stone, Brent–Kung, and hybrid prefix architecture and recommend one with justification.

2. A transmission-gate multiplexer is followed by a large CMOS load. Identify the major delay components and propose circuit-level methods to improve its performance without sacrificing full-swing operation.

3. A dynamic node loses voltage during evaluation because of charge sharing. Explain how you would diagnose the problem and modify the circuit while considering keeper strength, leakage, and noise margin.

22. Multiple Choice Questions with Answers

Question 1

Which property is a principal advantage of static CMOS logic?

A. It requires a precharge clock for every gate

B. It provides rail-to-rail outputs and strong noise margins

C. It always uses fewer transistors than pass-transistor logic

D. It eliminates all dynamic power

Correct Answer: B. It provides rail-to-rail outputs and strong noise margins

Question 2

In an n-type dynamic gate, what normally occurs during the precharge phase?

A. The dynamic node is discharged through the evaluation network

B. The dynamic node is connected to ground by a pMOS transistor

C. The dynamic node is charged toward V_DD by a pMOS transistor

D. The output is forced to an analog midpoint

Correct Answer: C. The dynamic node is charged toward V_DD by a pMOS transistor

Question 3

Why can an nMOS pass-transistor output representing logic 1 be degraded?

A. The nMOS cannot conduct electrons

B. The high level is limited approximately by threshold-voltage loss

C. The pMOS pull-up always shorts the output to ground

D. The input capacitance becomes zero

Correct Answer: B. The high level is limited approximately by threshold-voltage loss

Question 4

What is the main purpose of a transmission gate in a multiplexer?

A. To pass both logic levels with reduced threshold degradation

B. To generate a carry without input signals

C. To provide permanent isolation from the power supply

D. To implement only NAND functions

Correct Answer: A. To pass both logic levels with reduced threshold degradation

Question 5

For a ripple-carry adder, which factor primarily causes delay to increase with word length?

A. The serial propagation of carry from lower to higher bit positions

B. The absence of XOR operations in every bit slice

C. The use of only pMOS transistors

D. The lack of a power supply during addition

Correct Answer: A. The serial propagation of carry from lower to higher bit positions

Question 6

Which statement best describes a carry-save adder?

A. It immediately propagates every carry across the complete word

B. It converts three operands into two while postponing carry propagation

C. It can add only unsigned one-bit operands

D. It replaces all partial-product generation

Correct Answer: B. It converts three operands into two while postponing carry propagation

Question 7

A Kogge–Stone adder is often fast logically but may be costly physically because it has

A. No generate or propagate nodes

B. Large wiring demand and routing congestion

C. Only one full-adder cell

D. No switching activity

Correct Answer: B. Large wiring demand and routing congestion

Question 8

Which technique directly reduces unnecessary switching in an inactive arithmetic datapath?

A. Operand isolation

B. Increasing every transistor width

C. Removing all output buffers

D. Using a longer ripple chain

Correct Answer: A. Operand isolation

Question 9

What is charge sharing in a dynamic circuit?

A. Permanent short-circuit current between the supplies

B. Redistribution of stored charge between a dynamic node and internal capacitances

C. The transfer of data between two clock domains

D. The generation of complementary inputs by an inverter

Correct Answer: B. Redistribution of stored charge between a dynamic node and internal capacitances

Question 10

Why can a theoretically shallow arithmetic network fail to provide the expected post-layout speed?

A. Boolean equations cannot be implemented in silicon

B. Interconnect parasitics and routing congestion may dominate delay

C. Static CMOS has no capacitance

D. Carry signals never depend on wiring

Correct Answer: B. Interconnect parasitics and routing congestion may dominate delay