3. CMOS Circuit Fundamentals

Introduction and Context

Complementary metal–oxide–semiconductor (CMOS) logic is the dominant design style for modern digital integrated circuits. Its importance arises from a useful combination of nearly zero static power in ideal steady-state operation, high noise immunity, scalable implementation, and compatibility with large-scale integration. Although CMOS gates are often introduced as simple combinations of p-channel and n-channel MOSFETs, reliable high-performance design requires a quantitative understanding of voltage transfer characteristics, noise margins, delay, power, transistor sizing, parasitic effects, and process variation.

A CMOS circuit is not merely a Boolean expression implemented with transistors. It is an analog electrical system whose voltages and currents must satisfy digital requirements. A logic gate must distinguish valid logic levels, reject disturbances, charge and discharge capacitances within a specified time, and operate across variations in process, supply voltage, temperature, and workload. This chapter develops the device-level foundations needed to make those judgments.

The discussion assumes the basic operation of enhancement-mode MOS transistors and Boolean logic. The focus is on static CMOS, while dynamic power, leakage, and scaling trends are also considered because they strongly influence contemporary design decisions.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain the operation of CMOS inverters and complementary pull-up and pull-down networks.

2. Derive and interpret the voltage transfer characteristic and switching threshold of a CMOS inverter.

3. Calculate high and low noise margins and relate them to logic robustness.

4. Estimate propagation delay using resistance–capacitance models and understand the role of logical effort.

5. Analyze dynamic, short-circuit, and leakage power.

6. Select transistor widths using drive-strength, rise/fall-time, fan-out, and area considerations.

7. Identify important parasitic capacitances and their influence on circuit behavior.

8. Evaluate designs over process, voltage, and temperature corners.

9. Apply these concepts to practical CMOS gate design and debugging.

The CMOS Inverter as a Reference Circuit

The CMOS inverter contains a pMOS transistor connected between the supply voltage \(V_{DD}\) and the output, and an nMOS transistor connected between the output and ground. Their gates are connected to the input. When the input is low, the nMOS is off and the pMOS is on, so the output is charged toward \(V_{DD}\). When the input is high, the pMOS is off and the nMOS is on, so the output is discharged toward ground.

The complementary arrangement produces a rail-to-rail output in steady state. Ideally, one transistor is off when the other is on, and no direct dc path exists from \(V_{DD}\) to ground. This explains the low static power of ideal CMOS logic. In practice, subthreshold current, gate leakage, junction leakage, and leakage through imperfectly off devices produce nonzero static power.

For an nMOS transistor, conduction begins when \(V_{GS}\) exceeds the threshold voltage \(V_{TN}\). For a pMOS transistor, it is convenient to use the magnitude \(|V_{TP}|\); conduction occurs when \(V_{SG}>|V_{TP}|\). The strength of a transistor is often represented by

\[

\beta_n=\mu_n C_{ox}(W/L)_n, \qquad \beta_p=\mu_p C_{ox}(W/L)_p,

\]

where \(W\) and \(L\) are channel width and length, \(\mu\) is carrier mobility, and \(C_{ox}\) is oxide capacitance per unit area. Because electron mobility is usually higher than hole mobility, a pMOS generally requires greater width than an nMOS to provide comparable drive current.

Voltage Transfer Characteristic

The voltage transfer characteristic (VTC) plots output voltage \(V_O\) against input voltage \(V_I\). It contains five useful regions:

• At low input voltage, the pMOS is on and the nMOS is off; the output is approximately \(V_{DD}\).
• As the input rises above the nMOS threshold, both devices may conduct and the output begins to fall.
• In the transition region, both transistors conduct substantially. Small changes in input can produce large changes in output.
• At high input voltage, the pMOS is off and the nMOS is on; the output is approximately zero.
• The slope in the transition region indicates voltage gain and switching sharpness.

The switching point \(V_M\) is commonly defined by \(V_I=V_O=V_M\). Under a simplified long-channel model, both devices are often assumed to be in saturation at this point. Equating their drain currents gives an approximate relationship:

\[

\beta_n(V_M-V_{TN})^2=\beta_p(V_{DD}-V_M-|V_{TP}|)^2.

\]

Thus,

\[

V_M=\frac{\sqrt{\beta_p}(V_{DD}-|V_{TP}|)+\sqrt{\beta_n}V_{TN}}

{\sqrt{\beta_n}+\sqrt{\beta_p}}.

\]

The exact value depends on device models and operating conditions. Increasing nMOS strength shifts the switching point toward a lower input voltage, while increasing pMOS strength shifts it upward. A roughly centered inverter is often desirable, but the correct choice depends on the required noise margins, rise/fall symmetry, energy, and system-level timing.

The small-signal gain near the switching point is large because the pMOS and nMOS currents change rapidly with input voltage. High gain improves the restoration of degraded logic levels and helps cascade gates reliably. Excessively aggressive sizing, however, increases input capacitance and may increase the delay of the preceding stage.

Noise Margins and Logic Validity

Digital signals are not required to have one exact voltage. A receiver interprets a range of voltages as logic zero or logic one. Four quantities describe this behavior:

• \(V_{IL}\): the largest input voltage guaranteed to be interpreted as low.
• \(V_{IH}\): the smallest input voltage guaranteed to be interpreted as high.
• \(V_{OL}\): the largest output voltage guaranteed as low.
• \(V_{OH}\): the smallest output voltage guaranteed as high.

The low and high noise margins are

\[

NM_L=V_{IL}-V_{OL}, \qquad NM_H=V_{OH}-V_{IH}.

\]

For a well-designed CMOS inverter, \(V_{OL}\) is close to zero and \(V_{OH}\) is close to \(V_{DD}\). The values of \(V_{IL}\) and \(V_{IH}\) are often obtained from points on the VTC where the magnitude of the voltage gain is one. A larger noise margin means that a signal can tolerate more coupled noise, supply disturbance, ground bounce, or interconnect interference.

Noise margin is not identical to gain. A steep VTC can provide strong logic regeneration, but the allowable input ranges and output levels must also be considered. Lower supply voltage generally reduces the available voltage separation and therefore makes noise immunity more sensitive to threshold variation, coupling, and ground noise.

Static CMOS Logic Gates

A static CMOS gate is constructed from two complementary transistor networks. The pull-down network (PDN), made of nMOS transistors, conducts when the output should be zero. The pull-up network (PUN), made of pMOS transistors, conducts for the complementary condition and charges the output to one.

The PDN is formed directly from the Boolean condition that produces a low output. Series nMOS transistors implement an AND condition: all devices must conduct. Parallel nMOS transistors implement an OR condition: any conducting path can discharge the output. The PUN is the dual network: series pMOS corresponds to parallel nMOS, and parallel pMOS corresponds to series nMOS.

For a two-input NAND gate, the nMOS devices are in series and the pMOS devices are in parallel. The output is low only when both inputs are high. For a two-input NOR gate, the nMOS devices are in parallel and the pMOS devices are in series. The output is low when either input is high.

The complementary construction ensures that, in a valid steady state, the output is connected either to the supply or to ground, but not both. Complex gates can therefore be designed by first specifying the discharge condition, constructing the nMOS network, and then deriving its dual pMOS network.

The topology affects delay. Series devices increase effective resistance, while parallel devices increase capacitance at internal and input nodes. A NAND gate with a long nMOS stack usually has a weaker pull-down path than an inverter. A NOR gate with a pMOS stack may have a particularly slow pull-up because pMOS devices are already weaker than nMOS devices.

Delay, Resistance, and Logical Effort

A logic transition requires charging or discharging capacitance. A first-order delay estimate is

\[

t_p\approx 0.69R_{eq}C_L,

\]

where \(R_{eq}\) is the effective on-resistance of the conducting network and \(C_L\) includes external load, gate capacitance of following stages, wire capacitance, diffusion capacitance, and other parasitics. Rising and falling delays should be considered separately because pMOS and nMOS strengths differ.

The propagation delays are commonly defined as the time from the 50% point of the input transition to the 50% point of the output transition. Rise time and fall time instead describe the movement of the output between specified voltage limits, often 10% and 90% of the supply.

A more useful abstraction for multistage design is logical effort. The delay of a gate can be approximated by

\[

d=gh+p,

\]

where \(g\) is logical effort, \(h=C_L/C_{in}\) is electrical effort or fan-out, and \(p\) is parasitic delay. For a path of several stages, the path effort is the product of logical efforts and electrical effort. If branching is present, branching effort is also included. A common first-order sizing rule is to distribute effort approximately evenly among stages, often with a stage effort near three to four for practical CMOS paths.

Logical effort does not replace transistor-level simulation. It is a design method for comparing topologies, selecting stage sizes, and estimating delay early in the design process. It is especially valuable when the designer must drive a large capacitance without unnecessarily enlarging every transistor.

Transistor Sizing, Fan-Out, and Parasitics

Sizing is a multi-objective problem. Wider devices reduce channel resistance and improve drive strength, but they increase gate capacitance, diffusion capacitance, area, dynamic power, and the load seen by the preceding stage. Minimum-length devices are often fastest in digital logic but may have greater leakage and poorer control of short-channel effects. Larger channel length can reduce leakage and improve matching, at the cost of speed and area.

An inverter is often sized by choosing the nMOS width as a reference and increasing pMOS width to compensate for lower hole mobility. The appropriate ratio is process dependent; using a fixed universal ratio is poor practice. The ratio should be evaluated using simulated rise and fall times, switching threshold, energy, and corner results.

Fan-out is the number or, more accurately, the capacitive burden of loads driven by a gate. A gate driving four identical gate inputs has a nominal fan-out of four, but actual delay also depends on wire capacitance and the input sizes of those gates. Large fan-out may require a buffer chain. A chain of progressively larger inverters is faster and often more energy efficient than one minimum-size inverter driving the entire load.

Important parasitic capacitances include:

• Gate capacitance, associated with the oxide and channel region.
• Source and drain junction capacitance, which varies with voltage.
• Overlap capacitance between gate and source or drain.
• Interconnect capacitance to neighboring wires, substrate, and power rails.
• Internal node capacitance in transistor stacks.

Internal capacitances can dominate the delay of complex gates even when the external load is small. Charge sharing may also cause temporary voltage excursions at internal nodes. Careful ordering of series transistors, transistor folding, and layout-aware sizing can reduce these effects.

Power Dissipation in CMOS

CMOS power has three principal components. Dynamic switching power is approximately

\[

P_{dyn}=\alpha C_L V_{DD}^{2}f,

\]

where \(\alpha\) is the activity factor, \(C_L\) is switched capacitance, and \(f\) is switching frequency. The quadratic dependence on supply voltage makes voltage reduction highly effective for energy reduction, although lower voltage also reduces noise margin and drive current.

Short-circuit power occurs during an input transition when both the pMOS and nMOS are temporarily on. It increases with slow input edges, large supply voltage, and device strength. Ensuring adequate input slew and avoiding unnecessarily large devices reduces this component.

Static or leakage power is modeled as

\[

P_{leak}=V_{DD}I_{leak}.

\]

Leakage includes subthreshold conduction, gate-oxide tunneling, junction leakage, and gate-induced drain leakage. It rises strongly with temperature and is highly sensitive to threshold voltage and process variation. Low-threshold devices improve speed but generally increase leakage, whereas high-threshold devices reduce leakage but slow transitions.

Energy per transition is often more meaningful than average power for an isolated event. In a practical system, however, clock activity, glitching, memory access, and standby intervals determine the total energy budget. Logic restructuring that reduces unnecessary transitions can be as important as transistor sizing.

Process, Voltage, and Temperature Corners

A design that works at nominal conditions may fail at a corner. Process corners represent variations in transistor characteristics. Common labels include fast–fast (FF), slow–slow (SS), fast nMOS/slow pMOS (FS), and slow nMOS/fast pMOS (SF). Voltage corners represent supply variation, while temperature corners represent the operating thermal range.

The SS corner often produces the largest delay, but the worst leakage commonly occurs in a fast, high-temperature condition. Low supply voltage reduces drive and noise margin. Temperature increases usually reduce mobility and speed, although leakage rises substantially. The actual worst case depends on the technology and the metric being measured.

Sign-off analysis should therefore examine at least:

1. Functional correctness over all specified corners.

2. Setup, hold, and propagation timing under slow and fast conditions.

3. Noise margins and output levels.

4. Dynamic and leakage power.

5. Electromigration, IR drop, and supply integrity where relevant.

6. Statistical variation caused by mismatch and random process effects.

Corner analysis is best combined with extracted parasitic simulation. Pre-layout estimates are useful for architecture and sizing, but routing can change capacitance, coupling, delay, and even logic behavior.

An Applied Design Scenario: A Low-Power Control-Path Inverter Chain

Background

Consider an illustrative design in which a control signal generated by a small CMOS gate must drive a long on-chip control line and the inputs of several receiving gates. The control path is timing-sensitive, but it is also active during a battery-powered operating mode.

Problem

A minimum-size inverter connected directly to the line produces a slow transition. Increasing its width improves the final transition but makes the original gate heavily loaded. The designer must reduce delay without allowing dynamic power and leakage to grow excessively.

Analysis

The load consists of receiver gate capacitance, wire capacitance, and coupling to adjacent conductors. The minimum-size driver has a high electrical effort, so its delay is dominated by \(R_{eq}C_L\). A very large single inverter would reduce output resistance but impose a large input capacitance on the preceding stage. In addition, the larger diffusion regions increase parasitic capacitance and switching energy.

Approach

The designer inserts a tapered chain of inverters. The first stage remains relatively small, and later stages increase in size so that the capacitance ratio between successive stages is approximately balanced. Logical-effort estimates provide initial sizes; transistor-level simulation then refines them using extracted wire capacitance. Separate rise and fall measurements are made, and pMOS widths are adjusted to compensate for mobility imbalance.

The chain is simulated at nominal, SS/low-voltage/hot, and FF/high-voltage/cold conditions. The slow corner determines the maximum delay, while the fast hot corner is examined for leakage and minimum pulse-width behavior. If standby leakage is important, high-threshold devices or a power-gating strategy may be considered.

Outcome

The tapered chain reduces delay compared with the minimum-size driver while avoiding the excessive input capacitance of a single oversized inverter. The final design is accepted only after timing, noise margin, power, and corner requirements are simultaneously satisfied. The exact optimum is not determined by delay alone; it is a Pareto choice among speed, energy, area, and robustness.

Learning Points

The scenario illustrates four professional practices: estimate before simulating, distinguish external from parasitic capacitance, evaluate rise and fall paths separately, and optimize across corners rather than at nominal conditions only.

Design Challenges and Common Mistakes

A frequent mistake is to treat transistor count as the only measure of gate quality. Two gates with the same number of transistors may have very different delay because of stack depth, internal capacitance, and input-dependent paths. Another mistake is to use the same pMOS-to-nMOS ratio for every process and load. Mobility, threshold voltage, layout, and target transition symmetry must be considered.

Ignoring input slew can lead to underestimation of short-circuit power and delay. Ignoring wire parasitics causes optimistic timing, especially in advanced technologies where interconnect delay may dominate. Designers should also avoid interpreting a nominal VTC as proof of robust logic; noise margins must be evaluated at specified corners.

Power optimization can create new risks. Lowering supply voltage reduces switching energy but may increase delay and susceptibility to noise. Lowering threshold voltage improves performance but increases leakage. Aggressive transistor upsizing reduces resistance while increasing capacitance and energy. These trade-offs require system-level priorities rather than isolated optimization.

Professional and Responsible Design Practice

CMOS design has professional consequences beyond functional correctness. A timing failure can cause unsafe control behavior, while excessive power can produce thermal stress and shorten product life. Designers should document assumptions, model limits, corner definitions, and verification coverage. Reproducible simulation conditions and traceable design rules are essential in safety-critical, medical, automotive, and infrastructure applications.

Standard-cell libraries and automated synthesis tools use characterized delay, power, noise, and leakage models. The quality of those models depends on accurate transistor simulation, layout extraction, and process information. Engineers should not apply library data outside its characterized voltage, temperature, loading, and slew ranges without qualification.

Current Directions

Modern CMOS design increasingly combines multi-threshold devices, adaptive body bias, power gating, multi-voltage domains, and dynamic voltage and frequency scaling. FinFET and gate-all-around devices improve electrostatic control compared with traditional planar MOSFETs, but parasitic resistance, capacitance, variability, and thermal constraints remain important. Standard-cell optimization increasingly uses automated characterization, statistical timing, machine-learning-assisted exploration, and layout-aware synthesis.

These developments do not eliminate the fundamentals presented here. Transfer characteristics, noise margins, effective resistance, capacitance, switching activity, leakage, and corner analysis remain the basis for understanding and validating more advanced technologies.

Best Practices for CMOS Gate Design

1. Begin with the required logic function and identify the critical pull-up and pull-down paths.

2. Use complementary networks so that valid steady states do not create a direct supply-to-ground path.

3. Estimate delay using resistance–capacitance and logical-effort models before detailed simulation.

4. Size pMOS and nMOS devices using measured rise/fall behavior rather than an assumed universal ratio.

5. Include fan-out, wire capacitance, internal nodes, and extracted parasitics.

6. Evaluate dynamic, short-circuit, and leakage power separately.

7. Check noise margins and logic levels at all required process, voltage, and temperature corners.

8. Use tapered buffers for large capacitive loads.

9. Treat low-voltage, high-temperature, and high-leakage conditions explicitly.

10. Verify the final layout with design-rule checking, extraction, and post-layout simulation.

Chapter Summary

CMOS logic uses complementary pMOS and nMOS networks to obtain rail-to-rail logic with very low ideal static power. The CMOS inverter provides the fundamental model for understanding voltage transfer characteristics, switching threshold, gain, and noise margins. Static gates are built from a pull-down network and its dual pull-up network; series and parallel topology determine both Boolean operation and electrical performance.

Delay is governed by effective resistance, load capacitance, parasitic capacitance, input slew, and topology. Logical effort provides a useful early design framework for comparing gates and sizing multistage paths. Power consists mainly of dynamic switching power, short-circuit power, and leakage power, each requiring different optimization methods. Transistor sizing therefore involves trade-offs among delay, energy, area, noise immunity, and leakage.

Reliable CMOS design requires analysis over process, voltage, and temperature corners, preferably with extracted parasitics. Professional design practice combines analytical estimates, circuit simulation, layout-aware verification, and documented assumptions. These principles remain applicable as CMOS technologies evolve toward advanced transistor structures and increasingly automated design flows.

Key Terms

CMOS: Logic technology using complementary pMOS and nMOS transistors.

Pull-up network: pMOS network that connects an output to the positive supply.

Pull-down network: nMOS network that connects an output to ground.

Voltage transfer characteristic: Relationship between input and output voltage of a logic circuit.

Switching threshold: Input voltage at which an inverter is commonly considered to have equal input and output voltages.

Noise margin: Tolerable noise voltage that does not cause an incorrect logic interpretation.

\(V_{IL}\): Maximum input voltage guaranteed to be interpreted as low.

\(V_{IH}\): Minimum input voltage guaranteed to be interpreted as high.

Logical effort: Relative measure of a gate’s drive difficulty compared with a reference inverter.

Fan-out: Electrical load imposed by the inputs and interconnect driven by a gate.

Parasitic capacitance: Unintended or intrinsic capacitance arising from devices, junctions, overlaps, and wiring.

Dynamic power: Power consumed in charging and discharging capacitances during switching.

Short-circuit power: Power dissipated when both pull-up and pull-down devices conduct during a transition.

Leakage power: Power caused by nonzero current when a circuit is nominally static.

Propagation delay: Time between a specified input transition point and the corresponding output transition point.

Process corner: Model representing a particular combination of manufacturing variations.

Electrical effort: Ratio of load capacitance to input capacitance.

Threshold voltage: Minimum effective gate-to-source voltage required for strong MOS conduction.

Charge sharing: Redistribution of charge among connected parasitic and internal capacitances.

Tapered buffer: Series of progressively larger gates used to drive a large capacitive load efficiently.

Review Questions

Short Answer Questions

1. Why does an ideal CMOS inverter consume negligible static power in a valid steady state?

2. Define \(NM_L\) and \(NM_H\).

3. How do series and parallel nMOS devices implement Boolean conditions?

4. State the principal dependence of dynamic power on supply voltage.

5. Why are pMOS transistors usually made wider than nMOS transistors?

Long Answer Questions

1. Explain the operation of a CMOS inverter and derive the approximate expression for its switching threshold.

2. Describe the construction of NAND and NOR gates using complementary pull-up and pull-down networks.

3. Explain logical effort and show how it assists the sizing of a multistage driver.

4. Discuss dynamic, short-circuit, and leakage power, including methods for reducing each component.

5. Explain why process, voltage, and temperature corner analysis is essential in CMOS circuit validation.

Analytical / Application Questions

1. A CMOS inverter drives a capacitance that is four times its input capacitance. Explain how a tapered inverter chain could reduce delay and identify the associated power trade-off.

2. A gate has acceptable nominal delay but fails at low supply voltage and high temperature. Analyze the likely causes and propose design changes.

3. A two-input NOR gate has a much slower rising transition than falling transition. Relate this behavior to transistor topology and propose a sizing strategy.

22. Multiple Choice Questions with Answers

Question 1

At the switching point of a CMOS inverter under the simplified long-channel model, which condition is used?

A. The pMOS is off and the nMOS is in cutoff

B. The input voltage is zero

C. The pMOS and nMOS drain currents are equal

D. The output voltage is always equal to ground

Correct Answer: C. The pMOS and nMOS drain currents are equal

Question 2

Which expression correctly defines the high noise margin?

A. VIL − VOL

B. VOH − VIH

C. VIH − VOL

D. VOH − VIL

Correct Answer: B. VOH − VIH

Question 3

In a CMOS NAND gate, the nMOS transistors are normally arranged:

A. In parallel

B. In series

C. With gates tied to VDD

D. As a transmission-gate pair

Correct Answer: B. In series

Question 4

For a fixed capacitance and switching activity, reducing VDD from V to V/2 ideally changes dynamic power by what factor?

A. One-half

B. One-fourth

C. Two

D. Four

Correct Answer: B. One-fourth

Question 5

A gate with large electrical effort is most likely to exhibit increased delay because:

A. Its threshold voltage becomes zero

B. Its effective resistance must charge a relatively large load capacitance

C. Its pMOS network is permanently off

D. Its leakage current disappears

Correct Answer: B. Its effective resistance must charge a relatively large load capacitance

Question 6

Why is a pMOS commonly made wider than an nMOS in an inverter?

A. Holes generally have lower mobility than electrons

B. pMOS devices cannot conduct at high voltage

C. Wider pMOS devices reduce gate oxide thickness

D. nMOS devices have no parasitic capacitance

Correct Answer: A. Holes generally have lower mobility than electrons

Question 7

Which condition commonly produces a large leakage current?

A. Low temperature with zero supply voltage

B. High temperature combined with a fast device condition

C. An ideal cutoff model at nominal voltage

D. A purely capacitive open circuit

Correct Answer: B. High temperature combined with a fast device condition

Question 8

A tapered buffer chain is primarily used to:

A. Eliminate all leakage current

B. Drive a large capacitance more efficiently than one minimum-size gate

C. Make every transistor minimum length

D. Convert an nMOS network into a pMOS network

Correct Answer: B. Drive a large capacitance more efficiently than one minimum-size gate

Question 9

Which event produces short-circuit power in a CMOS inverter?

A. Both pMOS and nMOS conduct simultaneously during an input transition

B. Both devices remain off at steady state

C. Only the pMOS conducts while the output is high

D. A load capacitance is permanently disconnected

Correct Answer: A. Both pMOS and nMOS conduct simultaneously during an input transition

Question 10

A two-input NOR gate has a slow rising output mainly because its pull-up path:

A. Uses parallel nMOS devices

B. Contains series pMOS devices, which are relatively weak

C. Has no input capacitance

D. Always has zero parasitic capacitance

Correct Answer: B. Contains series pMOS devices, which are relatively weak