11. Quantum, Nanoelectronic, and Emerging Devices

Introduction and Context

Semiconductor-device engineering is entering a regime in which device dimensions, material composition, and information-storage mechanisms are controlled at nearly atomic scales. Conventional device theory remains indispensable, but it is no longer sufficient by itself to describe structures whose dimensions are comparable with the electron wavelength, whose operation depends on individual electrons, or whose functionality arises from spin, ionic motion, or collective material states.

This chapter examines a group of devices that extend semiconductor electronics beyond the classical field-effect transistor: quantum-confined structures, resonant-tunneling devices, single-electron devices, nanowire and two-dimensional-material field-effect transistors, spintronic devices, memristive elements, and neuromorphic hardware. These technologies do not represent a single replacement technology. Rather, they provide different solutions to different limitations of conventional electronics, including short-channel effects, power dissipation, memory-wall constraints, and the inefficiency of implementing brain-like computation with conventional processors and memory.

A central theme is that nanoscale operation creates both opportunities and constraints. Quantum confinement can improve electrostatic control, but it also makes energy levels discrete. Tunneling can enable extremely fast switching, but leakage and fabrication variability become serious concerns. Single-electron operation promises ultralow-energy logic, yet thermal noise and charge-background fluctuations can prevent room-temperature operation. Similarly, two-dimensional materials offer atomically thin channels, while contacts, defects, and large-area integration remain difficult. The appropriate evaluation of an emerging device therefore requires more than a comparison of nominal speed or feature size; it requires consideration of manufacturability, variability, reliability, architecture, and application context.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain how quantum confinement modifies the density of states and carrier energy in semiconductor structures.

2. Describe tunneling, resonant tunneling, Coulomb blockade, and single-electron transport.

3. Compare nanowire, carbon-nanotube, and two-dimensional-material FETs with conventional MOSFETs.

4. Explain the operating principles and applications of spintronic, memristive, and neuromorphic devices.

5. Evaluate device performance using speed, energy, gain, variability, endurance, retention, and scalability criteria.

6. Identify fabrication, thermal, interconnect, reliability, and system-integration constraints.

7. Select suitable emerging-device technologies for representative engineering applications.

From Classical Scaling to Quantum Engineering

In a classical semiconductor model, carriers occupy continuous energy bands and device currents are determined mainly by drift, diffusion, electrostatics, and scattering. When one or more device dimensions become comparable with the de Broglie wavelength or the characteristic confinement length of carriers, boundary conditions quantize carrier motion. The resulting energy spectrum is no longer continuous in every direction.

For an ideal electron confined in a rectangular region, the allowed energy levels can be approximated by

E(nx, ny, nz) = (h²/8m*)[(nx²/Lx²) + (ny²/Ly²) + (nz²/Lz²)],

where m* is the effective mass, Lx, Ly, and Lz are confinement dimensions, and nx, ny, and nz are positive integers. Although real semiconductor structures require band-structure and electrostatic models, the expression shows the key dependence: reducing a confinement dimension increases the separation between energy levels. Quantum effects become especially important when this energy separation is comparable with thermal energy kT or with the energy broadening caused by scattering and measurement.

The density of states also changes with dimensionality. In a bulk three-dimensional material, the density of states varies approximately as the square root of energy above the band edge. In a quantum well, where carriers are confined in one direction, the density of states is step-like. In a quantum wire, confined in two directions, it has sharp one-dimensional subbands. In a quantum dot, confined in all three directions, the states are discrete, resembling an artificial atom. These changes affect optical absorption, carrier injection, threshold voltage, transport, and noise.

Quantum confinement can be beneficial because it permits engineering of energy levels and strengthens electrostatic control. It can also be harmful because small dimensional fluctuations produce significant threshold-voltage and current variations. At nanoscale dimensions, interfaces and surfaces occupy a large fraction of the device, so surface roughness, defects, trapped charge, and contact resistance become central design parameters rather than secondary imperfections.

Tunneling and Resonant Transport

Quantum tunneling is the transmission of a carrier through a potential barrier that would be classically forbidden. For a rectangular barrier of height Φ and thickness t, a simplified transmission dependence is

T ∝ exp[-2κt], where κ = √(2m*Φ)/ħ.

The exponential dependence on barrier thickness makes tunneling extremely sensitive to process variation. It also permits useful functions such as nonvolatile switching, negative differential resistance, and charge transfer through very thin insulating layers.

A resonant-tunneling diode (RTD) consists typically of a quantum well between two potential barriers. Electrons incident from one contact can tunnel through the first barrier, occupy a quasi-bound state in the well, and tunnel through the second barrier. When the electron energy aligns with the quasi-bound level, transmission rises sharply. As the applied voltage increases further, alignment is lost and current decreases, producing a region of negative differential resistance (NDR), in which dI/dV is negative.

The peak-to-valley current ratio, peak current density, resonance width, and voltage position of the resonance are important RTD parameters. An RTD can be combined with a transistor to form resonant-tunneling logic, multivalued logic, oscillators, and high-frequency circuits. Its attraction is not simply high speed; the NDR characteristic can implement functions with fewer devices than conventional Boolean logic. However, low voltage gain, limited noise margin, temperature sensitivity, and process control requirements complicate large-scale digital integration.

Resonant tunneling also appears in quantum-cascade lasers and resonant-tunneling transistors. In these devices, the engineered alignment of energy states controls carrier injection and recombination. The general design principle is energy-selective transport: rather than allowing carriers to cross a broad range of energies, the structure selectively enhances transmission at designed energies.

Single-Electron Devices and Coulomb Blockade

A single-electron transistor (SET) controls current through a small conducting island connected to source and drain by tunnel junctions. A gate capacitively controls the island potential. If the island has total capacitance CΣ, adding one electron requires an approximate charging energy

Ec = e²/(2CΣ).

When Ec is greater than the thermal energy kT and the tunnel resistance is sufficiently high, charge transfer is suppressed except at particular gate voltages. This phenomenon is Coulomb blockade. Conductance then occurs in periodic regions of gate voltage known as Coulomb oscillations.

The SET differs fundamentally from a MOSFET. A MOSFET modulates a continuous or quasi-continuous channel charge, whereas an SET regulates individual-electron tunneling events. The device can achieve very high charge sensitivity and extremely low energy per operation. Applications include electrometers, charge sensors, photon detectors, spectroscopy, quantum-information interfaces, and specialized ultra-low-power circuits.

The main difficulty is operating temperature. To observe robust Coulomb blockade, the charging energy must exceed thermal fluctuations. This requires a very small island, low-temperature operation, or both. Background charges in the substrate and nearby dielectrics shift the oscillation pattern and cause instability. Furthermore, an SET generally provides low current and limited voltage gain, making fan-out and signal restoration difficult. Practical circuits may therefore use SETs as sensors or front-end elements rather than as direct replacements for all CMOS logic.

Nanowire and Carbon-Nanotube Field-Effect Transistors

A nanowire FET uses a semiconductor wire with a diameter sufficiently small for strong electrostatic control and, in some cases, quantum confinement. A gate may surround the wire in a gate-all-around configuration, producing a larger gate-to-channel control ratio than a planar device. Better control reduces short-channel effects such as drain-induced barrier lowering and subthreshold leakage.

Nanowires can be fabricated from silicon, III–V compounds, germanium, and other materials. Their performance depends on carrier mobility, contact resistance, surface states, crystal defects, and diameter uniformity. A wire that is excellent as an isolated research device may be difficult to integrate into a dense wafer-scale process because placement, alignment, source–drain contacting, and thermal management must all be controlled.

Carbon nanotube FETs use semiconducting single-wall carbon nanotubes as channels. Their strong one-dimensional transport and high carrier mobility permit high current density at low channel dimensions. A nanotube’s bandgap depends approximately on its diameter and chirality. Metallic nanotubes, however, can remain after synthesis and must be removed or tolerated; even a small fraction can cause unacceptable leakage or short circuits in a digital circuit. Contact resistance and the difficulty of deterministic placement are additional barriers.

Nanowire and nanotube transistors illustrate an important principle in emerging-device evaluation: excellent intrinsic transport does not automatically produce an excellent integrated technology. The complete technology must include material synthesis, purification, placement, contacting, gate formation, interconnect, thermal processing, and defect-tolerant circuit design.

Two-Dimensional-Material FETs

Two-dimensional (2D) materials consist of atomically thin layers held together in many cases by van der Waals forces. Graphene, molybdenum disulfide, tungsten diselenide, black phosphorus, and related materials have been studied for electronic and optoelectronic devices.

Graphene has high carrier mobility and excellent in-plane conductivity, but pristine graphene has no conventional bandgap. As a result, a graphene FET often exhibits a low ratio of on-current to off-current, which limits its use in conventional digital logic. Graphene remains attractive for high-frequency devices, sensors, transparent conductors, and other applications in which high mobility or broadband response is more important than low leakage.

Semiconducting transition-metal dichalcogenides such as MoS2 possess bandgaps and can form atomically thin channels with good gate control. Their thinness suppresses electrostatic short-channel effects and makes them attractive for flexible electronics, sensors, photodetectors, and low-power switching. Yet contact resistance, defects, environmental sensitivity, mobility variability, and large-area growth remain significant limitations. Black phosphorus offers a thickness-dependent bandgap and anisotropic transport, but environmental degradation requires encapsulation.

Vertical stacking of 2D layers creates van der Waals heterostructures. Because the layers do not require conventional lattice matching, designers can combine materials with different bandgaps and electronic properties. This enables tunneling FETs, photonic devices, memory elements, and multifunctional sensors. The challenge is to translate laboratory-scale stacking and transfer techniques into reproducible, contamination-controlled manufacturing.

Spintronics: Using Spin as an Information Variable

Conventional electronics primarily uses carrier charge. Spintronics exploits the electron’s spin degree of freedom in addition to, or instead of, charge. A ferromagnetic material can act as a spin-polarized source, while a nonmagnetic channel transports spin information. Spin-dependent resistance provides a means of reading magnetic states.

Giant magnetoresistance (GMR) occurs in structures containing alternating ferromagnetic and nonmagnetic layers. The resistance depends on whether the magnetizations are parallel or antiparallel. Tunneling magnetoresistance (TMR) uses a thin insulating barrier between ferromagnetic electrodes. A magnetic tunnel junction (MTJ) commonly has a fixed reference layer, a tunnel barrier, and a free magnetic layer. The relative orientation of the two magnetic layers determines the resistance.

In spin-transfer torque memory, a current transfers angular momentum to the free layer and switches its magnetization. Spin–orbit torque devices use strong spin–orbit interactions and adjacent heavy-metal or topological layers to generate switching torque. STT-MRAM offers nonvolatility, high endurance, and fast access, but switching current, thermal stability, write variability, and integration with CMOS must be carefully managed.

Spintronic devices are particularly attractive for nonvolatile memory, magnetic sensors, oscillators, and unconventional computing. Their energy advantage depends on system conditions. A device may eliminate standby leakage but still require substantial write energy or peripheral circuitry. Therefore, evaluation must include the memory array, sense amplifiers, write drivers, error correction, and thermal environment.

Memristive Devices and Resistive Switching

A memristive device is a two-terminal element whose resistance depends on its history. In practical resistive random-access memory (ReRAM), resistance switching may result from movement of oxygen vacancies, formation and rupture of conductive filaments, interfacial charge trapping, phase change, or other electrochemical mechanisms. Applying a suitable voltage or current changes the device between high-resistance and low-resistance states.

The idealized memristor is often described through a state variable w that evolves according to applied voltage or current, while the conductance depends on w. Real devices are more complex: switching may be abrupt or gradual, unipolar or bipolar, filamentary or interface-dominated, and analog or digital. These distinctions determine endurance, retention, variability, and suitability for computation.

ReRAM is attractive because of compact cell size, nonvolatility, and compatibility with crossbar arrays. A crossbar applies voltages to selected rows and columns to program or read cells. However, sneak-path currents through unselected devices can corrupt read operations. Selector devices, nonlinear switching, bias schemes, and coding methods are used to reduce this problem.

Memristive devices are also important in in-memory and neuromorphic computing. Their conductance can represent a synaptic weight, and the current produced by applying an input voltage can implement an analog multiply–accumulate operation according to Ohm’s and Kirchhoff’s laws. Device nonidealities, including cycle-to-cycle variation, conductance drift, limited resolution, asymmetric potentiation and depression, and device-to-device mismatch, must be incorporated into algorithms and calibration procedures.

Neuromorphic Hardware

Neuromorphic hardware seeks to emulate selected computational principles of biological neural systems, especially event-driven communication, distributed memory, sparse activity, and adaptation. A neuromorphic system generally contains neurons, synapses, communication pathways, local learning or update rules, and event-driven control. It is not necessarily a literal biological replica; it is an architecture designed to reduce the cost of tasks such as pattern recognition, sensory processing, and temporal inference.

In conventional von Neumann computing, data move repeatedly between memory and a processing unit. This movement consumes energy and creates a bandwidth bottleneck. Neuromorphic and in-memory systems place computation near or within the memory array. A crossbar of memristive devices, for example, can perform vector–matrix multiplication in parallel, while CMOS circuits perform nonlinear activation, conversion, and control.

The quality of a neuromorphic implementation depends on more than the nominal precision of a synapse. Relevant metrics include energy per synaptic operation, latency, network throughput, classification accuracy, learning capability, endurance, retention, noise tolerance, and scalability. Analog devices can offer dense and efficient computation but require calibration and tolerate limited precision. Digital implementations generally provide greater reproducibility but may use more area and energy.

Training may occur off-chip, with weights programmed into the hardware, or on-chip through local learning rules. On-chip learning improves adaptability but increases circuit complexity and exposes the system to device variation. Hardware-aware training, stochastic computing, redundancy, and periodic calibration are practical responses to nonideal devices.

A Framework for Evaluating Emerging Devices

A useful evaluation separates device-level merit from technology-level readiness and system-level utility. At the device level, important quantities include switching energy, delay, transconductance, current density, endurance, retention, noise, and operating temperature. At the technology level, one must examine yield, variability, process compatibility, defect density, uniformity, and integration with interconnect and peripheral circuits. At the system level, memory hierarchy, communication energy, software support, algorithms, packaging, and reliability determine the actual benefit.

The following trade-offs recur across emerging devices:

• Energy versus robustness: Lower switching energy can increase susceptibility to thermal noise and variation.
• Density versus accessibility: A dense array may require complex selectors, sensing, or error correction.
• Intrinsic speed versus system speed: Contact, interconnect, and conversion overhead can dominate channel transport.
• Analog efficiency versus precision: Analog computation is compact and parallel, but device drift and mismatch require calibration.
• Novel functionality versus manufacturing maturity: A new physical effect may be valuable but difficult to reproduce at scale.

A practical selection process begins by defining the application constraint. A sensor front end may value charge sensitivity; a cache may value endurance and latency; an edge-AI accelerator may value energy per inference; a quantum device may value coherence and isolation. No emerging device is universally superior.

Applications Across Engineering Practice

Quantum wells and dots are used in lasers, photodetectors, infrared detectors, single-photon sources, and quantum-information research. RTDs support high-frequency oscillators, frequency converters, and special-purpose logic. SETs provide highly sensitive electrometry and charge detection. Nanowire and 2D FETs are candidates for aggressively scaled logic, flexible electronics, chemical sensors, and optoelectronics.

Spintronic devices are used in magnetic-field sensing, hard-disk read heads, MRAM, and emerging oscillators. Memristors are being investigated for nonvolatile memory, programmable analog circuits, hardware security primitives, physical unclonable functions, and neuromorphic accelerators. Neuromorphic systems are particularly promising for event-based vision, speech and acoustic classification, robotics, industrial monitoring, and always-on edge sensing, where sparse temporal data can be processed locally without continuously transferring raw data to the cloud.

Illustrative Case Study: Selecting a Device for an Edge-AI Sensor Node

Background

A fictitious industrial-monitoring company, NexaSense, is designing a battery-powered sensor node for detecting abnormal vibration in motors. The node must operate for several years, process data locally, and transmit only alarms or compact features. The vibration signal is sparse, the classification model is modest in size, and occasional recalibration is acceptable.

Situation and Problem

The engineering team considers three alternatives: a conventional low-power CMOS microcontroller with external memory, a digital accelerator with SRAM, and a memristive crossbar neuromorphic accelerator. The memristive option promises lower energy for matrix operations, but its conductance variation and limited analog precision may reduce classification accuracy.

Analysis

The CMOS solution offers mature tools, predictable behavior, and simple software development. Its disadvantage is repeated movement of sensor data between memory and computation. The digital accelerator reduces this overhead but increases design complexity and may remain inefficient for sparse, event-driven signals. The memristive crossbar can execute weighted summation near the stored weights, potentially reducing data movement. However, the design must include digital-to-analog and analog-to-digital conversion, write verification, drift compensation, and a method for handling defective cells.

The team evaluates not only energy per multiply–accumulate operation but also total energy per classified event, including sensing, conversion, memory programming, calibration, and radio transmission. It tests accuracy under conductance variation, temperature changes, aging, and supply fluctuations. Hardware-aware retraining is used to map neural-network weights to the available conductance states.

Approach and Solution

The selected architecture uses a small CMOS controller for wake-up, diagnostics, and exception handling, together with a modest memristive array for the first-stage feature extraction. A digital classifier performs the final decision. The system periodically recalibrates conductance values and uses redundancy for the most sensitive weights. Raw vibration data are retained only during diagnostic events.

Outcome

In the illustrative evaluation, the hybrid architecture provides a favorable energy–latency trade-off for normal operation, while the CMOS fallback path preserves reliability when the analog array is outside calibration limits. The design does not treat the memristor as a universal processor; it assigns the device only to the computation for which its parallel analog behavior is useful.

Learning Points

The case demonstrates that emerging-device selection is an architectural decision. Device-level energy claims are insufficient unless peripheral circuits, calibration, data movement, reliability, and application accuracy are included. Hybrid systems often provide a more realistic path to deployment than complete replacement of CMOS.

Challenges, Reliability, and Professional Responsibility

The most persistent challenge is variability. At nanoscale dimensions, line-edge roughness, atomic-scale defects, random dopants, trapped charge, and contact fluctuations can alter device behavior. Statistical design, redundancy, adaptive biasing, calibration, and error correction are therefore essential techniques.

Reliability mechanisms include bias-temperature instability, hot-carrier degradation, dielectric breakdown, electromigration, retention loss, resistance drift, magnetic thermal instability, fatigue, and stochastic switching. Emerging devices may also exhibit new failure modes, such as filament overgrowth in ReRAM or loss of magnetic state in an MTJ. Accelerated testing must be interpreted carefully because the physical mechanism under stress may differ from that during normal operation.

Thermal management remains important even when individual devices are low power. Dense arrays, converters, drivers, and interconnects generate local heat. Temperature changes can alter tunneling rates, magnetic stability, ionic mobility, and carrier transport. Packaging must be treated as part of the device technology.

Professional practice requires honest reporting of performance. Researchers and engineers should distinguish isolated-device measurements from array-level results, report statistical distributions rather than only best-case values, identify measurement overhead, and state operating conditions. Environmental and safety implications of nanomaterial synthesis, toxic precursors, waste handling, and end-of-life disposal should also be considered. Security is relevant as well: nonvolatile memories and physically unclonable devices can improve security, but analog variation and side channels may create new vulnerabilities.

Current Directions and Scalability Constraints

Current research is moving toward gate-all-around architectures, vertically stacked devices, monolithic three-dimensional integration, 2D heterostructures, spin–orbit materials, ferroelectric and ionic devices, photonic–electronic co-integration, and brain-inspired accelerators. These directions share an emphasis on reducing interconnect cost and increasing functional density rather than merely shrinking a transistor.

Artificial intelligence is influencing device development in two ways. First, machine-learning models are used for process optimization, defect classification, compact-model extraction, and prediction of device aging. Second, AI workloads motivate specialized hardware based on in-memory computing, sparsity, approximate arithmetic, and event-driven processing. The most promising systems will combine device physics with algorithmic tolerance rather than demand ideal devices.

Scalability should be understood in several dimensions: geometric scaling, wafer-scale manufacturing, yield scaling, economic scaling, design-tool scaling, and application scaling. A device may scale geometrically but fail economically because fabrication is too complex. It may scale in density but fail at the system level because interconnect and heat dominate. It may demonstrate excellent laboratory performance but lack a reliable compact model, process design kit, or test methodology. Consequently, the transition from emerging device to commercial technology is governed as much by integration ecosystems as by physical operation.

Best Practices for Engineering Evaluation

A rigorous evaluation should begin with a clearly defined application and baseline technology. Measurements should include distributions across devices and wafers, not only representative curves. The complete energy budget should include drivers, sensing, conversion, memory access, communication, and cooling where applicable. Models should connect material parameters to circuit and system behavior.

Designers should use technology–application co-optimization. Algorithms can be trained to tolerate noise, quantization, drift, and stuck-at faults. Circuits can provide calibration, redundancy, adaptive sensing, and error correction. Architecture can exploit sparsity, locality, and parallelism. Finally, claims should be tested under realistic temperature, aging, workload, and manufacturing conditions.

Chapter Summary

Quantum and emerging semiconductor devices exploit physical mechanisms that conventional MOSFET theory does not fully capture. Quantum confinement changes energy levels and density of states; tunneling enables resonant transport and negative differential resistance; and Coulomb blockade permits control of individual-electron transfer. Nanowire, nanotube, and 2D-material FETs improve electrostatic control or offer novel transport properties, but contacts, defects, placement, and manufacturing remain difficult.

Spintronic devices use magnetic state and spin-dependent transport for sensing and nonvolatile memory. Memristive devices store information in resistance and can perform in-memory analog computation, although variability, drift, endurance, and sneak currents must be managed. Neuromorphic hardware exploits event-driven operation and local computation to reduce data-movement energy, especially for edge intelligence.

The central engineering lesson is that emerging devices must be evaluated at device, technology, circuit, and system levels. Intrinsic speed or density is insufficient without considering thermal noise, reliability, yield, peripheral overhead, software, packaging, and economic scalability. Hybrid architectures that combine emerging devices with mature CMOS are often the most practical route to useful systems.

Key Terms

Quantum confinement: Modification of carrier energy levels caused by restricting motion to nanoscale dimensions.

Density of states: Number of allowed electronic states per unit energy and volume or area.

Quantum well: Structure confining carriers in one spatial direction.

Quantum wire: Structure confining carriers in two spatial directions.

Quantum dot: Nanostructure confining carriers in all three spatial directions.

Quantum tunneling: Transmission through a classically forbidden potential barrier.

Resonant tunneling: Enhanced tunneling when carrier energy aligns with a quasi-bound state.

Negative differential resistance: Region in which current decreases as applied voltage increases.

Coulomb blockade: Suppression of electron transfer because charging energy exceeds available thermal energy.

Single-electron transistor: Tunnel-junction device controlling transport through an island one electron at a time.

Nanowire FET: Field-effect transistor using a nanoscale wire as its conducting channel.

Two-dimensional material: Atomically thin material with strongly confined thickness and layered properties.

Spintronics: Electronics exploiting electron spin and spin-dependent transport.

Magnetic tunnel junction: Two ferromagnetic layers separated by a thin insulating tunnel barrier.

Memristive device: History-dependent resistive element whose conductance changes with electrical excitation.

Resistive switching: Reversible change between resistance states caused by electrical stimulus.

Neuromorphic hardware: Computing hardware inspired by neural organization and event-driven processing.

Coulomb oscillation: Periodic conductance variation with gate voltage in a single-electron device.

Sneak-path current: Unintended current through unselected paths in an array.

Device variability: Statistical variation in electrical behavior among nominally identical devices.

Review Questions

Short Answer Questions

1. How does reducing a confinement dimension affect the energy spacing of a carrier?

2. What is the physical origin of negative differential resistance in an RTD?

3. Define Coulomb blockade and state the condition required to observe it.

4. Why is graphene less suitable than a semiconducting 2D material for conventional digital switching?

5. What information is represented by the resistance of a magnetic tunnel junction?

Long Answer Questions

1. Explain quantum wells, quantum wires, and quantum dots using density-of-states arguments.

2. Describe the structure, operation, and limitations of a resonant-tunneling diode.

3. Compare a MOSFET and a single-electron transistor in terms of charge control, energy, noise, and scalability.

4. Discuss the operating principles and integration challenges of nanowire and 2D-material FETs.

5. Explain how memristive crossbars support neuromorphic computation and analyze their main nonidealities.

Analytical / Application Questions

1. An SET is to operate at room temperature. What device parameters must be changed to make charging energy dominate thermal energy, and what practical penalties may result?

2. A design team claims that a memristive accelerator is ten times more energy efficient than CMOS based only on array multiply–accumulate energy. Identify the additional quantities required for a fair system comparison.

3. Select an appropriate emerging-device technology for a low-power magnetic-field sensor, an always-on event-based vision system, and a high-endurance nonvolatile memory. Justify each selection using device and system criteria.

22. Multiple Choice Questions with Answers

Question 1

A quantum dot differs from a quantum well primarily because it confines carriers in:

A. No spatial direction

B. One spatial direction

C. Two spatial directions

D. All three spatial directions

Correct Answer: D. All three spatial directions

Question 2

The negative differential resistance of a resonant-tunneling diode occurs when:

A. The device temperature reaches zero

B. Resonant alignment is lost as voltage increases beyond the peak

C. The tunnel barriers become infinitely thick

D. The source and drain are short-circuited

Correct Answer: B. Resonant alignment is lost as voltage increases beyond the peak

Question 3

Coulomb blockade is most readily observed when:

A. Charging energy is much smaller than thermal energy

B. The island capacitance is made very large

C. Charging energy exceeds thermal fluctuations and tunnel resistance is sufficiently high

D. The device has no gate electrode

Correct Answer: C. Charging energy exceeds thermal fluctuations and tunnel resistance is sufficiently high

Question 4

A major integration problem for carbon-nanotube digital circuits is:

A. All nanotubes are necessarily metallic

B. The inability of nanotubes to conduct current

C. The presence of metallic nanotubes and difficulty of deterministic placement

D. The absence of any possible gate control

Correct Answer: C. The presence of metallic nanotubes and difficulty of deterministic placement

Question 5

Why does pristine graphene generally provide poor current on/off ratio for digital logic?

A. It has no conventional bandgap

B. It has excessively high contact resistance in every structure

C. It cannot transport electrons

D. Its thickness is always greater than bulk silicon

Correct Answer: A. It has no conventional bandgap

Question 6

In an MTJ-based memory cell, the resistance is primarily determined by:

A. The relative magnetization orientation of its magnetic layers

B. The optical wavelength incident on the cell

C. The number of source terminals

D. The mechanical length of the package

Correct Answer: A. The relative magnetization orientation of its magnetic layers

Question 7

Which problem is especially associated with resistive crossbar arrays?

A. Coulomb oscillation in every wire

B. Sneak-path currents through unselected devices

C. The absence of any nonvolatile state

D. The impossibility of parallel operation

Correct Answer: B. Sneak-path currents through unselected devices

Question 8

The principal architectural motivation for in-memory computing is to reduce:

A. The bandgap of the semiconductor

B. Data movement between memory and processing units

C. The number of available transistor terminals

D. The need for any form of sensing

Correct Answer: B. Data movement between memory and processing units

Question 9

Which evaluation would provide the fairest comparison between a memristive accelerator and a CMOS accelerator?

A. Comparing only the intrinsic conductance of one device

B. Comparing only the maximum current density

C. Including conversion, calibration, memory access, communication, and accuracy costs

D. Comparing devices at unrelated temperatures and workloads

Correct Answer: C. Including conversion, calibration, memory access, communication, and accuracy costs

Question 10

A major reason emerging devices are often combined with CMOS rather than used alone is that CMOS provides:

A. No variability under any condition

B. Mature control, sensing, logic, and interface circuitry

C. Perfectly zero leakage current

D. Quantum confinement in every channel

Correct Answer: B. Mature control, sensing, logic, and interface circuitry