8. Nanoscale CMOS and Advanced Transistor Architectures

Introduction and Context

The continued progress of integrated electronics has depended heavily on scaling the MOSFET. Reducing transistor dimensions increases packing density, improves switching speed, and can reduce the energy required per operation. Classical constant-field scaling, however, becomes unreliable when the channel length approaches the nanometre range. The electric field is no longer uniformly controlled by the gate, carrier transport ceases to be adequately described by low-field mobility, and leakage currents become comparable with useful signal currents.

Nanoscale CMOS therefore represents more than the fabrication of smaller planar transistors. It involves a coordinated change in device geometry, materials, process technology, circuit design, and reliability engineering. Short-channel effects, velocity saturation, mobility degradation, source–drain tunnelling, gate leakage, random variability, and self-heating impose limits that cannot be solved by dimensional scaling alone. FinFETs, fully depleted silicon-on-insulator devices, gate-all-around nanowire FETs, and nanosheet transistors have consequently replaced or supplemented conventional planar CMOS in advanced technology generations.

This chapter examines the physical origins of nanoscale limitations and explains how advanced architectures restore electrostatic control. It also considers the design–technology trade-offs involved in selecting a transistor structure for high-performance computing, low-power systems, radio-frequency circuits, and emerging heterogeneous platforms.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the principal short-channel effects in nanoscale MOSFETs.

2. Distinguish mobility degradation, velocity saturation, ballistic transport, and quasi-ballistic transport.

3. Analyse subthreshold, gate, junction, and drain-induced leakage mechanisms.

4. Relate device scaling to threshold voltage, variability, power, and reliability.

5. Explain the operating principles and structural advantages of SOI, FinFET, nanowire, and nanosheet FETs.

6. Compare transistor architectures using electrostatic control, drive current, parasitics, manufacturability, and variability.

7. Apply compact physical models and design metrics to technology-selection problems.

8. Identify current challenges and emerging directions in nanoscale CMOS.

From Planar Scaling to Electrostatic Design

For a long-channel MOSFET in saturation, the square-law model gives

\[

I_D \approx \frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T)^2,

\]

where \(\mu_n\) is carrier mobility, \(C_{ox}\) is oxide capacitance per unit area, \(W\) and \(L\) are channel width and length, and \(V_T\) is threshold voltage. This model is valuable for introducing MOS operation, but its assumptions become weak at nanoscale dimensions. The channel is not uniformly inverted, the lateral electric field is high, carrier velocity approaches a limiting value, and the source and drain fields penetrate deeply into the channel.

A useful measure of electrostatic integrity is the characteristic length, often represented approximately for a planar device by

\[

\lambda \propto \sqrt{\frac{\varepsilon_{si}}{\varepsilon_{ox}}t_{si}t_{ox}},

\]

where \(t_{si}\) is the silicon body thickness and \(t_{ox}\) is the effective oxide thickness. Good gate control requires the channel length to be several times larger than this characteristic length. Multigate structures reduce the effective electrostatic length because the gate surrounds a larger fraction of the channel perimeter.

The traditional scaling objective was constant electric field: dimensions and supply voltage were reduced together so that fields remained approximately unchanged. In practice, supply voltage has not fallen as rapidly as dimensions, partly because adequate circuit speed requires sufficient overdrive. This creates a power-density problem. Dynamic power is approximately

\[

P_{dyn}=\alpha C_L V_{DD}^{2}f,

\]

while static power is associated mainly with leakage. At advanced nodes, reducing dynamic power by lowering voltage can increase delay and reduce noise margins; reducing threshold voltage to recover speed increases off-state current. The technology problem is therefore a constrained optimization rather than simple geometric shrinkage.

Short-Channel Effects and Their Physical Interpretation

Threshold-voltage roll-off

In a long-channel MOSFET, the gate primarily determines the surface potential. As the channel becomes shorter, depletion regions from the source and drain occupy a greater proportion of the channel. Their charges assist the gate in controlling the barrier, so the threshold voltage decreases with decreasing channel length. This is called threshold-voltage roll-off.

Roll-off causes transistors with different channel lengths to exhibit different switching points. It also increases off-state current. Halo implants and pocket implants can suppress roll-off, but they increase impurity scattering, junction capacitance, and process sensitivity.

Drain-induced barrier lowering

Drain-induced barrier lowering (DIBL) occurs when an increased drain voltage lowers the source-channel energy barrier. The drain consequently gains partial control over the channel current even when the gate voltage is below threshold. DIBL is measured through the change in threshold voltage with drain voltage:

\[

DIBL \approx -\frac{\Delta V_T}{\Delta V_D}.

\]

A high DIBL produces poor output resistance, increased off-state current, and a threshold voltage that depends strongly on circuit bias. Multigate architectures reduce DIBL by placing the channel closer to controlling gate surfaces.

Subthreshold-slope degradation

Below threshold, drain current varies approximately exponentially with gate voltage:

\[

I_D \propto \exp\left(\frac{V_{GS}-V_T}{nV_T^{*}}\right),

\]

where \(V_T^{*}=kT/q\) is the thermal voltage and \(n\) is a body-factor-related coefficient. The subthreshold swing is

\[

S=(\ln 10)n\frac{kT}{q}.

\]

At room temperature, an ideal conventional MOSFET has a lower limit near 60 mV per decade. Real devices have larger values because of depletion capacitance, interface traps, and imperfect electrostatics. A poor subthreshold swing means that a large reduction in gate voltage is required to suppress leakage.

Channel-length modulation and output conductance

In saturation, the drain depletion region extends into the channel as drain voltage increases. The effective channel length decreases, causing drain current to rise with drain voltage. At nanoscale dimensions this effect is intensified, lowering intrinsic gain:

\[

A_v \approx g_m r_o.

\]

Although digital logic mainly requires switching speed and noise margins, analogue circuits depend strongly on output resistance and intrinsic gain. This is one reason why advanced digital process technologies do not automatically provide superior analogue performance.

Punch-through and breakdown

When source and drain depletion regions approach one another, the gate loses effective control of the intervening barrier. Punch-through can produce substantial current even without strong inversion. High drain fields may also cause impact ionization, hot-carrier degradation, and avalanche breakdown. Short-channel engineering uses shallow junctions, graded dopant profiles, low-field extensions, and improved gate control to limit these effects.

High-Field Transport: Mobility, Velocity, and Ballisticity

Carrier mobility is not constant in a nanoscale transistor. A vertical electric field attracts carriers toward the oxide interface, where surface roughness and interface defects increase scattering. The effective mobility therefore decreases as gate field increases. Phonon scattering, Coulomb scattering from charged impurities, and remote scattering from high-k dielectrics also influence transport.

At high lateral electric field, carrier velocity no longer increases linearly with field. It approaches a saturation velocity, so the current is better approximated by

\[

I_{D,sat}\approx W Q_{inv}v_{sat},

\]

rather than by the long-channel square-law expression. Velocity saturation reduces the benefit of further channel-length reduction: current may scale approximately with width rather than with \(1/L\). The transconductance also becomes less dependent on overdrive than predicted by the square-law model.

When the channel length becomes comparable with the mean free path, carriers can cross part of the channel without scattering. Such transport is called quasi-ballistic; completely ballistic transport is an ideal limiting case. Ballisticity can improve injection velocity, but the current is still limited by source injection, contact resistance, phonon scattering, and quantum confinement. It does not mean that resistance or power dissipation disappears.

A nanoscale transistor must consequently be evaluated using injection velocity, contact resistance, effective mobility, quantum capacitance, and parasitic capacitance, not mobility alone. Source and drain resistance can consume a significant fraction of the applied voltage and reduce both drive current and transconductance.

Leakage Mechanisms and Power Consequences

Leakage in nanoscale CMOS has several physically distinct components.

Subthreshold leakage is diffusion current through a channel whose gate voltage is below threshold. It increases exponentially with reduced threshold voltage, increased temperature, and DIBL.

Gate leakage results from direct tunnelling through an ultrathin dielectric. High-k dielectrics permit a physically thicker film for a similar electrical oxide thickness, reducing direct tunnelling while preserving gate capacitance. Metal gates avoid the depletion and work-function limitations of heavily doped polysilicon.

Junction leakage arises from reverse-biased source and drain junctions through diffusion, generation–recombination, and band-to-band tunnelling. Aggressive doping and high electric fields can increase band-to-band tunnelling.

Gate-induced drain leakage occurs near the drain surface under high electric field, especially when the gate and drain overlap strongly. It can be significant in the off state.

Source–drain tunnelling becomes relevant when the barrier is extremely short or thin. Conventional silicon MOSFET scaling is generally limited before this mechanism dominates, but it is important in very short channels and alternative-material research.

Leakage increases standby power and may cause thermal runaway. In memory arrays, leakage can also disturb stored information. Designers use power gating, body bias, multi-threshold libraries, transistor stacking, state retention, and adaptive voltage control. These circuit techniques reduce system-level leakage but cannot substitute for good device electrostatics.

Variability, Reliability, and Statistical Design

At large dimensions, random fluctuations are averaged over many dopant atoms and interface features. At nanoscale dimensions, a small number of discrete dopants, line-edge variations, fin-width variations, work-function fluctuations, and oxide-thickness variations can cause appreciable changes in threshold voltage and drive current.

Random dopant fluctuation is particularly important in heavily doped planar channels. Fully depleted and undoped-body devices reduce this source of variation, although they introduce sensitivity to work-function variation and geometric fluctuations. FinFET width quantization also produces discrete changes in effective width because transistor width is determined by the number and dimensions of fins.

Variability affects timing yield, SRAM stability, analogue offset, leakage distribution, and power. Mean-value design is insufficient; statistical corner analysis and Monte Carlo simulation are required. At advanced nodes, local mismatch, systematic process gradients, layout-dependent effects, and ageing must be considered together.

Important reliability mechanisms include bias-temperature instability, hot-carrier injection, time-dependent dielectric breakdown, electromigration, self-heating, and stress-induced leakage current. Three-dimensional devices may have improved electrostatic control but poorer thermal paths, particularly when an insulating buried layer separates the active device from the substrate.

SOI Devices and the Body-Control Problem

Silicon-on-insulator technology places a thin silicon layer on an insulating buried oxide. In fully depleted SOI, the silicon body is thin enough that the depletion region extends through it. The architecture reduces junction capacitance, improves isolation, and can provide excellent switching energy and speed. It is attractive for low-power digital circuits, radio-frequency systems, and applications requiring reduced substrate coupling.

Partially depleted SOI retains a neutral body region. The body potential can become history-dependent, producing the floating-body effect. Impact ionization can charge the body and alter threshold voltage, causing transient anomalies and kink effects in output characteristics. Body contacts or circuit techniques are used to control this behaviour.

SOI also introduces self-heating because the buried oxide has low thermal conductivity. Temperature rise reduces mobility, increases leakage, and accelerates ageing. Thus SOI illustrates a general principle: an architecture may improve electrical isolation while worsening thermal management.

FinFETs: Three-Dimensional Gate Control

A FinFET forms the channel in a thin vertical fin. The gate controls two or three sides of the fin, depending on the structure. The effective width is approximately related to fin height and fin thickness; in a double-sided device, a useful first-order estimate is

\[

W_{eff}\approx 2H_{fin}+T_{fin}.

\]

The thin fin reduces the distance over which source and drain fields can influence the channel. Consequently, FinFETs exhibit lower DIBL, improved subthreshold swing, and reduced threshold roll-off compared with comparable planar devices.

FinFET width is quantized by the number of fins. A designer cannot select every arbitrary transistor width, which affects standard-cell architecture, analogue sizing, and leakage optimization. Fin height and fin pitch are constrained by lithography, etch uniformity, mechanical stability, and parasitic capacitance. Gate resistance, source–drain resistance, and interconnect capacitance become increasingly important as intrinsic transistor speed improves.

FinFETs are well suited to mainstream high-performance and low-power CMOS because they provide a strong balance among electrostatics, drive current, manufacturability, and ecosystem maturity. Their limitations become more pronounced when further scaling requires even stronger gate control or when flexible width adjustment is important.

Gate-All-Around, Nanowire, and Nanosheet FETs

A gate-all-around (GAA) FET surrounds the channel on every side. This geometry maximizes gate-to-channel control and minimizes drain-field penetration. Nanowire GAA devices use narrow cylindrical or rectangular channels, whereas nanosheet devices use wider horizontal sheets separated vertically by dielectric spacers.

Nanowires offer excellent electrostatics and can support very small channel dimensions, but their cross-sectional area limits drive current and their fabrication and contact formation are demanding. Nanosheets provide a compromise: they retain GAA control while offering greater effective width per stacked channel. Several sheets can be vertically stacked, increasing current within a compact footprint.

The architecture also permits greater width flexibility than a single FinFET, since sheet width can be engineered. However, inner spacers, gate formation, sheet release, source–drain epitaxy, contact resistance, and thermal transport create significant process challenges. Parasitic capacitance may increase because of three-dimensional gate and contact structures.

Beyond silicon, devices such as nanowire FETs, two-dimensional-material FETs, complementary FETs, and vertically stacked transistors are being investigated. Their value depends not only on channel transport but also on defect density, contact resistance, manufacturability, variability, and integration with existing design rules.

Comparing Architectures Through Design Metrics

Architecture selection should begin with the application rather than with the smallest nominal dimension. The following metrics are central:

• Electrostatic control: subthreshold swing, DIBL, threshold roll-off, and gate control.
• Performance: drive current, transconductance, intrinsic delay, and contact resistance.
• Power: dynamic capacitance, leakage, operating voltage, and thermal resistance.
• Area efficiency: footprint, pitch, fin or sheet count, and standard-cell height.
• Analogue suitability: intrinsic gain, matching, noise, output resistance, and body control.
• Manufacturability: process complexity, defect sensitivity, yield, and design-rule maturity.
• Reliability: self-heating, dielectric stress, bias-temperature instability, and electromigration.

A FinFET may be preferable for a high-volume digital processor because its process and cell libraries are mature. A GAA nanosheet may be selected when electrostatic margin and drive current at reduced voltage are more important than process simplicity. SOI may be advantageous for RF isolation or low junction capacitance, while bulk CMOS can remain attractive where cost and broad device-option availability dominate.

Design and Technology Co-Optimization

Device technology and circuit architecture cannot be optimized independently. A transistor with high drive current may also have larger capacitance and leakage. A narrow fin improves electrostatic control but reduces current per device. Lower threshold voltage improves speed but raises standby power. Higher-k dielectrics increase capacitance and may introduce remote phonon scattering or reliability concerns.

At the circuit level, designers use multi-threshold devices, power domains, clock gating, operand isolation, body bias where available, and near-threshold operation. At the physical-design level, placement, orientation, fin count, contact arrangement, and local interconnect determine effective performance. Standard-cell height and routing congestion may dominate system-level benefit even when transistor-level metrics improve.

Electronic-design-automation tools increasingly use statistical timing, parasitic extraction, machine-learning-assisted layout exploration, and reliability-aware optimization. Such tools are useful only when their models capture layout dependence, temperature, variability, and ageing. Artificial intelligence can accelerate design-space exploration, but it does not remove the need for physical understanding and experimentally validated compact models.

Illustrative Case Study: Selecting an Architecture for a Low-Power Edge Processor

Background

Consider a fictional semiconductor company developing a battery-powered edge-vision processor. The chip must perform sustained inference at low supply voltage, occupy a small die area, and tolerate substantial manufacturing variation. It will be produced in a high-volume digital process with embedded memory and limited design time.

Situation and Problem

A planar bulk CMOS option offers low process cost but exhibits high DIBL and subthreshold leakage at the required channel length. A mature FinFET option provides better electrostatic control, while an emerging GAA nanosheet option offers higher drive current at reduced voltage but has greater process complexity and uncertain library maturity.

Analysis

The processor spends long periods in standby and intermittent periods in intensive computation. Consequently, both leakage and dynamic energy matter. The planar option would require a higher threshold voltage or aggressive power gating, reducing wake-up performance and increasing circuit complexity. FinFETs provide lower leakage and a mature standard-cell ecosystem. Their quantized width is a disadvantage for analogue sensor interfaces, but most computation is digital. GAA nanosheets could improve performance per unit area, yet the project schedule and verification effort make their process risk significant.

Approach and Solution

The company selects FinFET technology, uses high-threshold devices in retention and always-on blocks, and reserves low-threshold devices for critical arithmetic paths. Power domains are shut down during inactivity. Standard cells are characterized across process, voltage, temperature, and mismatch corners. SRAM assist circuits are evaluated with statistical variation because low-voltage operation reduces read and write margins.

Outcome

The selected architecture meets the energy target without relying on immature process features. The design gives up some peak performance relative to the projected nanosheet option but gains predictable yield, established models, and shorter development time.

Learning Points

The case demonstrates that the smallest or newest transistor is not automatically the best engineering choice. Architecture must be judged against workload, leakage duty cycle, voltage range, library maturity, thermal limits, yield, and schedule. Technology selection is a system-level decision.

Challenges, Limitations, and Common Engineering Mistakes

A common mistake is to use the long-channel square-law model to predict nanoscale current or delay without calibration. Another is to treat the process node label as a complete description of transistor capability; nominal node names do not uniquely specify channel length, contacted pitch, density, or performance.

Designers may also ignore contact and interconnect resistance, assume that lower supply voltage always reduces total power, or evaluate leakage only at room temperature. Three-dimensional devices can conceal thermal bottlenecks, and improved gate control does not guarantee improved analogue gain. Excessive reliance on typical-case simulation can produce unacceptable yield loss when variation is large.

Experimental characterization must therefore include temperature dependence, statistical distributions, layout effects, ageing, and transient operation. Compact models should be validated against silicon or physically credible simulation, and design margins should reflect application consequences rather than arbitrary conventional corners.

Professional and Ethical Considerations

Advanced semiconductor engineering has professional consequences beyond transistor performance. Process decisions affect energy consumption throughout product life, material use, manufacturing waste, and electronic waste. Reliability claims must be supported by appropriate qualification rather than optimistic nominal simulation. Engineers should report uncertainty in models, distinguish measured data from projections, and avoid presenting unverified emerging architectures as production-ready.

Security is also relevant. Process variation and device ageing can influence hardware fingerprints, side channels, fault behaviour, and physical unclonable functions. Secure design requires awareness of both intentional and unintentional variability. Supply-chain governance, export controls, intellectual-property protection, and responsible handling of process data are additional organizational concerns in advanced semiconductor development.

Current Developments and Emerging Directions

The current direction of CMOS scaling combines improved electrostatics with backside power delivery, advanced interconnects, high-k/metal-gate refinement, and three-dimensional integration. Gate-all-around nanosheets are being developed for stronger control and greater width flexibility. Complementary FET concepts stack n-channel and p-channel devices vertically to reduce footprint. Backside power networks aim to separate power delivery from signal routing and reduce front-side congestion.

Further progress is constrained by interconnect delay, thermal density, contact resistance, variability, and economic complexity. Two-dimensional semiconductors and alternative channel materials may offer excellent electrostatic scaling, but contacts, defects, wafer-scale integration, and reliability remain difficult. In many systems, architectural specialization, chiplets, three-dimensional integration, and workload-aware voltage management may provide greater practical benefit than transistor scaling alone.

Best-Practice Framework for Nanoscale Device Evaluation

A disciplined evaluation should proceed through the following questions:

1. Is electrostatic control adequate at the intended channel length and supply voltage?

2. What are the dominant transport and resistance limits: mobility, velocity saturation, ballistic injection, or contacts?

3. Which leakage mechanisms determine standby power at the operating temperature?

4. How do process, local mismatch, layout, and ageing affect yield?

5. Are parasitic capacitance and thermal resistance included in system-level estimates?

6. Does the architecture support the required analogue, memory, RF, and digital functions?

7. Is the process sufficiently mature for the required volume, reliability, and schedule?

8. Have performance, power, area, cost, and risk been optimized jointly rather than separately?

Chapter Summary

Nanoscale CMOS is governed by electrostatic control, nonclassical carrier transport, leakage, variability, and reliability rather than by geometric scaling alone. Short-channel effects such as threshold roll-off, DIBL, punch-through, and subthreshold-slope degradation arise because source and drain fields increasingly influence the channel. High lateral fields cause velocity saturation, while short channels produce quasi-ballistic transport and make contact resistance important.

Leakage includes subthreshold, gate, junction, gate-induced drain, and tunnelling components. Lower threshold voltage improves speed but increases standby power, making power management and device architecture inseparable. SOI reduces junction capacitance and substrate coupling but may suffer from floating-body effects and self-heating. FinFETs improve electrostatic control through multigate geometry, while GAA nanowire and nanosheet FETs surround the channel and provide still stronger control with greater process complexity.

Architecture selection requires joint consideration of performance, power, area, variability, analogue behaviour, thermal management, manufacturability, reliability, and design ecosystem. The central professional lesson is that technology optimization is application-dependent: the most advanced device is valuable only when its benefits outweigh its process, modelling, thermal, and economic risks.

Key Terms

Short-channel effect: Deviation from long-channel MOSFET behaviour caused by reduced channel length.

Threshold-voltage roll-off: Reduction of threshold voltage as channel length decreases.

Drain-induced barrier lowering: Reduction of the source-channel barrier caused by drain voltage.

Subthreshold swing: Gate-voltage change required to change subthreshold current by one decade.

Velocity saturation: Limitation of carrier velocity at high lateral electric field.

Ballistic transport: Carrier transport with negligible scattering over the relevant channel distance.

Quasi-ballistic transport: Transport in which carriers experience limited scattering during channel transit.

DIBL: Drain-induced barrier lowering, commonly measured as threshold change per drain-voltage change.

Gate leakage: Current tunnelling through the gate dielectric.

Junction leakage: Reverse-biased source or drain leakage through semiconductor junction mechanisms.

SOI: Silicon-on-insulator technology using a buried insulating layer beneath the active silicon.

Fully depleted SOI: SOI in which the thin silicon body is depleted throughout operation.

FinFET: Multigate transistor using a vertical fin as the channel body.

Gate-all-around FET: Transistor whose gate surrounds the channel on all sides.

Nanowire FET: GAA transistor using a narrow wire-like channel.

Nanosheet FET: GAA transistor using a wider horizontal sheet channel, often vertically stacked.

Characteristic length: Electrostatic length scale describing gate control relative to source and drain fields.

Random variability: Statistical device variation caused by discrete atoms, geometry, interfaces, and work-function fluctuations.

Self-heating: Device temperature rise caused by internally generated power and limited heat removal.

Design–technology co-optimization: Joint optimization of process, device, circuit, layout, and system decisions.

Review Questions

Short Answer Questions

1. What physical mechanism causes DIBL, and how does it affect off-state current?

2. Why does velocity saturation weaken the benefit of reducing channel length?

3. Distinguish subthreshold leakage from gate leakage.

4. State two electrical advantages and one thermal limitation of SOI technology.

5. Why is transistor width quantized in a conventional FinFET design?

Long Answer Questions

1. Explain the major short-channel effects in a planar MOSFET and show how multigate structures mitigate them.

2. Discuss mobility degradation, velocity saturation, quasi-ballistic transport, and contact resistance as successive nanoscale transport considerations.

3. Compare planar bulk CMOS, SOI, FinFET, and GAA nanosheet FETs in terms of electrostatics, power, variability, thermal behaviour, and manufacturability.

4. Explain the principal leakage mechanisms in nanoscale CMOS and describe circuit and technology methods for controlling leakage power.

5. Discuss why device scaling requires design–technology co-optimization rather than independent transistor and circuit development.

Analytical / Application Questions

1. A transistor shows a threshold-voltage reduction of 80 mV when drain voltage increases by 0.8 V. Calculate its approximate DIBL and explain the likely circuit consequence.

2. An edge processor operates mostly in standby but requires short bursts of high performance. Choose between a mature FinFET process and a higher-drive but immature GAA process, and justify the choice using at least five engineering criteria.

3. A proposed SOI circuit meets its room-temperature speed target but fails at elevated temperature. Analyse the likely role of self-heating, mobility reduction, leakage, and reliability, and propose design remedies.

22. Multiple Choice Questions with Answers

Question 1

Which effect most directly describes the lowering of the source-channel barrier by an increasing drain voltage?

A. Velocity saturation

B. Drain-induced barrier lowering

C. Channel-length modulation

D. Gate-induced drain leakage

Correct Answer: B. Drain-induced barrier lowering

Question 2

Why does velocity saturation reduce the improvement obtained by shortening a nanoscale MOSFET channel?

A. Carrier velocity becomes limited at high lateral field

B. Gate oxide capacitance becomes zero

C. The source and drain become electrically isolated

D. Threshold voltage becomes independent of geometry

Correct Answer: A. Carrier velocity becomes limited at high lateral field

Question 3

Which leakage mechanism is most directly reduced by replacing an ultrathin conventional oxide with a physically thicker high-k dielectric of similar electrical thickness?

A. Junction leakage

B. Subthreshold leakage

C. Direct gate tunnelling

D. Punch-through

Correct Answer: C. Direct gate tunnelling

Question 4

The principal electrostatic advantage of a FinFET over a comparable planar MOSFET is that the gate

A. eliminates all parasitic capacitance

B. controls the channel from multiple surfaces

C. prevents velocity saturation

D. removes contact resistance

Correct Answer: B. controls the channel from multiple surfaces

Question 5

A fully depleted SOI device may experience significant self-heating mainly because

A. the buried oxide impedes heat flow to the substrate

B. the channel is always in avalanche breakdown

C. the gate dielectric is metallic

D. the source and drain are not doped

Correct Answer: A. the buried oxide impedes heat flow to the substrate

Question 6

Which architecture provides the strongest geometric gate control by surrounding the channel on all sides?

A. Planar bulk MOSFET

B. Partially depleted SOI MOSFET

C. Gate-all-around FET

D. Single-gate thin-film transistor

Correct Answer: C. Gate-all-around FET

Question 7

Why can nanoscale variability be large even when average device dimensions are accurately controlled?

A. A small number of dopants and interfaces can significantly affect device behaviour

B. Thermal voltage becomes exactly zero

C. All transistors become perfectly ballistic

D. Interconnects no longer contribute capacitance

Correct Answer: A. A small number of dopants and interfaces can significantly affect device behaviour

Question 8

For a digital processor that spends most of its time in standby, which trade-off is especially important?

A. Peak transconductance versus oxide colour

B. Threshold voltage, leakage power, and wake-up performance

C. Fin height versus package logo

D. Substrate doping versus instruction-set syntax

Correct Answer: B. Threshold voltage, leakage power, and wake-up performance

Question 9

A GAA nanosheet transistor can offer greater width flexibility than a conventional FinFET primarily because

A. sheet width can be engineered more continuously than fin count

B. it has no source or drain

C. it operates without a gate dielectric

D. it eliminates quantum confinement

Correct Answer: A. sheet width can be engineered more continuously than fin count

Question 10

Which statement best expresses design–technology co-optimization?

A. Selecting the smallest transistor without considering circuits

B. Optimizing process, device, layout, circuit, and system metrics jointly

C. Ignoring thermal behaviour until packaging

D. Using only typical-case simulations

Correct Answer: B. Optimizing process, device, layout, circuit, and system metrics jointly