7. MOSFET Operation and Compact Modeling

Introduction and Context

The metal–oxide–semiconductor field-effect transistor (MOSFET) is the dominant active device in modern integrated electronics. Its importance arises from the ability to control channel conductivity through an electric field, while requiring essentially no steady-state gate current. This property supports high packing density, low static power, and compatibility with large-scale silicon manufacturing. MOSFET operation underlies digital logic, analog amplifiers, memory, power management, sensors, and mixed-signal systems.

An idealized long-channel MOSFET provides a useful bridge between semiconductor physics and circuit design. Starting from charge control, one can derive the drain current, identify the cutoff, triode, and saturation regions, and obtain important quantities such as transconductance and output conductance. Real devices, however, depart from this ideal description because of body effect, channel-length modulation, velocity saturation, mobility degradation, parasitic capacitances, leakage, noise, and process variation. Compact models incorporate these effects in a form suitable for circuit simulators such as SPICE.

This chapter develops the physical and mathematical foundations of MOSFET operation and then connects them with small-signal analysis, high-frequency behavior, noise, compact modeling, and parameter extraction.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain MOS capacitor inversion and the physical operation of an n-channel MOSFET.

2. Derive the long-channel drain-current equations in cutoff, triode, and saturation.

3. Interpret threshold voltage, body effect, channel-length modulation, and mobility degradation.

4. Determine transconductance, output conductance, voltage gain, and relevant capacitances.

5. Explain MOSFET noise mechanisms and their effect on circuit performance.

6. Distinguish physical device equations from SPICE compact-model representations.

7. Extract key MOSFET parameters from measured current–voltage and capacitance data.

8. Recognize modeling limitations, scaling effects, and emerging directions in MOSFET technology.

From MOS Capacitor to MOSFET

Consider an n-channel MOS structure consisting of a metal gate, oxide layer, p-type silicon body, and two n+ regions serving as source and drain. With the gate at a sufficiently negative voltage, holes accumulate near the silicon–oxide interface. As the gate voltage becomes positive, holes are repelled and a depletion region forms. At a still higher voltage, electrons are attracted to the interface in sufficient concentration to create an inversion layer. This electron sheet connects the source and drain when the device is fabricated with suitable n+ contacts.

The gate voltage at which strong inversion is conventionally said to occur is the threshold voltage, denoted by V_T. In a simplified form, the threshold voltage of an nMOS transistor with source and body at the same potential is

V_T0 = V_FB + 2φ_F + γ√(2φ_F),

where V_FB is the flat-band voltage, φ_F is the Fermi potential, and γ is the body-effect coefficient. The exact expression depends on substrate doping, oxide capacitance, fixed charge, and interface states.

When a drain-to-source voltage V_DS is applied, electrons flow from source to drain through the inversion layer. Conventional current flows from drain to source. The gate controls the inversion charge, whereas the drain voltage establishes a lateral electric field that causes carrier transport along the channel.

Long-Channel Charge-Control Model

For an nMOS transistor, define V_GS as the gate-to-source voltage and V_DS as the drain-to-source voltage. The overdrive voltage is

V_OV = V_GS − V_T.

A channel exists only when V_OV > 0. Under the gradual-channel approximation, the inversion charge per unit area at a position x along the channel is approximately

Q_i(x) = −C_ox [V_GS − V_T − V(x)],

where C_ox = ε_ox/t_ox is the oxide capacitance per unit area and V(x) is the local channel potential relative to the source. The negative sign represents electron charge.

Assuming constant mobility μ_n and channel width W, the drain current is obtained by integrating the drift current along a channel of length L:

I_D = μ_n C_ox (W/L) [(V_GS − V_T)V_DS − V_DS²/2].

This expression applies while the channel exists throughout its length. The current is therefore a quadratic function of V_DS in the triode or linear region.

Cutoff Region

If V_GS ≤ V_T, the ideal long-channel model predicts that the inversion channel is absent and

I_D ≈ 0.

In practical devices, a weak-inversion or subthreshold current remains. For V_GS below threshold, a useful approximation is

I_D = I_0 exp[(V_GS − V_T)/(nU_T)] [1 − exp(−V_DS/U_T)],

where U_T = kT/q is the thermal voltage and n is the subthreshold slope factor. Subthreshold operation is particularly important in ultra-low-power circuits, although leakage becomes a major limitation in scaled technologies.

Triode or Linear Region

When 0 < V_DS < V_GS − V_T, the channel exists from source to drain. The current is

I_D = μ_n C_ox (W/L) [(V_GS − V_T)V_DS − V_DS²/2].

For very small V_DS, the transistor behaves approximately as a voltage-controlled resistor:

R_ON ≈ 1/[μ_n C_ox(W/L)(V_GS − V_T)].

This region is used in transmission gates, analog switches, variable resistors, and sampled-data circuits.

Saturation Region

As V_DS increases, the inversion charge at the drain end decreases. Pinch-off begins when

V_DS = V_GS − V_T = V_OV.

For V_DS ≥ V_OV, the ideal long-channel current becomes

I_D = (1/2) μ_n C_ox (W/L)(V_GS − V_T)².

The drain current is ideally independent of V_DS in saturation. Physically, pinch-off does not mean that current stops at the drain end. Carriers reaching the pinch-off region are swept through it by the electric field and continue into the drain.

The quantity β = μ_nC_ox(W/L) is often called the process-transistor gain factor. Thus, in saturation, I_D = βV_OV²/2. The boundary between triode and saturation is not a separate operating state; it is the condition V_DS = V_OV.

Body Effect and Threshold Modulation

The body or bulk terminal influences threshold voltage whenever the source and body are not at the same potential. For an nMOS transistor with reverse body bias V_SB ≥ 0,

V_T = V_T0 + γ[√(2φ_F + V_SB) − √(2φ_F)].

Increasing V_SB widens the depletion region and requires a larger gate voltage to produce strong inversion. This phenomenon is called the body effect.

Body effect is important in source followers, stacked transistors, analog switches, and circuits in which the source voltage changes dynamically. It reduces the voltage gain of some common-drain stages and introduces a body transconductance. A small change in source-to-body voltage produces

g_mb = ∂I_D/∂V_SB.

For a saturated long-channel device,

g_m = μ_nC_ox(W/L)V_OV = 2I_D/V_OV,

and, approximately,

g_mb = ηg_m,

where η is commonly between a fraction of unity and a value dependent on substrate bias and process parameters.

Nonidealities in Practical MOSFETs

Channel-Length Modulation

In saturation, increasing V_DS extends the depletion region around the drain and shortens the effective channel length. Consequently, current increases slightly with V_DS. A first-order model is

I_D = (1/2)βV_OV²(1 + λV_DS),

where λ is the channel-length modulation coefficient. The output conductance is

g_o = ∂I_D/∂V_DS ≈ λI_D,

and the intrinsic output resistance is r_o = 1/g_o. The finite output resistance limits the gain of common-source amplifiers.

Mobility Degradation

A strong vertical electric field at the oxide interface increases surface scattering and reduces effective mobility. A commonly used empirical representation is

μ_eff = μ_0/[1 + θV_OV],

where θ is a mobility-degradation parameter. This causes the drain current to grow more slowly than the ideal square-law expression at high overdrive.

Velocity Saturation

In short-channel devices, carrier velocity no longer increases linearly with electric field. It approaches a saturation velocity v_sat. The square-law relation then becomes inaccurate, and the saturation current may become approximately proportional to V_OV rather than V_OV². This changes the dependence of transconductance on current and is one reason that long-channel formulas should not be used uncritically for modern nanoscale transistors.

Drain-Induced Barrier Lowering

A large drain voltage can lower the source-channel barrier, increasing current even when V_GS is fixed. This effect, called drain-induced barrier lowering (DIBL), reduces the apparent threshold voltage as V_DS increases. DIBL is a major short-channel effect and contributes to off-state leakage.

Subthreshold Slope and Leakage

The subthreshold slope indicates how much gate voltage is required for a tenfold change in current. At room temperature, the ideal limit is approximately 60 mV per decade, while real devices have larger values because of depletion capacitance and interface effects. Leakage also includes gate tunneling, junction leakage, and gate-induced drain leakage.

Small-Signal MOSFET Behavior

Small-signal parameters describe incremental changes about a chosen bias point. For a saturated transistor with channel-length modulation,

I_D ≈ (1/2)βV_OV²(1 + λV_DS).

The transconductance is

g_m = ∂I_D/∂V_GS ≈ βV_OV = 2I_D/V_OV,

with corrections when mobility degradation or velocity saturation is included. The output conductance is g_o ≈ λI_D, and body transconductance g_mb accounts for threshold modulation by the body.

The intrinsic voltage gain of a common-source transistor is approximately

A_v ≈ −g_mr_o

when loading and source degeneration are neglected. A useful design measure is g_m/I_D, which is high in weak inversion, moderate in moderate inversion, and lower in strong inversion. The gm/ID method is widely used for analog design because it connects current efficiency with inversion level rather than relying exclusively on square-law equations.

The small-signal hybrid-pi representation includes controlled current g_mv_gs, output resistance r_o, body-controlled current g_mbv_bs, and terminal capacitances. For high-frequency analysis, the most important capacitances are C_gs, C_gd, C_db, and C_sb. In saturation, the channel charge is redistributed mainly between the source and gate, while the gate–drain capacitance is reduced in the ideal intrinsic model but remains affected by overlap and fringing fields.

The Miller effect multiplies the effective input contribution of C_gd in an inverting amplifier. This can substantially reduce bandwidth. Cascode structures reduce the voltage variation across the drain of the input transistor and therefore reduce Miller multiplication.

MOSFET Capacitances and Switching

MOSFET capacitances have both intrinsic and extrinsic components. Intrinsic capacitances arise from the inversion channel and depletion regions. Extrinsic capacitances include gate-source and gate-drain overlap, junction capacitances, interconnect capacitance, and package parasitics.

The drain and source junction capacitances are voltage dependent because the depletion widths vary with reverse bias. A common empirical form is

C_j(V) = C_{j0}(1 + V/φ_j)^{-m},

where C_{j0} is the zero-bias capacitance, φ_j is the junction potential, and m is a grading coefficient.

For digital switching, the gate charge Q_G is often more useful than a single capacitance value. It is divided into charging associated with C_GS, the Miller plateau associated with C_GD, and final gate-voltage rise. Switching loss, driver requirements, propagation delay, and electromagnetic behavior depend on this charge and on the applied gate-drive waveform.

Noise Mechanisms

Thermal channel noise results from random carrier motion. A common saturation-region model expresses the drain-current noise spectral density as

S_id = 4kTγ_n g_m,

where γ_n is a model-dependent coefficient. For an ideal long-channel device, γ_n is often approximated by 2/3; practical short-channel values can differ substantially.

Flicker noise, or 1/f noise, is associated with trapping and detrapping processes near the oxide–semiconductor interface. A simplified model is

S_{id,1/f} = K_f I_D^a/(C_{ox}^2WLf^b),

where the exponents and coefficient depend on technology and bias. Increasing device area generally reduces flicker noise, making large input transistors useful in precision amplifiers. At sufficiently high frequency, thermal noise dominates; at low frequency, flicker noise can control the noise floor.

Shot noise is associated with discrete carrier transport across junctions and is important in leakage paths and some non-equilibrium conditions. Gate-current noise, induced gate noise, and correlation between drain and gate noise become relevant at radio frequencies. Noise modeling is therefore inseparable from device geometry, bias, temperature, and frequency.

Compact Models and SPICE Practice

A compact model is a computational representation of a transistor that provides terminal currents, charges, capacitances, noise, and sometimes temperature dependence as functions of terminal voltages and technology parameters. It must balance physical fidelity, numerical robustness, computational speed, and parameter identifiability.

The simplest SPICE-level model uses parameters such as VTO, KP, GAMMA, PHI, LAMBDA, TOX, UO, and junction parameters. These parameters are convenient for hand analysis and introductory simulation but may not accurately describe modern short-channel devices.

The BSIM family is widely used for advanced CMOS design. BSIM models include effects such as short-channel threshold variation, mobility reduction, velocity saturation, DIBL, channel-length modulation, quantum effects, self-heating, noise, and bias-dependent charges. Model versions and parameter sets are technology-specific; a designer should use the model supplied for the process rather than substituting nominal textbook values.

Compact models are generally charge-based or surface-potential based. Charge-based approaches calculate terminal charges consistently so that transient simulations conserve charge. This is essential in switched circuits. Model cards also include statistical parameters for process variation, mismatch, and Monte Carlo analysis. A model is not merely a list of measured device values; it is a mathematical abstraction intended to reproduce observable behavior over a specified range of geometry, bias, temperature, and frequency.

Parameter Extraction and Model Validation

Parameter extraction begins with measurement planning. Devices with different channel lengths and widths are required to separate geometry effects from process parameters. Typical measurements include output characteristics I_D–V_DS, transfer characteristics I_D–V_GS, capacitance–voltage data, leakage, temperature dependence, and low-frequency noise.

From the saturation transfer characteristic, a plot of √I_D versus V_GS can provide an approximate threshold voltage from the intercept and a mobility–oxide factor from the slope. This method is useful for long-channel devices but becomes unreliable when mobility degradation, series resistance, or short-channel effects are strong.

The transconductance method estimates threshold voltage using the relation between I_D/g_m and V_GS. Constant-current extraction defines V_T as the gate voltage at a specified drain current normalized to device width. This is reproducible but depends on the selected current criterion.

Channel-length modulation can be estimated from the slope of output characteristics in saturation. The inverse of the slope gives an estimate of r_o. DIBL can be evaluated by comparing extracted threshold voltage at two drain voltages:

DIBL ≈ −ΔV_T/ΔV_DS.

Capacitance extraction uses C–V curves and, where necessary, de-embedding structures to remove pad and interconnect parasitics. Extracted models must then be validated against data not used during fitting. Validation should cover multiple device dimensions, bias regions, temperatures, and frequencies. A model that fits one transfer curve but fails for output current, capacitance, or noise is not a reliable compact model.

Parameter correlation is a major difficulty. For example, mobility, series resistance, and effective channel length can produce similar changes in current. Therefore, extraction should use a physically informed sequence, independent structures, and optimization constrained by realistic parameter ranges.

Applied Design Example

Consider an illustrative long-channel nMOS transistor with μ_nC_ox = 200 μA/V², W/L = 10, and V_T = 0.5 V. Thus β = 2 mA/V². If V_GS = 1.5 V, then V_OV = 1.0 V. For V_DS = 0.2 V, the device is in triode because V_DS < V_OV, and

I_D = 2 mA/V² [(1.0)(0.2) − (0.2²/2)] = 0.36 mA.

If V_DS is increased to 1.2 V, the device is in saturation and

I_D = (1/2)(2 mA/V²)(1.0²) = 1.0 mA.

The ideal model predicts the same saturation current for any larger V_DS. If λ = 0.02 V⁻¹, the corrected current at V_DS = 1.2 V is approximately 1.024 mA. The corresponding transconductance is approximately 2I_D/V_OV = 2 mS, and the output resistance is approximately 1/(λI_D) ≈ 48.8 kΩ. These values immediately indicate the trade-off between gain, bias current, and output resistance.

Illustrative Case Study: Selecting a Model for a Precision Sensor Interface

Background

An engineering team is designing a low-frequency CMOS readout circuit for a capacitive sensor. The input transistor must provide high transconductance, low flicker noise, and predictable operation over temperature. The circuit will be fabricated in a modern bulk CMOS process.

Situation and Problem

An initial design based on the square-law model predicts adequate gain using minimum-length devices. Post-layout simulation, however, shows lower gain, increased offset, and excessive low-frequency noise. The team must determine whether the problem arises from incorrect hand analysis, layout parasitics, or unsuitable device dimensions.

Analysis

The minimum-length devices exhibit significant channel-length modulation and DIBL, reducing r_o. Their small area increases flicker noise and mismatch. The source voltage also varies with sensor signal, producing body-effect modulation. In addition, the gate–drain overlap capacitance and routing parasitics create an input pole that was absent from the initial calculation.

Approach and Solution

The team adopts the foundry BSIM model for all simulations and uses a gm/ID design methodology. Longer-channel input devices are selected to improve output resistance and reduce short-channel effects. Device area is increased to lower flicker noise and mismatch, while the bias current is chosen to operate in moderate inversion. A fully differential topology with common-mode feedback reduces sensitivity to supply and substrate disturbances. Layout includes guard rings, symmetrical matching, common-centroid placement, and isolated sensitive nodes.

Parameter sweeps are performed over process corners, temperature, supply voltage, and Monte Carlo mismatch. Noise is evaluated at the sensor bandwidth rather than only at a single nominal frequency. Extracted parasitic capacitances are included before final bandwidth decisions.

Outcome

The revised design achieves a more reliable gain estimate, lower input-referred flicker noise, and improved tolerance to process variation. The result is not obtained by using one more complicated equation, but by matching the modeling level to the design objective and validating the model across the operating envelope.

Learning Points

The case illustrates that compact models are essential for final design, while analytical models remain indispensable for intuition and initial sizing. It also shows that noise, body effect, capacitance, mismatch, and layout cannot be treated as independent after the circuit becomes precision-oriented.

Design Trade-offs, Limitations, and Common Errors

The square-law model is valuable for understanding but can be misleading when applied to short-channel devices, low-voltage operation, or high-frequency circuits. Common errors include identifying saturation solely from a high drain voltage, ignoring body bias, using V_T as a constant under all conditions, treating capacitances as fixed, and estimating gain with r_o omitted.

Another frequent mistake is confusing terminal current conventions in SPICE with textbook current directions. Designers should also distinguish intrinsic transistor dimensions from drawn dimensions, since spacer structure, diffusion extension, and layout-dependent effects alter effective length and width.

Model fitting can fail when too many parameters are adjusted simultaneously. Overfitting measured data may produce excellent agreement for one device while destroying physical consistency across dimensions. Temperature, self-heating, contact resistance, and measurement parasitics must be considered when extracting parameters.

Professional and Ethical Considerations

Compact models influence yield predictions, reliability margins, and product specifications. Engineers should document model version, parameter source, extraction conditions, and validity range. Reporting only typical-corner simulations can conceal failure risks. Process corners and statistical distributions should be based on defensible characterization rather than arbitrary margins.

When proprietary process models are used, confidentiality and access controls are essential. In safety-critical or high-reliability applications, traceability from measured data to model assumptions and design decisions is part of responsible engineering practice.

Current Developments

Modern MOSFET modeling increasingly addresses nanosheet and gate-all-around transistors, variability at extremely small dimensions, quantum confinement, self-heating, and non-equilibrium transport. Machine-learning methods are being explored for surrogate models, parameter extraction, and acceleration of circuit simulation. Their use is most effective when combined with physical constraints, because an unconstrained data-driven model may interpolate well but behave unrealistically outside the training range.

Compact models are also being extended for cryogenic electronics, radiation effects, flexible substrates, and three-dimensional integration. The central challenge remains unchanged: a model must be sufficiently accurate for the intended decision while remaining stable and efficient in a simulator.

Best Practices for Analysis and Simulation

1. Begin with the long-channel equations to establish the expected operating region and scale of currents.

2. Include body effect whenever source and body potentials differ.

3. Use gm, g_o, g_mb, and capacitances at the actual bias point rather than nominal values.

4. Select a process-qualified compact model for final simulation.

5. Verify model behavior over geometry, bias, temperature, frequency, and statistical corners.

6. Separate intrinsic device behavior from layout and measurement parasitics.

7. Use independent validation data when extracting or fitting parameters.

8. Report assumptions and validity ranges clearly.

Chapter Summary

The MOSFET operates by controlling an inversion channel through the electric field from its gate. Under the gradual-channel approximation, charge integration produces the triode current equation and the saturation square-law relation. Threshold voltage, body bias, and overdrive determine channel formation and current level. Practical devices exhibit channel-length modulation, mobility degradation, velocity saturation, DIBL, subthreshold leakage, and bias-dependent capacitance.

Small-signal parameters such as transconductance, output conductance, body transconductance, and intrinsic gain connect device physics with amplifier design. Gate, junction, and overlap capacitances determine switching and high-frequency behavior, while thermal and flicker noise establish important performance limits. Compact models such as BSIM extend analytical understanding to realistic circuit simulation. Reliable parameter extraction requires carefully designed measurements, physically meaningful fitting, and validation across dimensions and operating conditions. Effective MOSFET design therefore combines equations, measurement, simulation, layout awareness, and engineering judgment.

Key Terms

Threshold voltage: Gate-to-source voltage conventionally required to establish strong inversion.

Inversion layer: A mobile carrier layer at the semiconductor surface whose conductivity is controlled by the gate.

Overdrive voltage: The quantity V_GS − V_T.

Triode region: Operating region in which a channel exists from source to drain and current depends on both V_GS and V_DS.

Saturation region: Region beginning near V_DS = V_GS − V_T in which the drain-end channel pinches off.

Pinch-off: Reduction of inversion charge near the drain end at high drain voltage.

Body effect: Variation of threshold voltage caused by source-to-body bias.

Channel-length modulation: Increase in saturation current caused by reduction of effective channel length with drain voltage.

Transconductance: Incremental change in drain current per change in gate voltage.

Output conductance: Incremental change in drain current per change in drain voltage.

Body transconductance: Incremental drain-current response to source-to-body voltage.

DIBL: Drain-induced barrier lowering that reduces threshold voltage at high drain bias.

Subthreshold conduction: Exponential drain current occurring below the nominal threshold voltage.

Gate charge: Charge required to change the gate voltage and establish the channel state.

Miller effect: Effective multiplication of feedback capacitance in an inverting amplifier.

Flicker noise: Low-frequency noise commonly associated with interface traps and carrier trapping.

Compact model: Computational transistor model suitable for circuit simulation.

Parameter extraction: Determination of model parameters from measured device behavior.

Gm/ID methodology: Analog design approach based on transconductance efficiency.

Process corner: A model condition representing systematic manufacturing variation.

Review Questions

Short Answer Questions

1. What physical condition produces an inversion layer in an nMOS transistor?

2. State the condition separating the triode and saturation regions.

3. Why does body bias increase the threshold voltage of an nMOS transistor?

4. Define channel-length modulation and state its effect on output resistance.

5. Name two important MOSFET noise mechanisms.

Long Answer Questions

1. Derive the long-channel MOSFET drain-current equations for the triode and saturation regions.

2. Explain body effect and derive the standard threshold-voltage expression for an nMOS transistor.

3. Discuss the origins and circuit consequences of MOSFET capacitances.

4. Explain the role of BSIM-type compact models in modern integrated-circuit design.

5. Describe a systematic procedure for extracting and validating MOSFET parameters from measurements.

Analytical / Application Questions

1. A transistor has β = 1 mA/V², V_T = 0.6 V, and V_GS = 1.6 V. Determine the operating region and drain current for V_DS = 0.4 V and V_DS = 1.5 V.

2. An amplifier transistor operates at I_D = 0.5 mA with V_OV = 0.25 V and λ = 0.04 V⁻¹. Estimate g_m, r_o, and the intrinsic voltage gain magnitude.

3. A sensor interface exhibits excessive low-frequency noise and lower-than-expected gain. Using the concepts in this chapter, propose device-sizing, biasing, modeling, and layout changes and justify each one.

22. Multiple Choice Questions with Answers

Question 1

For a long-channel nMOS transistor, which condition indicates the onset of saturation?

A. V_DS = 0

B. V_DS = V_GS − V_T

C. V_GS = 0

D. V_DS = V_T − V_GS

Correct Answer: B. V_DS = V_GS − V_T

Question 2

If V_GS is fixed above threshold and V_DS is increased within the triode region, the ideal drain current initially does what?

A. Remains exactly zero

B. Decreases linearly

C. Increases according to a quadratic expression

D. Becomes independent of both voltages

Correct Answer: C. Increases according to a quadratic expression

Question 3

What is the principal effect of positive source-to-body voltage in an nMOS transistor?

A. It lowers threshold voltage

B. It raises threshold voltage

C. It eliminates channel-length modulation

D. It makes oxide capacitance zero

Correct Answer: B. It raises threshold voltage

Question 4

For a saturated long-channel MOSFET without channel-length modulation, transconductance can be written as:

A. g_m = V_OV/(2I_D)

B. g_m = 2I_D/V_OV

C. g_m = I_DV_OV

D. g_m = λ/I_D

Correct Answer: B. g_m = 2I_D/V_OV

Question 5

Channel-length modulation primarily causes which practical behavior?

A. Finite output resistance in saturation

B. Zero drain current below threshold

C. Constant gate current

D. Elimination of body effect

Correct Answer: A. Finite output resistance in saturation

Question 6

Which effect is most directly associated with multiplication of gate–drain capacitance in an inverting amplifier?

A. Body effect

B. Miller effect

C. DIBL

D. Velocity saturation

Correct Answer: B. Miller effect

Question 7

A larger input transistor area is commonly used in a precision amplifier mainly to reduce:

A. Flicker noise and mismatch

B. Oxide thickness

C. Thermal voltage

D. Threshold voltage to zero

Correct Answer: A. Flicker noise and mismatch

Question 8

DIBL is identified experimentally by observing that threshold voltage:

A. Increases as drain voltage increases

B. Decreases as drain voltage increases

C. Is independent of drain voltage in all devices

D. Depends only on gate overlap capacitance

Correct Answer: B. Decreases as drain voltage increases

Question 9

Which measurement is especially useful for estimating channel-length modulation?

A. The slope of the output characteristic in saturation

B. The package lead inductance

C. The source-body resistance alone

D. The oxide thickness without electrical data

Correct Answer: A. The slope of the output characteristic in saturation

Question 10

Why are charge-consistent compact models important in transient simulation?

A. They eliminate all process variation

B. They ensure physically consistent terminal charge and current behavior

C. They make every transistor long-channel

D. They remove the need for layout extraction

Correct Answer: B. They ensure physically consistent terminal charge and current behavior