6. MOS Capacitors and Semiconductor Interfaces

Introduction and Context

The metal–oxide–semiconductor (MOS) capacitor is one of the most important structures in semiconductor device physics. Although its geometry is simple, it contains the essential electrostatic principles used in MOSFETs, CMOS circuits, nonvolatile memories, sensors, and many semiconductor–insulator systems. The MOS capacitor provides a controlled way to study how an applied voltage redistributes charge in a semiconductor and how that redistribution is reflected in capacitance–voltage (C–V) measurements.

A practical MOS structure consists of a conducting electrode, an insulating layer, and a semiconductor substrate. The insulator prevents direct carrier transport under ideal conditions, while its electric field modifies the carrier concentration near the semiconductor surface. Depending on the applied gate voltage, the surface may experience accumulation, depletion, or inversion. Real devices depart from the ideal model because of fixed oxide charge, mobile ions, interface traps, oxide traps, nonuniform doping, leakage, and dielectric breakdown.

Understanding these effects is essential for extracting threshold voltage, evaluating oxide quality, selecting high-k dielectrics, interpreting experimental C–V curves, and designing reliable integrated devices.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain accumulation, depletion, and inversion in a MOS capacitor.

2. Derive and interpret the ideal MOS C–V characteristic.

3. Relate threshold voltage to substrate doping, oxide thickness, work-function difference, and charge effects.

4. Distinguish fixed oxide charge, mobile ionic charge, oxide-trapped charge, and interface-trap charge.

5. Explain high-frequency, low-frequency, and quasistatic C–V measurements.

6. Diagnose interface and oxide defects from C–V hysteresis, stretch-out, and frequency dispersion.

7. Evaluate high-k gate dielectrics and their principal reliability concerns.

8. Apply MOS capacitor concepts to device characterization and engineering decisions.

The MOS Structure and Its Electrostatic Basis

Consider a p-type semiconductor beneath an oxide and a metal gate. The oxide capacitance per unit area is

Cox = εox/tox,

where εox is the dielectric permittivity and tox is the physical oxide thickness. In the ideal case, the gate voltage is divided between the oxide and the semiconductor surface. The surface potential, ψs, measures the change in electrostatic potential between the bulk semiconductor and its surface.

The semiconductor charge is determined by the surface potential and the doping profile. For a uniformly doped substrate, the depletion width in the depletion approximation is

Wdep = [2εsψs/(qNA)]1/2,

for a p-type substrate, where εs is semiconductor permittivity, q is electronic charge, and NA is acceptor concentration. The depletion charge magnitude is

|Qdep| = qNAWdep = [2qεsNAψs]1/2.

The semiconductor capacitance associated with depletion is

Cs = εs/Wdep.

Because the oxide and semiconductor capacitances are in series, the measured capacitance is

C = (CoxCs)/(Cox + Cs).

This relation explains why the measured capacitance falls as the depletion region widens.

The metal–semiconductor work-function difference, φms, is an important built-in voltage. In an ideal MOS capacitor, the flat-band voltage is

VFB = φms.

For a nonideal device, charge in or near the oxide modifies this relation:

VFB = φms − Qox/Cox,

where Qox represents the appropriate effective charge per unit area. A shift in flat-band voltage is therefore a sensitive indicator of dielectric and interface conditions.

Accumulation, Depletion, and Inversion

For a p-type substrate, a sufficiently negative gate voltage attracts holes toward the semiconductor surface. The surface hole concentration exceeds its bulk value, producing accumulation. The semiconductor then behaves approximately as a conductor, and the measured capacitance approaches Cox.

When a positive gate voltage is first applied, holes are repelled from the surface. A region depleted of mobile majority carriers develops. The remaining ionized acceptor atoms form a negative space charge. As gate voltage increases, the depletion width grows and the total capacitance decreases because Cox is now in series with the smaller depletion capacitance.

At still higher positive voltage, electrons, which are minority carriers in the p-type substrate, are attracted to the surface. When the electron concentration at the surface becomes comparable to the hole concentration in the bulk, strong inversion is said to begin. The inversion layer can then conduct current and forms the channel of an n-channel MOSFET.

For a uniformly doped p-type semiconductor, the conventional strong-inversion condition is

ψs = 2φF,

where

φF = (kT/q) ln(NA/ni).

At this condition, the maximum depletion width is approximately

Wmax = [4εsφF/(qNA)]1/2,

and the maximum depletion charge is

|Qdep,max| = [4qεsNAφF]1/2.

The exact onset of inversion depends on the definition used and on measurement frequency. In a high-frequency C–V measurement, minority carriers cannot respond rapidly, so the inversion capacitance remains near its minimum value. In a low-frequency or quasistatic measurement, minority carriers follow the signal and the capacitance rises toward Cox.

For an n-type substrate, the voltage polarities and carrier types are reversed: positive voltage causes accumulation of electrons, negative voltage causes depletion followed by hole inversion.

The Ideal C–V Characteristic

The ideal C–V curve is conventionally plotted against gate voltage. In accumulation, C is approximately Cox. During depletion, C decreases as Wdep increases. In inversion, the curve depends strongly on frequency.

At high frequency, the alternating signal is too rapid for minority carriers to be generated, recombined, or transported sufficiently to follow it. The inversion-layer charge is therefore effectively fixed during the small-signal cycle, and the capacitance remains near

Cmin = (CoxCdep,max)/(Cox + Cdep,max),

where Cdep,max = εs/Wmax.

At low frequency, minority carriers respond to the ac signal. The inversion layer contributes charge variation, and the measured capacitance increases toward Cox. A quasistatic measurement uses a slowly varying voltage and can provide information about interface traps and minority-carrier response.

The distinction between high- and low-frequency C–V behavior is not merely instrumental. It reveals the time constants of carrier generation, recombination, and trapping processes. In nanoscale devices, series resistance, quantum confinement, polysilicon depletion, and nonuniform doping can further distort the measured curve.

A useful experimental procedure is to compare the measured curve with an ideal theoretical curve, determine the accumulation capacitance, locate the flat-band condition, estimate substrate doping from the depletion region, and examine frequency-dependent deviations. The comparison should account for measurement geometry and parasitic capacitance before physical conclusions are drawn.

Threshold Voltage and Its Physical Components

The threshold voltage of an n-channel MOS structure on a p-type substrate is commonly expressed as

VT = VFB + 2φF + |Qdep,max|/Cox.

For a device with source-to-body bias VSB, the depletion charge increases and produces the body effect:

VT(VSB) = VT(0) + γ([2φF + VSB]1/2 − [2φF]1/2),

where γ is the body-effect coefficient. For a uniformly doped substrate,

γ = [2qεsNA]1/2/Cox.

This expression illustrates several engineering trade-offs. Increasing oxide thickness reduces Cox and increases the depletion-charge contribution to threshold voltage. Increasing substrate doping increases φF and depletion charge, generally raising threshold voltage but also affecting mobility, junction capacitance, and variability. Work-function engineering permits threshold adjustment without relying exclusively on channel doping.

Threshold voltage is not an immutable material constant. It depends on temperature, body bias, oxide charge, interface traps, drain bias, stress history, and the extraction method. For this reason, a reported threshold voltage should always be associated with measurement conditions and a defined extraction procedure.

Charges and Defects at the Semiconductor–Insulator Interface

The ideal MOS model assumes a perfect insulator and a defect-free interface. Real structures contain several charge populations with different physical origins and time responses.

Fixed oxide charge is located near the semiconductor–oxide interface and is generally immobile under normal operating conditions. It shifts the flat-band and threshold voltages. Mobile ionic charge, often associated with alkali contaminants, can drift under electric field and temperature, causing bias-temperature instability and hysteresis.

Oxide-trapped charge is produced when carriers become trapped within the dielectric, frequently after electrical stress or radiation exposure. Its amount may depend on stress voltage, polarity, temperature, and time. Interface traps are electronic states at the semiconductor–insulator boundary. They can exchange charge with the semiconductor and therefore respond according to their energy level and time constant.

Interface-trap density is often denoted Dit, with units of cm−2 eV−1. Interface traps produce C–V stretch-out, frequency dispersion, conductance peaks, threshold-voltage instability, and degraded carrier mobility. Their effect is particularly significant near the bandgap, where they exchange charge with the surface over experimentally accessible time scales.

A practical diagnostic distinction is useful:

• A nearly rigid C–V voltage shift suggests fixed charge or work-function difference.
• Frequency dispersion and stretch-out suggest interface traps or slow states.
• Hysteresis suggests mobile charge or trapping and detrapping.
• Leakage and weak accumulation capacitance suggest dielectric defects, pinholes, or excessive tunneling.

These indicators are not perfectly unique; reliable diagnosis requires multiple measurement frequencies, sweep directions, temperatures, and stress conditions.

Interface-Trap Models and Measurement Methods

In the small-signal equivalent circuit, interface traps are represented by a frequency-dependent conductance and capacitance. At low frequency, traps can follow the ac signal and contribute to measured capacitance. At higher frequency, they cannot respond and instead produce a reduced response or dispersion.

The conductance method measures the parallel conductance, Gp/ω, as a function of frequency and bias. A peak occurs when the trap response time is comparable to the measurement period. This method can estimate Dit and trap time constants, although series resistance and nonuniform trap distributions must be carefully corrected.

The Terman method compares high-frequency experimental C–V data with an ideal curve to infer surface-potential distortion. The high–low method compares high-frequency and low-frequency curves, while quasistatic methods use a slow voltage sweep. Each method has assumptions concerning doping, leakage, frequency range, and minority-carrier generation. Agreement among independent methods is stronger evidence than reliance on a single extraction technique.

High-k Dielectrics and Equivalent Oxide Thickness

As conventional SiO2 becomes physically thin, direct tunneling produces unacceptable gate leakage. A high-k dielectric has a larger relative permittivity than SiO2 and can provide a larger capacitance at greater physical thickness. The equivalent oxide thickness is

EOT = tox,high-k (κSiO2/κhigh-k),

ignoring interfacial layers and other nonidealities. A smaller EOT improves electrostatic control, while the larger physical thickness reduces tunneling leakage.

Common high-k materials include hafnium-based oxides used in advanced CMOS technologies. Their integration is not simply a matter of maximizing dielectric constant. High-k films may introduce interface dipoles, fixed charge, border traps, remote phonon scattering, crystallization, oxygen vacancies, and reduced mobility. A thin interfacial SiO2 or silicon oxynitride layer is often retained to improve interface quality, but it increases total EOT.

The metal gate and dielectric must be selected as a system. Work-function compatibility, thermal stability, chemical reaction, Fermi-level pinning, deposition damage, and compatibility with subsequent processing all influence threshold voltage and reliability.

Reliability of Semiconductor–Insulator Interfaces

MOS reliability is governed by electrical, thermal, and environmental stresses. Time-dependent dielectric breakdown occurs when defect generation and percolation create a conductive path through the dielectric. The time to breakdown is statistically distributed and depends strongly on electric field, temperature, thickness, and defect population.

Bias-temperature instability causes threshold-voltage shift during prolonged positive or negative gate bias at elevated temperature. In p-channel devices, negative-bias temperature instability is especially important; positive-bias temperature instability affects n-channel devices. Charge trapping and interface-state generation contribute to the observed shift, which may partially recover after stress removal.

Hot-carrier injection occurs when energetic carriers near the drain enter the oxide or generate interface defects. Although reduced drain fields have limited this problem in many modern devices, it remains relevant in high-voltage and analog structures. Radiation can generate electron–hole pairs in the oxide, leaving trapped charge and interface states. Electromigration is not an oxide-interface mechanism, but interconnect and package stresses can interact with device reliability and must be considered at system level.

Reliability evaluation commonly includes constant-voltage stress, constant-current stress, charge-to-breakdown tests, bias-temperature stress, and repeated C–V measurements. A meaningful reliability model must distinguish intrinsic dielectric behavior from measurement artifacts, edge-field enhancement, contamination, and process variation.

Applied Case Study: Diagnosing a Shifted and Stretched C–V Curve

Background

An illustrative semiconductor laboratory fabricates aluminum/oxide/p-type silicon capacitors. The devices show an accumulation capacitance close to the expected oxide capacitance, but the C–V curve is shifted toward more positive gate voltage and becomes increasingly stretched at lower frequency.

Situation and Problem

The process engineer must determine whether the shift results from incorrect metal work function, fixed oxide charge, interface traps, or measurement error. The decision matters because the same dielectric process will later be used in MOSFETs.

Analysis

The correct accumulation capacitance indicates that the oxide thickness is approximately as intended and that gross area errors are unlikely. The voltage shift can be represented initially by an effective flat-band shift, ΔVFB, and an equivalent charge approximately equal to −CoxΔVFB, with sign interpreted according to the chosen voltage convention. However, the increased stretch-out and frequency dispersion cannot be explained by a purely rigid voltage shift. They indicate a distributed interface response or slow oxide states.

The engineer repeats measurements at several frequencies, reverses the voltage sweep, measures conductance, and checks series resistance. If the curve exhibits hysteresis, mobile ions or slow trapping are implicated. If conductance shows a frequency-dependent peak and the high-frequency curve remains stable, interface traps are the dominant concern. A comparison with an unprocessed control wafer helps separate metal work-function variation from dielectric-process damage.

Approach and Solution

The process team reduces plasma damage before dielectric deposition, improves preclean control, and adds a forming-gas anneal. It also establishes a standard measurement protocol with guarded probing, series-resistance correction, multiple frequencies, and controlled sweep rate. Dit and effective oxide charge are extracted using both conductance and C–V methods.

Outcome

After process modification, the C–V shift is reduced, frequency dispersion becomes smaller, and hysteresis falls within the intended process window. The remaining voltage offset is incorporated into the gate work-function and threshold-voltage design.

Learning Points

A C–V shift alone does not identify a unique defect mechanism. Accumulation capacitance, frequency dependence, hysteresis, conductance, temperature, and control samples must be considered together. Interface quality is a process-integration property rather than a characteristic of the dielectric material alone.

Engineering Challenges and Common Mistakes

Several errors recur in MOS characterization. Treating the oxide capacitance as the measured capacitance in depletion leads to incorrect extraction of doping. Using a high-frequency inversion capacitance to infer an equilibrium inversion charge is also incorrect. Ignoring series resistance can create artificial frequency dispersion, particularly in accumulation. Estimating oxide charge without accounting for work-function difference produces misleading results.

Another common mistake is to regard threshold voltage as a uniquely measured point. Constant-current, transconductance-extrapolation, C–V, and charge-based methods can yield different values. The extraction method must match the intended application.

At advanced technology nodes, classical equations may require correction for quantum confinement, non-Maxwellian carrier statistics, poly-depletion, two-dimensional electrostatics, and discrete dopant fluctuations. These corrections do not invalidate the MOS framework; they indicate where the ideal approximation must be supplemented by device simulation and calibrated measurement.

Professional Practice, Governance, and Emerging Directions

Interface characterization affects manufacturing yield, product qualification, safety margins, and long-term field reliability. Measurement data should be traceable to calibrated instruments, defined wafer locations, controlled temperature, and documented stress history. Statistical sampling is necessary because interface defects and breakdown are spatially and temporally variable.

Current research emphasizes interface engineering for high-k/metal-gate stacks, ferroelectric gate stacks, two-dimensional semiconductors, wide-bandgap materials such as SiC and GaN, and cryogenic electronics. Wide-bandgap devices introduce deep traps, surface states, and field-management challenges that cannot always be analyzed using silicon assumptions. Automated parameter extraction and machine-learning-based process monitoring can identify wafer-to-wafer anomalies, but such tools require physically meaningful features, representative training data, and independent validation. Automation should support, not replace, physical interpretation.

Best practice is to combine ideal modeling, equivalent-circuit analysis, controlled experiments, independent extraction techniques, and reliability testing. The most useful result is not merely a fitted parameter, but a defensible explanation linking a measured electrical signature to a physical mechanism and a process decision.

Chapter Summary

The MOS capacitor is a fundamental structure for understanding semiconductor surface electrostatics and the operation of MOSFETs. Applied voltage produces accumulation, depletion, and inversion, while the oxide and semiconductor capacitances determine the measured C–V response. High-frequency and low-frequency measurements differ because minority carriers and interface traps have finite response times.

Threshold voltage depends on work-function difference, substrate doping, oxide capacitance, depletion charge, body bias, and defect charge. Fixed oxide charge shifts the C–V curve, whereas interface traps produce stretch-out, frequency dispersion, hysteresis, and conductance response. High-k dielectrics reduce leakage for a given EOT but introduce interface, mobility, and reliability challenges. Breakdown, bias-temperature instability, hot-carrier effects, radiation damage, and charge trapping must be evaluated through controlled stress experiments. Sound engineering practice combines physical models, careful measurement, statistical analysis, and process-aware interpretation.

Key Terms

MOS capacitor: A metal–insulator–semiconductor structure used to study electrostatics and capacitance.

Accumulation: Increase of majority carriers at the semiconductor surface.

Depletion: Region near the surface depleted of mobile majority carriers.

Inversion: Surface condition in which minority carriers dominate over majority carriers.

Surface potential: Electrostatic potential difference between semiconductor surface and bulk.

Oxide capacitance: Capacitance per unit area of the insulating layer, εox/tox.

Flat-band voltage: Gate voltage at which semiconductor energy bands are flat.

Threshold voltage: Gate voltage conventionally associated with strong inversion and channel formation.

Fermi potential: Potential related to the difference between the Fermi level and intrinsic level.

Body effect: Threshold-voltage change caused by source-to-body bias.

Interface trap: Electronic state at the semiconductor–insulator boundary that exchanges charge.

Dit: Interface-trap density per unit energy and area.

Fixed oxide charge: Immobile charge located in or near the oxide interface.

Mobile ionic charge: Oxide charge capable of movement under electric field or temperature.

Oxide-trapped charge: Charge captured in dielectric defects, often after stress.

High-k dielectric: Insulator with permittivity higher than that of SiO2.

Equivalent oxide thickness: SiO2 thickness giving the same ideal capacitance as another dielectric.

C–V hysteresis: Difference between forward and reverse voltage sweeps caused by slow charge processes.

Bias-temperature instability: Stress-induced threshold-voltage shift under bias and temperature.

Time-dependent dielectric breakdown: Progressive dielectric degradation leading to a conductive failure path.

Review Questions

Short Answer Questions

1. Why does the capacitance of a p-type MOS capacitor decrease during depletion?

2. Define flat-band voltage and state how oxide charge affects it.

3. Why is the inversion capacitance frequency dependent?

4. What physical information is represented by Dit?

5. Define equivalent oxide thickness.

Long Answer Questions

1. Explain accumulation, depletion, and inversion in a p-type MOS capacitor using charge and band concepts.

2. Derive the expression for threshold voltage under the depletion approximation.

3. Compare high-frequency, low-frequency, and quasistatic C–V measurements.

4. Explain the origins and electrical signatures of fixed oxide charge, mobile ions, oxide traps, and interface traps.

5. Discuss the benefits, integration difficulties, and reliability concerns of high-k gate dielectrics.

Analytical / Application Questions

1. A MOS capacitor has a rigid C–V voltage shift but negligible frequency dispersion. Which defect mechanisms are most likely, and what additional experiment would distinguish work-function error from fixed oxide charge?

2. A device shows increasing threshold voltage after positive-temperature stress and partial recovery after stress removal. Propose a physical explanation and a measurement plan.

3. A high-k dielectric provides the desired EOT but produces lower mobility and strong C–V dispersion. Analyze the likely causes and recommend process or stack modifications.

22. Multiple Choice Questions with Answers

Question 1

For a p-type MOS capacitor, which condition corresponds to accumulation?

A. A negative gate voltage attracts holes to the surface

B. A positive gate voltage repels holes and leaves ionized acceptors

C. A positive gate voltage attracts electrons until strong inversion

D. The gate voltage makes the semiconductor bands flat

Correct Answer: A. A negative gate voltage attracts holes to the surface

Question 2

Why does the depletion-region capacitance decrease as positive gate voltage increases on a p-type substrate?

A. The oxide permittivity decreases

B. The depletion width increases, reducing semiconductor capacitance

C. The metal becomes electrically insulating

D. Minority carriers instantly neutralize the depletion charge

Correct Answer: B. The depletion width increases, reducing semiconductor capacitance

Question 3

In a high-frequency C–V measurement of a p-type MOS capacitor, the inversion capacitance remains near its minimum primarily because

A. majority carriers cannot respond

B. the oxide becomes thicker at inversion

C. minority carriers cannot follow the ac signal

D. the substrate becomes intrinsic

Correct Answer: C. minority carriers cannot follow the ac signal

Question 4

Which observation most directly indicates interface-trap response?

A. A purely rigid voltage translation with no frequency dependence

B. Frequency dispersion and stretch-out of the C–V curve

C. A larger metal work function only

D. A constant accumulation capacitance with zero conductance

Correct Answer: B. Frequency dispersion and stretch-out of the C–V curve

Question 5

If oxide thickness is reduced while all other parameters remain constant, Cox will

A. decrease

B. remain unchanged

C. increase

D. become zero in inversion

Correct Answer: C. increase

Question 6

The principal electrostatic advantage of a high-k dielectric is that it can

A. provide a larger physical thickness for a specified capacitance

B. eliminate all interface traps

C. make minority carriers infinitely fast

D. remove the need for a gate electrode

Correct Answer: A. provide a larger physical thickness for a specified capacitance

Question 7

A C–V curve displays pronounced hysteresis between forward and reverse sweeps. Which mechanism is most plausible?

A. Only ideal depletion capacitance

B. Mobile charge or slow trapping and detrapping

C. Perfectly fixed work-function difference

D. Zero oxide field

Correct Answer: B. Mobile charge or slow trapping and detrapping

Question 8

For an n-channel MOS structure on a p-type substrate, increasing substrate doping generally raises threshold voltage because it increases

A. only metal conductivity

B. the Fermi potential and depletion-charge contribution

C. the minority-carrier mobility without limit

D. the oxide bandgap

Correct Answer: B. the Fermi potential and depletion-charge contribution

Question 9

Which test is particularly useful for estimating interface-trap density through a frequency-dependent response?

A. Conductance method

B. Optical microscope inspection alone

C. Four-point probe measurement of the metal

D. Mechanical thickness measurement alone

Correct Answer: A. Conductance method

Question 10

A dielectric exhibits increasing leakage followed by a sudden conductive path after electrical stress. This behavior is most consistent with

A. accumulation

B. body effect

C. time-dependent dielectric breakdown

D. flat-band operation

Correct Answer: C. time-dependent dielectric breakdown