Radar Transmitters, Receivers and Digital Hardware

Introduction

A radar is only as capable as its radio-frequency front end and digital processing chain. Antenna gain and waveform design determine what a radar attempts to transmit and observe, but the transmitter must generate sufficient radiated energy, the receiver must detect extremely weak echoes in the presence of strong interference, and the digital hardware must preserve and exploit the information contained in those echoes. These functions are strongly coupled. Increasing transmitter power can improve detection range but may impose greater duplexer isolation, thermal-management, linearity, and regulatory requirements. Increasing receiver bandwidth can improve range resolution but also increases noise power and data rate. Selecting a high-speed analogue-to-digital converter (ADC) may be ineffective if the analogue front end has insufficient dynamic range or if the processing architecture cannot sustain the resulting data stream.

This chapter examines the architecture and evaluation of radar transmitters, power amplifiers, oscillators, duplexers, receivers, mixers, data converters, timing systems, FPGA and GPU processing, and software-defined radar. Emphasis is placed on design trade-offs, quantitative reasoning, implementation constraints, and the relationship between analogue and digital subsystems.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Compare radar transmitter architectures and select suitable oscillators and power amplifiers.

2. Explain duplexer operation and evaluate isolation, insertion loss, recovery time, and protection.

3. Analyse superheterodyne, homodyne, and direct-sampling receiver architectures.

4. Evaluate receiver noise, gain distribution, linearity, dynamic range, phase noise, and spurious responses.

5. Explain mixer operation and the implications of sampling, quantization, ADC/DAC resolution, and clock jitter.

6. Design a suitable division of labour among analogue circuits, FPGAs, GPUs, CPUs, and software.

7. Assess software-defined radar architectures and their practical limitations.

8. Apply best practices to a complete radar front-end design problem.

1. Radar Hardware Signal Chain

A conventional monostatic radar signal chain is

waveform generator → exciter → power amplifier → duplexer or circulator → antenna

on transmission, and

antenna → duplexer → limiter/protection → low-noise amplifier → mixer and local oscillator → IF or baseband filter → ADC → digital processor

on reception.

The exciter establishes carrier frequency, modulation, pulse timing, phase coherence, and often waveform agility. The power amplifier raises the signal to the required peak or average power. The duplexer permits one antenna to be shared by transmitter and receiver while limiting the large transmit leakage reaching the sensitive receiver. The low-noise amplifier (LNA) establishes receiver sensitivity, while mixers and local oscillators translate the signal to a frequency that can be filtered and digitized. Digital hardware performs matched filtering, pulse compression, Doppler processing, beamforming, detection, tracking, and data recording.

Important system-level requirements include peak power, average power, bandwidth, frequency stability, phase noise, receiver noise figure, maximum tolerable leakage, spurious-free dynamic range, latency, channel count, and data throughput. These requirements should be allocated across the signal chain rather than specified independently.

2. Radar Transmitters

2.1 Peak power, average power, and duty cycle

Peak power is important for short-pulse radars because it determines the instantaneous transmitted energy. Average power is important for thermal design, long-range surveillance, and continuous-wave or high-duty-cycle operation. For a periodic pulsed waveform,

\[

P_{avg}=P_{peak}\tau_r f_r=P_{peak}D,

\]

where \(\tau_r\) is pulse duration, \(f_r\) is pulse-repetition frequency (PRF), and \(D=\tau_r f_r\) is duty cycle. This relation assumes nearly constant power during the pulse and negligible power during the interpulse interval. For coded or shaped pulses, energy should be calculated by integrating instantaneous power; the simple expression is then an approximation based on the equivalent pulse width.

For a pulse of duration \(\tau\), transmitted energy is approximately

\[

E_t=P_{peak}\tau.

\]

A longer pulse increases energy but reduces uncompressed range resolution. Pulse compression allows a long, energy-rich waveform to achieve the resolution associated with a shorter effective bandwidth-limited pulse, subject to sidelobe and implementation constraints.

2.2 Oscillators and exciters

Radar oscillators must provide frequency accuracy, phase coherence, low phase noise, rapid tuning, and reliable synchronization. Common technologies include dielectric resonator oscillators, crystal-referenced synthesizers, phase-locked loops (PLLs), direct digital synthesis (DDS), and numerically controlled oscillators (NCOs).

A PLL locks a voltage-controlled oscillator to a reference through a feedback divider and phase detector. It provides frequency multiplication and controlled phase noise, but loop bandwidth creates a trade-off: a wide loop can suppress oscillator noise near the carrier but may transfer reference noise and spurs; a narrow loop improves filtering in some regions but slows settling and may allow more free-running oscillator noise.

DDS generates a digital phase trajectory and converts it to an analogue waveform. If the phase accumulator has \(N\) bits, its nominal frequency resolution is approximately

\[

\Delta f=\frac{f_{clk}}{2^N},

\]

where \(f_{clk}\) is the reference clock. The formula assumes an ideal accumulator and identifies tuning-word resolution, not necessarily actual frequency accuracy. Phase truncation, DAC quantization, clock jitter, and reconstruction-filter imperfections produce spurs and noise.

Phase noise is particularly important in coherent radar. Transmitter phase noise can raise range sidelobes or mask weak Doppler targets near strong clutter. Receiver local-oscillator phase noise can cause reciprocal mixing, in which strong off-channel signals are converted into in-band noise.

2.3 Power amplifier technologies

Vacuum electronic devices such as magnetrons, klystrons, and travelling-wave tubes can deliver high peak or average power, especially at microwave and millimetre-wave frequencies. Semiconductor devices, including silicon LDMOS, gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide technologies, offer solid-state reliability, modularity, fast control, and graceful degradation.

A magnetron is efficient and powerful but generally has poorer phase coherence and frequency control than a modern solid-state exciter. A klystron provides high gain and power with good coherence but is bulky and requires high-voltage infrastructure. GaN amplifiers offer high power density, high breakdown voltage, and broad bandwidth, but thermal design, device reliability, and linearity remain important.

Power-amplifier classes represent efficiency-linearity compromises. Class A is highly linear but inefficient. Class AB provides a practical compromise for modulated radar waveforms. Switching classes can be efficient but may require linearization and filtering. For linear frequency-modulated, phase-coded, or multicarrier waveforms, amplifier compression causes spectral regrowth, amplitude and phase distortion, and pulse-compression loss.

A useful measure is power-added efficiency (PAE),

\[

PAE=\frac{P_{out}-P_{in}}{P_{DC}},

\]

where \(P_{out}\), \(P_{in}\), and \(P_{DC}\) are RF output, RF input, and DC power. PAE is distinct from drain or collector efficiency because it subtracts input RF power. It is meaningful only with clearly stated operating conditions, frequency, modulation, and output power.

Thermal management is often the limiting design problem. Junction temperature depends on dissipated power, thermal resistance, mounting, cooling method, and ambient conditions. A modular solid-state radar may use many parallel amplifier modules so that failure of one module reduces power gradually rather than causing total failure.

2.4 Transmitter linearity and protection

Radar transmitters must tolerate reflected power caused by antenna mismatch, switching transients, and arcing. Protection may include isolators, circulators, directional couplers, fast shutdown, over-temperature sensing, and pulse blanking. Linearization techniques include digital predistortion, feedback, feedforward correction, and crest-factor management. These techniques are valuable when spectral masks, coexistence, or waveform fidelity are more important than maximum saturated power.

3. Duplexers, Circulators, and Receiver Protection

A duplexer enables a common antenna to transmit and receive while preventing transmitter energy from damaging or desensitizing the receiver. A circulator is a non-reciprocal multiport device that routes energy from port 1 to port 2, port 2 to port 3, and so on, depending on its design. A three-port circulator can connect transmitter, antenna, and receiver; an additional receiver limiter or filter is usually required.

Important duplexer specifications include:

• insertion loss in the receive path;
• isolation between transmitter and receiver;
• power-handling capability;
• switching or recovery time;
• bandwidth and tuning range;
• receiver leakage during transmission; and
• reliability under mismatch and high-voltage transients.

Insertion loss directly reduces sensitivity. If the duplexer contributes a loss \(L\) before the LNA, its noise factor is approximately equal to its loss when expressed as a linear ratio, assuming it is passive and at the reference temperature. Isolation must be evaluated against not only peak transmitter power but also receiver compression, leakage cancellation, limiter recovery, and local oscillator phase-noise effects.

A limiter protects the receiver by becoming strongly nonlinear above a threshold. It cannot be treated as an ideal switch: it introduces insertion loss, residual leakage, recovery time, noise, and possible distortion of weak signals immediately after a strong pulse. Receiver blanking is often coordinated with the transmit timing system, but excessive blanking reduces minimum detection range because echoes arriving during the blanking interval are lost.

4. Radar Receivers

4.1 Superheterodyne architecture

The superheterodyne receiver mixes the incoming RF signal with a local oscillator (LO) to produce an intermediate frequency (IF). Fixed IF filters can provide excellent selectivity and stable gain. Multiple conversion stages may be used to manage image rejection, bandwidth, and frequency planning.

The image frequency is an undesired RF frequency that produces the same IF after mixing. An RF preselector or image-rejection mixer is therefore required. Frequency planning must also identify LO harmonics, mixer products, clock spurs, and reciprocal-mixing products.

4.2 Homodyne and direct-conversion architecture

A homodyne receiver converts the signal directly to baseband. In-phase (I) and quadrature (Q) channels preserve amplitude and phase and permit positive and negative frequency discrimination. Direct conversion reduces the number of IF components and can be highly integrated, but it is sensitive to DC offset, LO leakage, I/Q gain mismatch, quadrature error, flicker noise, and even-order distortion.

A low-IF architecture shifts the signal to a small nonzero IF, reducing DC-offset problems while retaining much of the integration advantage. It requires digital image rejection and careful handling of the image band.

4.3 Noise figure and sensitivity

Thermal noise power in bandwidth \(B\) is

\[

N=kT_0BF,

\]

where \(k\) is Boltzmann’s constant, \(T_0\) is the reference temperature, and \(F\) is receiver noise factor in linear units. In decibels, the available thermal noise is approximately \(-174\) dBm/Hz at 290 K, so

\[

N_{dBm}\approx -174+10\log_{10}(B)+NF,

\]

where \(B\) is in hertz and \(NF=10\log_{10}F\) in decibels. This estimate assumes a matched system, room-temperature reference, and white noise over the stated bandwidth.

For cascaded receiver stages, Friis’ formula is

\[

F_{total}=F_1+\frac{F_2-1}{G_1}+\frac{F_3-1}{G_1G_2}+\cdots,

\]

where each factor is linear and each gain is available power gain. The equation shows why a low-noise, adequately protected first amplifier is important. Excessive loss before the LNA is especially damaging.

Worked example. A receiver has 2 MHz noise bandwidth and 4 dB noise figure. Its input-referred thermal noise is

\[

N=-174+10\log_{10}(2\times10^6)+4.

\]

Since \(10\log_{10}(2\times10^6)=63.01\) dB, \(N\approx -106.99\) dBm, or approximately \(-107\) dBm. A required signal-to-noise ratio of 10 dB would require about \(-97\) dBm at the receiver input, before accounting for detection processing gain or losses.

4.4 Gain distribution, AGC, and dynamic range

Gain must be distributed so that weak signals remain above internal noise while strong leakage, clutter, and interference do not cause compression. Automatic gain control (AGC) can protect later stages and ADCs, but rapid AGC changes may distort coherent amplitude information and complicate calibration. In pulse-Doppler radar, gain control may be scheduled by range, pulse, or operating mode rather than driven only by instantaneous amplitude.

Receiver dynamic range is not a single number. It includes noise-limited sensitivity, 1-dB compression point, third-order intercept behaviour, blocking performance, spurious-free dynamic range (SFDR), ADC range, and the ratio of the strongest tolerable signal to the weakest detectable signal. A receiver may have excellent noise figure but poor blocking, or a high-resolution ADC but insufficient analogue linearity.

For two equal-amplitude interferers, third-order intermodulation products increase approximately three decibels for every one-decibel increase in input level, while the desired fundamental increases one decibel. The third-order intercept point is an extrapolated figure, not a safe operating level; operation near it is highly nonlinear.

5. Mixers and Frequency Conversion

An ideal mixer multiplies two signals. If the inputs contain frequencies \(f_{RF}\) and \(f_{LO}\), output components occur at the sum and difference frequencies:

\[

f_{out}=|f_{RF}\pm f_{LO}|.

\]

Real mixers also produce harmonics, conversion loss or gain, noise, LO leakage, RF leakage, and intermodulation products. Passive diode mixers are robust and linear over useful ranges but have conversion loss. Active mixers provide conversion gain but may have lower linearity or greater flicker noise.

Image-reject and I/Q mixers use phase relationships to suppress unwanted products. Calibration is necessary because amplitude and phase imbalance limit image rejection. Mixer selection must consider RF, LO, and IF bandwidths, conversion loss, noise figure, input compression, intercept point, isolation, and LO drive level.

6. ADCs, DACs, Sampling, and Quantization

6.1 Sampling architecture

An ADC may sample RF directly, sample an IF, or sample complex baseband. Direct RF sampling simplifies analogue frequency conversion but demands high input bandwidth, clock quality, data movement, and careful anti-alias filtering. Undersampling or bandpass sampling can intentionally translate a narrow RF band into a lower digital frequency, provided spectral replicas do not overlap and the ADC input network supports the frequency.

The Nyquist criterion requires a band-limited signal to be sampled at a rate greater than twice its highest frequency when frequencies are measured from DC. For a bandpass signal, lower sampling rates can be used if the sampled spectral bands remain non-overlapping; this is a bandpass-sampling condition, not permission to ignore aliasing.

Anti-alias filters must suppress out-of-band signals before sampling. Digital decimation filters then reduce sample rate after conversion, but they cannot remove aliasing that occurred at the ADC input.

6.2 Resolution and quantization

For an ideal N-bit ADC with a full-scale peak-to-peak input range \(V_{FS}\), the quantization step is

\[

q=\frac{V_{FS}}{2^N}.

\]

For a uniformly distributed quantization error between \(-q/2\) and \(+q/2\), its rms value is \(q/\sqrt{12}\). For a full-scale sinusoid and ideal quantization, the theoretical signal-to-quantization-noise ratio is approximately

\[

SQNR\approx 6.02N+1.76\text{ dB}.

\]

This result assumes an ideal converter, a sinusoidal input using the available range, and quantization noise spread over the Nyquist band. Effective number of bits (ENOB) is lower in real systems because of thermal noise, aperture jitter, distortion, clock phase noise, and spurs.

Increasing bit depth does not automatically provide equivalent system performance. If the analogue front end compresses, or if a strong interferer consumes the ADC range, additional nominal bits may not recover weak-signal information. Digital gain after the ADC does not improve ADC SNR.

6.3 Clock jitter

Sampling-clock timing uncertainty produces an SNR limitation that becomes more severe at higher input frequency. For a sinusoidal input of frequency \(f_{in}\) and rms aperture jitter \(t_j\), a commonly used approximation is

\[

SNR_{jitter}\approx -20\log_{10}(2\pi f_{in}t_j).

\]

This relation assumes independent small timing errors and is most useful as an engineering estimate. It demonstrates why direct sampling at microwave frequencies requires exceptionally clean clocks.

DACs are used for waveform generation, exciter synthesis, digital beamforming, and calibration. DAC specifications must include update rate, reconstruction filtering, SFDR, phase noise, latency, output power, and synchronization. DAC images require analogue reconstruction filters unless intentionally used in a bandpass architecture.

7. Timing, Coherence, and Synchronization

Coherent radar requires stable relationships among transmitter excitation, receiver LO, ADC sampling, pulse timing, antenna switching, and digital processing. A timing architecture may contain a master reference oscillator, low-noise clock distribution, trigger generation, timestamping, deterministic-latency links, and calibration channels.

Timing errors affect range, Doppler, beamforming, and coherent integration. For a simple pulsed radar, range is related to round-trip delay by

\[

R=\frac{c\Delta t}{2},

\]

where \(c\) is propagation speed and \(\Delta t\) is measured delay. A timing error \(\delta t\) produces approximate range error \(c\delta t/2\). At 1 ns, this is about 0.15 m in free space. In distributed arrays, relative phase and timing alignment may be more important than absolute time.

Clock distribution should control additive phase noise, skew, drift, electromagnetic coupling, and deterministic latency. Calibration tones, loopback paths, temperature sensors, and periodic phase measurements are practical methods for maintaining coherence.

8. FPGA, GPU, CPU, and Software-Defined Radar

FPGAs are effective for deterministic, highly parallel, low-latency operations such as digital downconversion, finite impulse response filtering, pulse compression, channelization, beamforming, decimation, and thresholding. They offer predictable timing but require careful fixed-point design, resource allocation, verification, and management of high-speed interfaces.

GPUs provide very high arithmetic throughput for parallel operations such as large-scale FFTs, adaptive beamforming, image formation, and machine-learning inference. Their disadvantages may include transfer latency, power consumption, scheduling variability, and dependence on memory bandwidth. CPUs are flexible and well suited to control, tracking, mode management, networking, and irregular algorithms.

A practical architecture commonly assigns streaming front-end processing to FPGA fabric, computationally intensive batch processing to GPUs, and supervisory functions to CPUs. Partitioning should be based on latency, throughput, numerical precision, reconfiguration needs, power, and maintainability rather than processing speed alone.

Software-defined radar moves waveform generation, filtering, detection, and mode control into programmable digital hardware and software. Its benefits include rapid waveform changes, multi-mode operation, remote upgrades, laboratory experimentation, and common hardware across missions. Its limits include ADC/DAC performance, analogue front-end bandwidth, processing load, cybersecurity, electromagnetic compatibility, data storage, and certification of reconfigurable behaviour.

Software-defined architectures require disciplined interfaces and configuration control. Waveform files, calibration constants, FPGA bitstreams, and detection software should be versioned and authenticated. A flexible radar is not automatically an open radar: proprietary interfaces, timing dependencies, and classified algorithms can still limit interoperability.

9. Integrated Design Metrics and Trade-offs

Several trade-offs recur in radar hardware design:

• Bandwidth versus noise and data rate: wider bandwidth improves range resolution but raises noise power and samples per second.
• Power versus linearity and thermal load: saturation improves efficiency but distorts modulated waveforms.
• Gain versus dynamic range: gain helps sensitivity but can cause compression and ADC overload.
• Frequency agility versus phase continuity: rapid tuning may complicate coherent processing.
• Direct sampling versus analogue complexity: fewer mixers reduce components but increase clock, filtering, and data-movement demands.
• Processing performance versus power and latency: GPUs may accelerate algorithms but introduce transfer and thermal costs.
• Modularity versus calibration complexity: replaceable channels improve maintainability but increase channel-to-channel mismatch.

Evaluation should use end-to-end metrics: probability of detection at a specified false-alarm rate, minimum detectable signal, range and Doppler sidelobes, spurious response, phase coherence, maximum interferer level, latency, availability, power consumption, and maintainability.

10. Illustrative Case Study: Coastal X-Band Pulse-Doppler Radar

Background

Consider an illustrative, non-classified coastal surveillance radar operating near 10 GHz. It must detect small vessels in sea clutter, use a shared antenna, support frequency-agile linear-FM pulses, and process several receive channels for digital beamforming.

Problem

The initial design uses a high-power saturated amplifier, a receiver with 80 dB analogue gain, and a 14-bit ADC. Sea clutter and nearby transmit leakage saturate the receiver, while the amplifier’s spectral regrowth degrades pulse-compression sidelobes. Although the ADC has adequate nominal resolution, recorded data show clipping and intermittent false alarms.

Analysis

The system problem is not simply insufficient ADC bits. The receiver has excessive fixed gain, inadequate leakage recovery, and insufficient analogue filtering. The transmitter’s nonlinear operation produces out-of-band energy that enters the receiver through imperfect duplexer isolation. Strong clutter occupies much of the ADC input range, reducing effective weak-signal resolution.

Approach

The redesigned chain uses a coherent GaN amplifier operated with output back-off selected from measured error-vector magnitude and spectral-mask requirements. A circulator, limiter, fast blanking, and calibrated leakage monitor are added. The first receiver stage uses a low-noise amplifier followed by switchable attenuation and a bandpass filter. Gain is scheduled by range and operating mode. A 16-bit, 250-MS/s ADC samples the selected IF, while FPGA logic performs digital downconversion, decimation, pulse compression, and channel alignment. A GPU performs adaptive clutter suppression and beamforming. The timing subsystem distributes a low-phase-noise reference and records deterministic timestamps.

Outcome

The redesign reduces clipping, improves pulse-compression sidelobes, and permits more useful ADC codes for weak echoes. The increase in ADC resolution contributes only because the analogue gain and protection strategy allow the converter to operate within range. FPGA processing reduces front-end data volume before GPU transfer, lowering latency and interconnect load.

Learning points

1. ADC resolution cannot compensate for analogue overload.

2. Transmitter linearity affects receiver performance through leakage and interference.

3. Duplexer isolation must be evaluated with actual pulse timing and recovery behaviour.

4. Hardware partitioning should follow latency and data-flow requirements.

5. Calibration and timing infrastructure are central radar functions, not optional accessories.

11. Challenges, Governance, and Best Practices

Radar hardware faces component obsolescence, thermal cycling, vibration, electromagnetic compatibility, cyberattack, supply-chain risk, and regulatory constraints. Transmit frequency, radiated power, bandwidth, and unwanted emissions are governed by national and international spectrum regulations. High-power transmitters create hazards involving RF exposure, high voltage, stored energy, and thermal surfaces; engineering controls, interlocks, shielding, and maintenance procedures are mandatory.

Modern radars increasingly use adaptive processing and machine learning. These systems should be evaluated for training-data bias, robustness to adversarial interference, explainability of alarm decisions, and fail-safe behaviour. Automated classification should support, not obscure, human operational responsibility where safety or security decisions are involved.

Best practices include:

• establish an end-to-end noise, gain, power, and data-budget model;
• specify both nominal and worst-case dynamic-range conditions;
• measure phase noise, spurs, leakage, compression, and timing skew rather than relying only on datasheets;
• include calibration and built-in test paths from the beginning;
• use controlled interfaces between FPGA, GPU, CPU, and software;
• verify fixed-point implementations against floating-point references;
• design for thermal margins, graceful degradation, and maintainability;
• protect configuration files, firmware, timing sources, and recorded data; and
• validate performance with representative clutter, interference, temperature, and aging conditions.

Chapter Summary

Radar transmitters convert coherent waveforms into high-power RF energy, while receivers recover weak echoes in the presence of noise, leakage, clutter, and interference. Oscillator selection determines frequency agility, phase coherence, and phase-noise performance. Power amplifiers require a balance among output power, efficiency, linearity, reliability, and thermal management. Duplexers, circulators, limiters, and blanking systems protect receivers but introduce loss and recovery constraints.

Superheterodyne, homodyne, low-IF, and direct-sampling receivers offer different trade-offs in filtering, integration, image rejection, DC offset, clock quality, and data rate. Noise figure and Friis’ formula guide gain allocation, while compression, intercept points, blocking, and SFDR characterize dynamic range. Mixers generate desired frequency translations but also images, spurs, and intermodulation products.

ADC and DAC selection must consider bandwidth, resolution, ENOB, clock jitter, sampling architecture, filtering, latency, and data movement. Quantization theory is useful only when analogue overload and clock limitations are also considered. FPGA, GPU, CPU, and software functions should be partitioned according to deterministic latency, parallelism, power, memory bandwidth, and flexibility. Software-defined radar provides agility but increases demands for calibration, cybersecurity, verification, and configuration control.

Key Terms

Transmitter: Radar subsystem that generates and radiates RF energy.

Exciter: Coherent source that generates the radar carrier and modulation.

Power amplifier: Circuit that increases RF signal power for transmission.

Duty cycle: Fraction of time that a pulsed transmitter is active.

Phase noise: Short-term random phase fluctuation of an oscillator.

Duplexer: Network that permits shared antenna transmission and reception.

Circulator: Non-reciprocal device that routes signals between ports.

Limiter: Protective nonlinear device that restricts excessive receiver input.

Low-noise amplifier: Receiver amplifier designed to add minimal noise.

Noise figure: Measure of degradation in signal-to-noise ratio caused by a device.

Mixer: Frequency-conversion device producing sum and difference frequencies.

Image frequency: Undesired frequency that converts to the same IF as the wanted signal.

Dynamic range: Usable span between the weakest detectable and strongest tolerable signals.

ADC: Converter that represents an analogue waveform as digital samples.

Quantization: Mapping of continuous amplitude values to discrete digital levels.

ENOB: Effective number of bits representing actual ADC performance.

Clock jitter: Timing uncertainty in sampling or clock transitions.

FPGA: Reconfigurable digital device used for parallel, deterministic processing.

Software-defined radar: Radar whose functions are substantially controlled by programmable digital hardware and software.

Spurious-free dynamic range: Difference between a desired signal and the largest unwanted spur within a specified bandwidth.

Review Questions

Short Answer Questions

1. Distinguish peak power, average power, and duty cycle in a pulsed radar.

2. Why is the first receiver amplifier particularly important in a cascaded receiver?

3. What functions are performed by a duplexer and a receiver limiter?

4. State two limitations of direct-conversion receivers.

5. Why does ADC bit depth alone not determine receiver dynamic range?

Long Answer Questions

1. Compare magnetron, klystron, travelling-wave-tube, and solid-state radar transmitters.

2. Explain superheterodyne, homodyne, low-IF, and direct-sampling receiver architectures.

3. Derive and interpret the receiver noise-power and Friis noise-factor relationships.

4. Discuss ADC sampling, quantization, ENOB, clock jitter, and anti-alias filtering in radar.

5. Explain how FPGA, GPU, CPU, and software functions may be partitioned in a modern radar.

Analytical / Application Questions

1. A receiver has a 5 MHz bandwidth and 6 dB noise figure. Calculate its input-referred noise power using a 290 K reference and estimate the input signal required for a 12 dB SNR.

2. Design a gain and protection strategy for a pulse-Doppler receiver exposed to strong transmit leakage and weak distant echoes. Justify the placement of filtering, limiting, attenuation, and the LNA.

3. Evaluate whether direct RF sampling or IF sampling is more appropriate for a multi-channel X-band radar, considering clock jitter, data rate, analogue complexity, calibration, and processing latency.

Multiple Choice Questions with Answers

Question 1

For a pulsed radar with peak power P, pulse duration τ, and PRF f, the average power is approximately

A. P/(τf)

B. Pτf

C. P+τ+f

D. Pτ/f

Correct Answer: B. Pτf

Question 2

Which subsystem primarily establishes receiver sensitivity when it is placed at the receiver input?

A. Low-noise amplifier

B. Power amplifier

C. DAC

D. GPU

Correct Answer: A. Low-noise amplifier

Question 3

The principal purpose of a duplexer is to

A. increase ADC resolution

B. share an antenna while isolating transmitter and receiver

C. perform Doppler FFT processing

D. generate quantization noise

Correct Answer: B. share an antenna while isolating transmitter and receiver

Question 4

For an ideal N-bit ADC receiving a full-scale sinusoid, the approximate theoretical SQNR is

A. 3.01N dB

B. 6.02N+1.76 dB

C. 20N dB

D. N/6.02 dB

Correct Answer: B. 6.02N+1.76 dB

Question 5

A mixer ideally produces which frequencies from RF and LO inputs?

A. Only the RF frequency

B. Only the LO frequency

C. The sum and difference frequencies

D. The product of the frequencies in hertz

Correct Answer: C. The sum and difference frequencies

Question 6

According to Friis’ formula, increasing the gain of the first receiver stage generally

A. increases the contribution of later-stage noise

B. reduces the input-referred contribution of later-stage noise

C. eliminates all receiver noise

D. reduces antenna gain

Correct Answer: B. reduces the input-referred contribution of later-stage noise

Question 7

Which processing platform is especially suited to deterministic, low-latency digital downconversion and pulse compression?

A. FPGA

B. Mechanical relay

C. Thermal sensor

D. Passive antenna radome

Correct Answer: A. FPGA

Question 8

For a 2 MHz bandwidth and 4 dB noise figure, using −174 dBm/Hz thermal noise, the approximate receiver noise power is

A. −107 dBm

B. −174 dBm

C. −63 dBm

D. −4 dBm

Correct Answer: A. −107 dBm

Question 9

Sampling-clock jitter becomes more restrictive as which quantity increases?

A. Input signal frequency

B. Antenna height only

C. Cable colour

D. Pulse code alphabet size only

Correct Answer: A. Input signal frequency

Question 10

A major advantage of a software-defined radar is

A. elimination of all analogue hardware

B. unlimited dynamic range

C. programmable waveform and processing flexibility

D. absence of calibration requirements

Correct Answer: C. programmable waveform and processing flexibility