10. GPUs, Domain-Specific Architectures, and AI Accelerators

Introduction and Context

The performance of a computer system is determined not only by the speed of its processor but also by how effectively its architecture matches the workload. General-purpose CPUs remain essential because they support complex control flow, operating-system functions, irregular data structures, and a wide range of applications. However, many contemporary workloads—machine learning, image processing, scientific simulation, database analytics, cryptography, and signal processing—contain large amounts of regular parallel computation. For such workloads, specialized architectures can provide substantially higher performance per watt than a conventional CPU.

This chapter examines the architectural choices available beyond the traditional CPU. It compares CPUs, vector processors, graphics processing units (GPUs), field-programmable gate arrays (FPGAs), tensor processing units (TPUs), and custom accelerators. The central design question is not simply which processor is fastest. It is which architecture provides the best combination of throughput, latency, programmability, energy efficiency, precision, memory capacity, development cost, and adaptability for a particular workload.

The discussion connects parallel execution models—SIMD, SIMT, dataflow, and systolic computation—with practical concerns such as memory movement, numerical precision, sparsity, compiler support, and hardware-software co-design. These issues are especially important in artificial intelligence, where the computational workload is shifting from training large models to serving them efficiently under strict latency and energy constraints.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain the architectural differences among CPUs, vector processors, GPUs, FPGAs, TPUs, and custom accelerators.

2. Select an appropriate execution model for regular, irregular, vector, tensor, and streaming workloads.

3. Distinguish SIMD, SIMT, dataflow, and systolic-array computation.

4. Evaluate the effects of precision, sparsity, locality, and memory movement on accelerator performance.

5. Apply suitable metrics for comparing throughput, latency, energy efficiency, and total cost.

6. Explain why hardware-software co-design is essential for AI and analytics systems.

7. Identify practical, organizational, ethical, and governance issues associated with accelerator deployment.

From General-Purpose Processors to Specialized Machines

A CPU is designed for versatility. It typically contains a small number of sophisticated cores, each with deep memory hierarchies, branch prediction, out-of-order execution, speculative execution, and mechanisms for handling interrupts and irregular control flow. These features improve single-thread performance, but they also consume area and energy. A CPU is therefore often the best choice when a program contains unpredictable branches, pointer-based structures, operating-system activity, or limited parallelism.

A vector processor operates on a vector of data elements using one instruction. Instead of adding two numbers with repeated scalar instructions, a vector instruction can add corresponding elements of two arrays. Modern CPUs include vector extensions, but dedicated vector processors can provide wider registers, more vector lanes, and specialized memory systems. Vector execution is highly effective when operations are regular and the same instruction applies independently to many elements.

A GPU evolved from graphics hardware, where the same mathematical operations must be applied to many pixels or vertices. Modern GPUs contain many arithmetic units organized into groups of threads. They are optimized for high throughput rather than minimum latency for one thread. A GPU can execute thousands of lightweight threads, hiding memory latency by switching among them. This makes it suitable for matrix operations, image processing, simulations, and neural-network training.

An FPGA is an integrated circuit whose logic, routing, and memory resources can be configured after manufacture. Instead of executing a fixed instruction stream, an FPGA can be configured as a specialized datapath. Pipelines, parallel operators, custom interfaces, and application-specific memory structures can be created for a particular algorithm. FPGAs offer excellent flexibility after deployment and can achieve strong energy efficiency, but design and verification are more difficult than programming a CPU or GPU.

A TPU is a domain-specific architecture designed primarily for tensor operations used in machine learning. The term is commonly associated with architectures that include large arrays of multiply-accumulate units, high-bandwidth on-chip storage, and software stacks optimized for neural-network graphs. A TPU is not simply a faster CPU; it reflects assumptions about the dominance of dense matrix and tensor computation in AI workloads.

A custom accelerator is designed for a narrower application or algorithm family. It may be implemented as an application-specific integrated circuit (ASIC), an FPGA configuration, or a tightly integrated block within a system-on-chip. Its specialization can reduce instruction overhead, shorten data movement, and improve performance per watt. The trade-off is reduced flexibility and substantial non-recurring engineering cost.

Execution Models: SIMD, SIMT, Dataflow, and Systolic Computation

SIMD and vector execution

Single Instruction, Multiple Data (SIMD) applies one instruction to multiple data elements. A SIMD processor may contain several lanes, each performing the same operation on a different element. For example, a vector addition of arrays A and B can be expressed as

C[i] = A[i] + B[i]

for many values of i in parallel. SIMD performs best when data are independent, aligned, and processed by a common control path. Conditional operations may require masks. If different elements follow different branches, some lanes become inactive, reducing utilization.

SIMT and GPU execution

Single Instruction, Multiple Threads (SIMT) presents the programmer with many threads, although the hardware commonly executes groups of threads together. Threads in a group may share an instruction stream while operating on different registers and data. This model is more expressive than a conventional vector instruction because each thread has its own logical state, but it still performs best when threads follow similar control flow.

Branch divergence occurs when threads in the same execution group take different paths. The hardware may execute both paths serially while disabling threads that do not participate in each path. Thus, a GPU kernel with many divergent branches may have much lower effective throughput than its nominal arithmetic capacity suggests.

Dataflow and streaming execution

In a dataflow architecture, computation is represented as operations connected by data dependencies. An operation can execute when its input data are available, rather than waiting for a globally ordered instruction stream. Streaming accelerators use this principle to move data through pipelines of operators. They are especially effective for filtering, image processing, packet processing, and inference pipelines in which data are consumed once or a small number of times.

Systolic arrays

A systolic array consists of interconnected processing elements that repeatedly pass data to neighboring elements. Matrix multiplication is a typical example. One matrix may move horizontally through the array while another moves vertically; each processing element performs multiply-accumulate operations and forwards partial results. This organization reuses data locally, reducing the need to access external memory.

Systolic computation is attractive for dense tensor operations because it converts a large matrix operation into regular movement through a fixed spatial structure. Its efficiency depends on keeping the array occupied. Small matrices, irregular dimensions, sparse data, and operations that do not map naturally to the array can reduce utilization.

A Framework for Matching Workloads to Architectures

Architecture selection should begin with workload characterization rather than hardware preference. Important questions include:

• Is the workload compute-bound or limited by memory bandwidth?
• Are operations regular or irregular?
• Is parallelism available across data elements, tasks, or pipeline stages?
• Are low latency or high throughput more important?
• What precision is required?
• How much sparsity exists, and can the hardware exploit it?
• How often will the algorithm change?
• What software tools and libraries are available?

CPUs are appropriate for orchestration, serial sections, irregular algorithms, small batches, and control-intensive tasks. Vector processors are suitable for regular numerical loops with predictable memory access. GPUs are effective when thousands of threads can perform similar operations and sufficient data parallelism exists. FPGAs are attractive for deterministic streaming, low-latency embedded applications, and workloads requiring custom interfaces or carefully controlled power consumption. TPUs and tensor ASICs are appropriate for high-volume dense neural-network operations. Custom ASICs become compelling when an algorithm is stable, deployment volume is high, and energy or latency targets justify the design investment.

A heterogeneous system often provides the best solution. A CPU may manage input, scheduling, and exception handling; a GPU may perform dense training; an FPGA may preprocess sensor streams; and a neural accelerator may execute inference. The challenge is then to coordinate data movement and software execution across devices.

Performance Is More Than Arithmetic Throughput

Peak operations per second can be misleading. Real performance depends on utilization, memory traffic, synchronization, precision, and workload size. A useful first distinction is between compute-bound and memory-bound workloads. In a compute-bound workload, arithmetic units are the limiting resource. In a memory-bound workload, processors frequently wait for data.

The arithmetic intensity of a workload is commonly defined as

Arithmetic intensity = operations performed / bytes transferred from the relevant memory level.

A roofline-style analysis compares arithmetic intensity with the ratio of peak computational throughput to memory bandwidth. If arithmetic intensity is low, increasing the number of arithmetic units may provide little benefit. Improving locality, data reuse, compression, or memory bandwidth may be more effective.

Memory movement is often more expensive than arithmetic, particularly for low-precision AI operations. An accelerator may perform a multiplication in a fraction of the energy required to fetch operands from off-chip memory. Consequently, architectures place substantial emphasis on caches, scratchpad memories, register files, shared memory, tiling, blocking, and on-chip data reuse.

Tiling divides a large operation into blocks that fit in a fast local memory. In matrix multiplication, tiles of input matrices are loaded once and reused for many multiply-accumulate operations. The correct tile size depends on local storage capacity, bandwidth, array dimensions, and the shape of the workload.

Precision, Quantization, and Numerical Reliability

AI and analytics workloads need not always use 64-bit or 32-bit floating-point values. Many neural-network operations tolerate reduced precision such as FP16, BF16, INT8, or lower-bit integer formats. Reduced precision decreases storage requirements, increases effective bandwidth, and allows more operations per unit of hardware area.

Training often uses higher precision than inference because optimization involves accumulation, gradient updates, and numerical stability. Mixed-precision training uses low precision for selected matrix operations while retaining higher precision for sensitive accumulations or model parameters. Inference can frequently use integer quantization, provided that accuracy loss remains acceptable.

Quantization may be post-training or calibration-based, or it may be incorporated during training through quantization-aware methods. The appropriate format depends on the model, data distribution, error tolerance, and hardware support. Lower precision is not automatically better: overflow, underflow, rounding error, and accumulated numerical error can cause unacceptable results.

Precision must therefore be evaluated at the application level. In a medical diagnostic system, a small reduction in classification accuracy may have serious consequences. In an approximate recommendation system, a small numerical change may be acceptable if it improves response time and reduces cost.

Sparsity and Irregularity

A matrix or tensor is sparse when many elements are zero or insignificant. If zeros can be skipped, the system may reduce computation and memory traffic. Sparsity can be unstructured, with nonzero values appearing at arbitrary positions, or structured, with zeros following a regular pattern such as blocks or pruned channels.

Unstructured sparsity may provide high theoretical compression but is difficult to exploit because indices must be stored and memory access becomes irregular. Structured sparsity is easier for hardware to process, although it may remove fewer parameters. The value of sparsity depends on whether the accelerator has mechanisms for compressed storage, index processing, load balancing, and skipping operations.

Irregular workloads also arise in graphs, recommendation systems, database joins, and scientific simulations. These workloads may contain abundant parallelism but poor locality and unpredictable access patterns. A GPU or tensor array may underperform if threads repeatedly wait for scattered memory accesses. CPUs, large caches, specialized graph processors, or data-reordering techniques may be more suitable.

Hardware-Software Co-Design

Hardware and software cannot be optimized independently for specialized computing. The algorithm determines data dependencies, precision, sparsity, and parallelism; the architecture determines which of these properties can be exploited efficiently. A compiler, runtime system, and programming model connect the two.

Co-design may involve changing the algorithm to fit the hardware. For example, a neural network may be reorganized to use regular tensor shapes, a database query may be transformed into a vectorized pipeline, or a signal-processing algorithm may be expressed as a streaming graph. Conversely, hardware designers may add support for a frequently occurring operator, a new data type, or a particular memory-access pattern.

The software stack commonly includes a programming language or kernel model, compiler transformations, libraries, runtime scheduling, device drivers, and performance-monitoring tools. High-level frameworks can improve productivity but may hide costly data transfers or generate poorly tiled kernels. Low-level optimization can improve performance but increases development and maintenance costs.

Portability is another concern. A model optimized for one GPU architecture may not achieve comparable performance on another. Vendor-specific libraries can provide excellent performance but create dependence on a particular ecosystem. Organizations must balance immediate efficiency against long-term flexibility and procurement risk.

Applications Across Industry and Research

GPUs are widely used for deep-learning training, scientific simulation, video analytics, computational finance, and rendering. Their high throughput is valuable when large batches or many independent tasks are available.

FPGAs are used in telecommunications, high-frequency data processing, industrial control, aerospace systems, network appliances, and edge inference. Their deterministic pipelines and reconfigurability are particularly useful when latency and power are tightly constrained.

TPUs and AI ASICs are used in cloud inference, large-scale model training, speech processing, recommendation systems, and computer vision. Their value increases when workloads are stable and operated at high volume.

Vector extensions and specialized CPU instructions remain important in cryptography, compression, multimedia, linear algebra, and analytics. A CPU with capable vector units can avoid the complexity of deploying a separate accelerator for moderate workloads.

Accelerators also support edge computing. An autonomous vehicle, camera, or industrial sensor may need to analyze data locally because transmitting raw data is expensive, slow, or unsafe. Edge accelerators must operate within limits on power, thermal dissipation, physical space, and updateability.

Illustrative Case Study: Selecting an Architecture for Smart-Camera Inference

Background

Consider a fictional manufacturing organization developing a smart-camera system for detecting defects on a fast-moving production line. Each camera captures high-resolution images. The system must identify defects within a strict latency limit, operate continuously, and function in a factory where network connectivity is not guaranteed.

Situation and Problem

The initial prototype runs a convolutional neural network on a CPU. It achieves acceptable accuracy but consumes substantial power and occasionally misses the latency target when several cameras operate simultaneously. A cloud-based GPU solution is considered, but transmitting images introduces network dependence, privacy concerns, and unpredictable delay.

Analysis

The image pipeline contains regular convolution, activation, resizing, and classification operations. These operations provide substantial data parallelism and can use reduced precision after validation. However, the system also includes camera control, error handling, configuration, and communication tasks that are not ideal for a tensor accelerator. The solution must therefore be heterogeneous.

A GPU provides strong development support and can meet throughput requirements, but its power consumption and thermal requirements may be excessive at the edge. An FPGA can implement a streaming image pipeline with predictable latency and low data movement, although development requires hardware expertise. A compact AI ASIC may offer the best energy efficiency but would be difficult to modify if the model changes frequently.

Approach and Solution

The organization selects a CPU-plus-FPGA design. The CPU handles device management, network communication, model updates, and exceptional cases. The FPGA performs image preprocessing and quantized convolution through a pipelined datapath. Intermediate feature maps are retained in on-chip memory where possible. The team uses structured pruning and INT8 quantization, validating accuracy against a higher-precision reference model.

The design is evaluated using end-to-end latency, energy per image, accuracy, resource utilization, and behavior under multiple-camera load. Profiling shows that transferring intermediate data to external memory is a greater bottleneck than arithmetic computation, so the pipeline is reorganized to increase local reuse.

Outcome

The redesigned system satisfies the latency requirement with lower power consumption than the CPU prototype and avoids dependence on continuous cloud connectivity. Its main cost is a longer development cycle and greater difficulty in changing the model. The team therefore reserves part of the FPGA fabric and defines a model-update procedure that includes recompilation, verification, and controlled deployment.

Learning Points

The case demonstrates that architecture selection is a systems decision. The highest theoretical operation rate is not necessarily the best choice. Precision, data movement, power, latency, update frequency, and software expertise must be considered together. It also illustrates why a heterogeneous architecture can separate control-oriented and tensor-oriented functions effectively.

Challenges, Risks, and Common Mistakes

A frequent mistake is selecting an accelerator based only on peak throughput. Real applications may be limited by input preparation, host-device transfers, synchronization, or insufficient parallelism. Another mistake is ignoring batch size. Large batches improve accelerator utilization but may increase latency and memory consumption.

Developers may also assume that all neural-network operators are equally well supported. Unsupported or inefficient operators can force data transfers between devices or execution engines, eliminating the expected benefit. Model shapes that are irregular or too small may leave a systolic array or GPU underutilized.

Specialized hardware has lifecycle risks. A design may become obsolete when models, standards, or data types change. Supply-chain dependence, toolchain availability, licensing, and device security must be considered. Firmware and model updates create attack surfaces, especially in connected edge devices.

Benchmarking must use representative workloads. Synthetic microbenchmarks can exaggerate arithmetic performance while hiding memory and orchestration costs. Evaluation should include warm-up behavior, power limits, thermal throttling, realistic input distributions, and full application latency.

Ethical, Governance, and Professional Considerations

Accelerators make it economically feasible to deploy AI systems at large scale, but faster computation does not guarantee fair or reliable decisions. Engineers must validate model accuracy across relevant populations and operating conditions. If an accelerator uses quantization or approximation, its effect on errors should be documented rather than treated as a purely technical detail.

Data governance is also important. Edge inference may improve privacy by avoiding transmission of raw images, but local devices still require secure storage, access control, and authenticated updates. Hardware telemetry and performance counters may reveal sensitive information. Organizations should define responsibility for model failures, maintenance, security patches, and decommissioning.

Professional practice requires transparent performance claims. Reported throughput should state precision, batch size, workload composition, power conditions, and whether data-transfer costs are included. Comparisons that omit these conditions can mislead decision-makers.

Current Developments and Emerging Directions

Several trends are shaping accelerator design. Chiplet-based systems allow specialized compute and memory components to be combined in a package, potentially reducing the cost of building a complete monolithic chip. High-bandwidth memory and advanced interconnects address the growing movement of model parameters and activations.

The boundary between training and inference hardware is also becoming less distinct. Large models require distributed systems, while inference increasingly uses quantization, sparsity, caching, and specialized attention mechanisms. Domain-specific accelerators are being designed for recommendation, graph processing, signal processing, and scientific workloads rather than neural networks alone.

Compiler-generated accelerators and high-level synthesis are making FPGA and ASIC development more accessible. At the same time, automatic operator fusion, graph partitioning, and machine-learning-based scheduling are improving software utilization of heterogeneous systems. Near-memory and in-memory computing seek to reduce the energy cost of moving data, although issues of precision, programmability, manufacturing, and reliability remain significant.

Best Practices for Architecture Selection

A disciplined selection process should:

1. Characterize the complete workload, including preprocessing, postprocessing, control, and data transfer.

2. Measure representative latency, throughput, energy, memory use, and utilization.

3. Identify the dominant bottleneck using profiling and roofline-style analysis.

4. Select precision only after application-level accuracy and reliability testing.

5. Examine whether sparsity is hardware-usable rather than merely theoretical.

6. Estimate software, verification, deployment, and maintenance costs.

7. Design interfaces and data layouts to minimize movement between memories and devices.

8. Evaluate portability, vendor dependence, security, and future model changes.

9. Use heterogeneous execution when different stages have different architectural needs.

10. Treat benchmark methodology and operational constraints as part of the architecture specification.

Chapter Summary

CPUs provide versatility and strong support for irregular control flow, while vector processors exploit regular data-level parallelism. GPUs use SIMT execution to deliver high throughput for massively parallel workloads. FPGAs implement configurable datapaths and are valuable for deterministic, streaming, and power-constrained applications. TPUs and other tensor accelerators specialize in dense matrix and tensor operations, while custom ASICs maximize efficiency for stable, high-volume workloads.

The best architecture depends on workload structure rather than peak arithmetic capability. SIMD and SIMT favor regular parallel computation; dataflow supports streaming pipelines; and systolic arrays provide efficient local reuse for dense matrix operations. Precision, sparsity, memory hierarchy, arithmetic intensity, and data movement strongly influence real performance. Hardware-software co-design aligns algorithms, compilers, runtimes, and hardware resources. Professional decisions must also consider cost, portability, security, governance, accuracy, and lifecycle change.

Key Terms

CPU: A general-purpose processor optimized for versatile, control-oriented computation.

Vector processor: A processor that applies one operation to multiple data elements.

SIMD: Single Instruction, Multiple Data execution using parallel data lanes.

SIMT: Single Instruction, Multiple Threads execution commonly used by GPUs.

GPU: A throughput-oriented processor containing many parallel arithmetic resources.

FPGA: A reconfigurable integrated circuit whose logic and interconnect can be programmed after manufacture.

TPU: A tensor-oriented accelerator designed primarily for machine-learning operations.

ASIC: An application-specific integrated circuit designed for a particular function or workload.

Accelerator: Hardware that performs selected operations more efficiently than a general-purpose processor.

Systolic array: A network of processing elements that passes data rhythmically between neighbors.

Dataflow architecture: An architecture in which operations execute when required input data are available.

Arithmetic intensity: The ratio of computational operations to bytes transferred.

Tiling: Dividing a large computation into blocks that fit in faster local memory.

Quantization: Representing values with reduced numerical precision.

Mixed precision: Using different numerical formats within one computation.

Sparsity: The presence of zero or insignificant values that may be skipped or compressed.

Branch divergence: Different threads in one execution group following different control-flow paths.

Heterogeneous computing: Coordinated execution across different processor types.

Hardware-software co-design: Joint optimization of algorithms, software, compilers, and hardware.

Roofline model: A performance model relating arithmetic intensity, compute capacity, and memory bandwidth.

Review Questions

Short Answer Questions

1. Why are CPUs generally more suitable than GPUs for irregular control flow?

2. Define SIMD and distinguish it from SIMT.

3. What is the purpose of a systolic array?

4. Why can memory movement dominate the energy use of an AI accelerator?

5. What is structured sparsity?

Long Answer Questions

1. Compare CPUs, GPUs, FPGAs, TPUs, and custom ASICs in terms of programmability, throughput, latency, energy efficiency, and typical applications.

2. Explain how SIMD, SIMT, dataflow, and systolic execution models map different workloads to hardware.

3. Discuss the role of precision and quantization in AI accelerator design, including their benefits and risks.

4. Explain hardware-software co-design and identify the roles of compilers, runtimes, memory systems, and algorithms.

5. Describe a systematic process for selecting an accelerator for an industrial or cloud workload.

Analytical / Application Questions

1. A workload performs irregular graph traversal with frequent pointer chasing but contains millions of independent requests. Would a GPU necessarily be the best choice? Analyze the factors that should be evaluated.

2. An image-classification model achieves high theoretical speedup after pruning, but measured latency improves only slightly. Use memory movement, sparsity structure, and utilization to explain the result.

3. Design a heterogeneous architecture for a smart-camera or autonomous-sensor system. Justify the allocation of control, preprocessing, inference, and communication tasks among CPU, GPU, FPGA, or AI accelerator resources.

22. Multiple Choice Questions with Answers

Question 1

Which workload characteristic most strongly favors a GPU over a CPU?

A. Highly irregular pointer chasing with unpredictable branches

B. Thousands of independent operations following similar control flow

C. Frequent operating-system interrupts and exception handling

D. Very small sequential tasks with strict single-thread latency

Correct Answer: B. Thousands of independent operations following similar control flow

Question 2

What is the principal effect of branch divergence in a SIMT execution group?

A. It increases the number of arithmetic units available

B. It causes different paths to be executed serially or with inactive threads

C. It automatically converts scalar instructions into vector instructions

D. It eliminates the need for synchronization

Correct Answer: B. It causes different paths to be executed serially or with inactive threads

Question 3

Why are systolic arrays efficient for dense matrix multiplication?

A. They avoid all local storage

B. They rely on unpredictable memory accesses

C. They reuse data through regular transfers between neighboring processing elements

D. They execute only scalar control instructions

Correct Answer: C. They reuse data through regular transfers between neighboring processing elements

Question 4

A workload has low arithmetic intensity and is limited by off-chip memory bandwidth. Which improvement is most likely to help first?

A. Adding more arithmetic units without changing data movement

B. Increasing data reuse through tiling and improving memory locality

C. Increasing branch prediction depth

D. Reducing the number of software threads to one

Correct Answer: B. Increasing data reuse through tiling and improving memory locality

Question 5

What is a principal advantage of FPGA-based acceleration?

A. It provides unlimited programmability with no design effort

B. It can implement customized pipelines and interfaces after manufacture

C. It always has higher peak throughput than every GPU

D. It requires no verification or hardware expertise

Correct Answer: B. It can implement customized pipelines and interfaces after manufacture

Question 6

Why might structured sparsity be preferred to unstructured sparsity in an accelerator?

A. It makes all values nonzero

B. It is easier for hardware to store, schedule, and exploit predictably

C. It always preserves exactly the original model accuracy

D. It removes the need for model compilation

Correct Answer: B. It is easier for hardware to store, schedule, and exploit predictably

Question 7

Which statement best describes mixed-precision computation?

A. Every operation uses the same high-precision format

B. Different parts of a computation use numerical formats selected for efficiency and stability

C. All values are converted to binary before execution

D. Precision is changed randomly during execution

Correct Answer: B. Different parts of a computation use numerical formats selected for efficiency and stability

Question 8

In the smart-camera case, why was a CPU-plus-FPGA design appropriate?

A. The CPU and FPGA perform identical functions

B. The CPU handled control while the FPGA implemented a predictable streaming inference pipeline

C. The FPGA was used only to increase network bandwidth

D. The CPU was removed because accelerators cannot perform control tasks

Correct Answer: B. The CPU handled control while the FPGA implemented a predictable streaming inference pipeline

Question 9

Which metric is most appropriate for evaluating an edge inference accelerator when power is constrained?

A. Peak clock frequency alone

B. Energy per inference together with latency and accuracy

C. Number of programming languages supported only

D. Theoretical number of transistors

Correct Answer: B. Energy per inference together with latency and accuracy

Question 10

What is the central purpose of hardware-software co-design?

A. To optimize hardware without considering algorithms

B. To ensure that algorithms, compilers, runtimes, and hardware exploit one another’s capabilities

C. To replace all software with fixed circuits

D. To guarantee that one accelerator supports every workload equally well

Correct Answer: B. To ensure that algorithms, compilers, runtimes, and hardware exploit one another’s capabilities