11. Energy, Thermal, Cost, and Sustainable Design

Introduction: Why Physical Efficiency Is an Architectural Concern

Computer architecture is often introduced through performance measures such as instruction throughput, latency, clock frequency, and parallelism. In modern systems, however, performance cannot be optimized independently of energy, temperature, manufacturing cost, reliability, and environmental impact. A processor that delivers excellent benchmark results but exceeds its thermal envelope, requires an expensive cooling system, or consumes excessive energy during years of operation may be inferior to a slightly slower but substantially more efficient design.

The physical constraints of computing have therefore become architectural constraints. Battery-powered devices are limited by stored energy. Data centres are limited by electrical capacity, cooling infrastructure, rack density, and operating expenditure. Embedded and safety-critical systems must control temperature to preserve reliability. At the manufacturing level, die area, defect density, packaging complexity, and yield strongly influence product cost. At the organizational level, carbon emissions and lifecycle policies increasingly influence procurement and system design.

This chapter develops a unified way to reason about these concerns. It examines dynamic and static power, energy and performance trade-offs, thermal modelling, dynamic voltage and frequency scaling (DVFS), power gating, area and yield, packaging, total cost of ownership, and carbon impact. The central argument is that sustainable computer design is not a separate environmental activity added after performance engineering; it is a multidimensional optimization problem that begins with architectural choices.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Distinguish power, energy, dynamic power, static power, and energy-delay measures.

2. Estimate power using switching, leakage, voltage, frequency, and capacitance models.

3. Explain thermal resistance, temperature limits, hotspots, and cooling constraints.

4. Analyse DVFS, power gating, clock gating, and other power-management techniques.

5. Relate die area, defect density, yield, packaging, and manufacturing cost.

6. Evaluate total cost of ownership across acquisition, operation, maintenance, and disposal.

7. Estimate operational and embodied carbon in computing systems.

8. Make architecture decisions using performance, energy, thermal, economic, and sustainability criteria.

From Performance-Centred Design to Multidimensional Optimization

Power is the instantaneous rate at which energy is consumed, measured in watts. Energy is the accumulated work performed by a system, measured in joules. A processor consuming 50 W for 10 seconds uses 500 J. Confusing these quantities leads to poor design decisions: a high-power processor may complete a task quickly and use less total energy than a low-power processor that runs for a much longer time.

A useful first metric is energy per operation or energy per instruction. For a workload requiring time \(T\) and average power \(P_{avg}\),

\[

E = P_{avg}T.

\]

For a fixed workload, reducing execution time does not necessarily reduce energy, because higher performance often requires higher voltage, frequency, switching activity, or active hardware. Architecture therefore involves trade-offs among throughput, latency, energy, peak power, and thermal behaviour.

Two commonly used combined metrics are energy-delay product (EDP) and energy-delay-squared product (ED\(^{2}\)P):

\[

EDP = E \times T,

\qquad ED^2P = E \times T^2.

\]

EDP penalizes designs that are simultaneously energy-hungry and slow. ED\(^{2}\)P gives greater importance to delay and is sometimes useful in performance-sensitive systems. These metrics should not replace workload-specific requirements, but they help compare architectural alternatives when no single measure is sufficient.

A design objective can be expressed abstractly as:

\[

\min F = w_pP + w_eE + w_tT + w_cC + w_gG,

\]

where the terms represent power, energy, execution time, cost, and environmental impact, and the weights reflect the application context. In practice, many decisions are constrained rather than freely weighted: for example, performance must exceed a target, temperature must remain below a limit, and cost must fit a product budget.

The Power Model: Switching, Short-Circuit, and Leakage

Dynamic power

Dynamic power is consumed when circuit nodes charge and discharge during logic transitions. A widely used approximation is:

\[

P_{dyn} = \alpha C_{eff}V^2f,

\]

where \(\alpha\) is the activity factor, \(C_{eff}\) is effective switched capacitance, \(V\) is supply voltage, and \(f\) is clock frequency. The equation has important architectural implications.

First, power increases linearly with frequency. Second, it increases quadratically with voltage, making voltage reduction particularly valuable. Third, reducing switching activity through clock gating, operand isolation, better algorithms, or reduced communication can lower power without necessarily reducing the clock frequency. Fourth, smaller capacitance can be achieved through shorter wires, smaller devices, fewer transitions, and improved physical organization.

Dynamic power includes capacitive switching power and, in some models, short-circuit power arising when both pull-up and pull-down transistors conduct briefly during a transition. The simple equation is not a complete transistor-level model, but it is highly useful for architectural reasoning.

Static or leakage power

Static power is consumed even when a circuit is not actively switching. It is commonly approximated as:

\[

P_{static} = I_{leak}V,

\]

where \(I_{leak}\) is leakage current. Leakage includes subthreshold leakage, gate-oxide leakage, and other device-dependent currents. As transistors become smaller and threshold voltages are reduced, leakage can become a substantial fraction of total power, particularly in large arrays and high-temperature conditions.

Leakage is strongly temperature-dependent. A hotter chip generally leaks more current, which increases power and may produce still more heat. This positive feedback is one reason thermal management and leakage management cannot be treated independently. Techniques such as high-threshold devices, power gating, body biasing, transistor stacking, and retention-aware sleep modes can reduce leakage.

Total chip power is often represented as:

\[

P_{total}=P_{dyn}+P_{static}+P_{short-circuit}+P_{I/O}+P_{memory},

\]

although the categories may overlap depending on the measurement method. System-level power also includes voltage regulators, memory modules, storage, fans, networking, displays, and conversion losses.

Activity and workload dependence

Power is not a fixed property of a processor. A vector-processing workload, a memory-intensive workload, and an idle operating system state activate different resources. Average power must therefore be measured or modelled over representative workloads. Peak power matters for voltage regulators, batteries, power delivery networks, and cooling; average power matters for energy bills and battery life.

Counters and sensors can report instructions, cache misses, cycles, temperature, voltage, and package power. These data support performance-per-watt analysis, but measurements must be interpreted carefully. Sensor accuracy, sampling interval, workload variability, and the boundary of the measured system all affect conclusions.

Energy Efficiency Techniques Across the Architecture

Voltage and frequency scaling

Dynamic voltage and frequency scaling changes operating voltage and clock frequency according to workload demand. Lowering frequency generally permits lower voltage, and because dynamic power depends on \(V^2\), the reduction can be substantial. DVFS is effective when the workload has slack, variable demand, or deadlines that can still be met at a lower operating point.

A simplified execution model assumes that work is proportional to the number of cycles and that execution time varies inversely with frequency. If a task is slowed from frequency \(f_1\) to \(f_2\), its active duration increases approximately by \(f_1/f_2\). Whether energy decreases depends on the power reduction and the additional time. Static leakage and fixed platform power may reduce or eliminate the benefit of aggressive slowing.

DVFS is not free. Voltage regulators have conversion losses, transitions require time, and frequent changes can complicate scheduling. Memory and I/O devices may not scale in the same way as cores. A lower processor frequency may leave a memory-bound application almost unchanged in completion time while providing only modest energy benefit.

Clock gating and power gating

Clock gating disables the clock to inactive sequential logic. It reduces switching activity while preserving the state of the gated block. It is relatively fast and is suitable when a unit is idle for short intervals.

Power gating disconnects an inactive block from its supply or ground through sleep transistors. It can greatly reduce leakage, but waking the block requires time and energy. State may be lost unless retention registers or memory are used. Power gating therefore requires an idle interval long enough to recover the transition cost. The break-even condition can be expressed conceptually as:

\[

T_{idle} > \frac{E_{enter}+E_{exit}}{P_{saved}},

\]

where the numerator is the energy required to enter and leave the low-power state and the denominator is the power saved while sleeping.

Architectural approaches

Energy can be reduced by exploiting specialization, locality, parallelism, and approximation. A dedicated accelerator may perform a task with fewer instructions and less data movement than a general-purpose core. Near-memory processing can reduce expensive movement between memory and processor. Caches reduce repeated accesses to slower and often more energy-intensive levels of the memory hierarchy, although large caches consume leakage and area.

Parallelism creates a nuanced trade-off. Running several units at a lower voltage and frequency may complete a task with less energy than one unit at a high frequency, but additional cores increase area, leakage, and communication. The best choice depends on workload parallelism, synchronization, data movement, and deadline requirements.

Thermal Design and Reliability

Electrical power becomes heat. A first-order steady-state thermal model is:

\[

T_{junction}=T_{ambient}+P\theta_{JA},

\]

where \(T_{junction}\) is chip temperature, \(T_{ambient}\) is ambient temperature, and \(\theta_{JA}\) is junction-to-ambient thermal resistance in °C/W. More detailed models separate junction-to-case, case-to-sink, and sink-to-ambient resistances:

\[

T_J=T_A+P(\theta_{JC}+\theta_{CS}+\theta_{SA}).

\]

This model is an approximation. Real chips exhibit spatial temperature variation, transient effects, package-dependent heat spreading, and workload-dependent hotspots. A core near a memory controller or dense accelerator may be much hotter than the average die temperature.

Thermal design power (TDP) is a design target for sustained cooling capability, not necessarily the absolute maximum instantaneous power. Designers must distinguish sustained power, short-duration boost power, and emergency thermal limits. If temperature approaches a limit, hardware may throttle frequency, reduce voltage, migrate work, or shut down.

Temperature affects reliability through mechanisms such as electromigration, time-dependent dielectric breakdown, bias temperature instability, and solder or interconnect fatigue. A commonly used qualitative relationship is that failure rates increase rapidly with temperature, often approximated by an Arrhenius model. Consequently, thermal headroom supports not only performance but also service life and warranty reliability.

Thermal management operates at several levels: heat spreaders and heat sinks, fans and liquid cooling, package and floorplan optimization, workload scheduling, thermal-aware DVFS, and emergency protection. Cooling itself consumes power, so reducing chip power can produce a second-order energy benefit by reducing fan or chiller demand.

Area, Yield, Packaging, and Manufacturing Economics

Die area influences cost, performance, power, and yield. A larger die can contain more cache, cores, or accelerators, but it is more likely to contain a manufacturing defect. A simplified yield model is:

\[

Y \approx e^{-AD_0},

\]

where \(A\) is die area and \(D_0\) is defect density. More elaborate models account for clustering and systematic defects, but the basic relationship captures the economic penalty of area.

Wafer cost is distributed across the number of usable dies. Approximate dies per wafer depend on wafer area, die area, and edge losses. The cost per good die is influenced by wafer processing cost, packaging cost, test cost, and yield. A large monolithic die may provide high bandwidth and low interconnect latency, but it can have poor yield and high cost.

Chiplet-based design divides a system into smaller dies connected within a package. Smaller dies can improve yield and allow reuse of independently manufactured components. Chiplets may also permit process specialization: logic, I/O, analog circuits, and memory can use different technologies. However, chiplets introduce die-to-die communication energy, package complexity, testing challenges, latency, and standards concerns.

Packaging is therefore an architectural consideration. 2.5D interposers, 3D stacking, high-bandwidth memory, and advanced organic substrates can improve density and performance, but they increase thermal and manufacturing complexity. In 3D stacks, heat removal is especially difficult for layers away from the cooling surface. Thermal-aware placement and vertical partitioning become necessary.

Design-for-test, redundancy, spare rows and columns in memories, and binning can improve effective yield. Binning classifies manufactured parts according to measured frequency, voltage, power, and defects. A chip that fails a top performance category may still be sold in a lower-performance product, reducing economic waste.

Total Cost of Ownership and the Economics of Efficiency

Purchase price is only one component of total cost of ownership (TCO). A system-level TCO model may include:

\[

TCO=C_{capital}+C_{energy}+C_{cooling}+C_{facility}+C_{software}+C_{maintenance}+C_{downtime}+C_{disposal}.

\]

Capital cost includes servers, accelerators, networking, storage, racks, and power-delivery equipment. Operating cost includes electricity, cooling, staff, software licences, repairs, and replacement parts. Downtime has direct and indirect costs, particularly for financial, industrial, and cloud services.

Energy efficiency may justify a higher purchase price when the system operates for many years or at high utilization. A simple payback period is:

\[

Payback = \frac{Additional\ capital\ cost}{Annual\ operating\ savings}.

\]

This calculation should include workload throughput. A slower but efficient machine may require more machines to meet a service-level objective, eliminating apparent savings. Conversely, a high-performance system may complete work quickly and remain idle, producing lower energy per task than a continuously operating low-performance system.

For data centres, useful metrics include power usage effectiveness (PUE):

\[

PUE=\frac{Total\ facility\ energy}{IT\ equipment\ energy}.

\]

A lower PUE indicates that a greater proportion of energy reaches computing equipment. PUE does not measure computational efficiency; a facility can have excellent PUE while running inefficient workloads. It should therefore be combined with metrics such as energy per transaction, energy per inference, or performance per watt.

Carbon Impact and Sustainable Architecture

The environmental impact of computing has at least two major components. Operational carbon arises from electricity consumed during use. Embodied carbon arises from extraction, semiconductor fabrication, packaging, transport, construction, and disposal. A simplified operational estimate is:

\[

Carbon_{operational}=Energy_{IT}\times Carbon\ intensity_{electricity}.

\]

Carbon intensity varies by location, time, generation mix, and contractual accounting method. Workload shifting to a region or time with lower-carbon electricity can reduce operational emissions, but network distance, latency, water use, and data sovereignty may impose constraints.

Embodied carbon becomes particularly important for devices with low utilization or short replacement cycles. Extending useful life, repairing equipment, reusing components, and designing for recycling can reduce lifecycle impact. However, retaining an obsolete system may increase operational energy and security risk. Sustainable decisions must compare the full lifecycle rather than assume that newer is always better or that replacement is always wasteful.

Water consumption is another concern. Semiconductor fabrication and data-centre cooling may require substantial water resources. A design with lower electrical energy but higher water use may not be preferable in a water-stressed region. Sustainability assessment should therefore consider energy, carbon, water, materials, toxicity, and end-of-life recovery where data are available.

A Decision Framework for Sustainable Architecture

A practical evaluation can proceed through the following sequence:

1. Define the workload, service-level objectives, lifetime, utilization, geographic deployment, and safety constraints.

2. Establish performance, power, temperature, area, cost, and carbon baselines.

3. Identify architectural alternatives such as more efficient cores, accelerators, chiplets, memory changes, or workload placement.

4. Model both average and peak behaviour, including idle periods, cooling, power conversion, and communication.

5. Evaluate manufacturing yield, packaging, software effort, reliability, and supply-chain risks.

6. Test alternatives using representative workloads rather than synthetic peak benchmarks alone.

7. Apply sensitivity analysis to electricity price, carbon intensity, utilization, defect density, and product lifetime.

8. Select a design that satisfies hard constraints and performs well across plausible future conditions.

Pareto analysis is useful when no single design dominates. A design is Pareto-optimal if improving one objective would worsen at least one other objective. For example, a chiplet system may reduce manufacturing cost and improve yield but increase package cost and communication energy. Decision-makers should make such trade-offs explicit rather than hide them inside a single score.

Illustrative Case Study: Sustainable Inference at the Edge

Background

Consider an illustrative company developing a vision system for industrial inspection. The device must process camera frames locally, respond within 50 ms, operate continuously for three years, and fit within a sealed enclosure with limited cooling. Network transmission of raw images is undesirable because of latency, privacy, and connectivity constraints.

Situation and alternatives

The engineering team considers three architectures. Alternative A uses a high-frequency general-purpose processor. Alternative B uses a lower-frequency multicore processor with a specialized inference accelerator. Alternative C uses a still smaller processor and sends selected frames to a remote cloud service.

Analysis

Alternative A satisfies latency but produces high heat in the sealed enclosure. Its peak power requires a larger heat spreader and creates thermal throttling during sustained workloads. Alternative C has low local power but violates the latency requirement under network congestion and transfers sensitive images outside the facility. Its total carbon impact also depends on cloud infrastructure and network energy.

Alternative B reduces operations through specialization and local data reuse. Although its purchase price is higher than that of the general-purpose processor, it performs inference at lower energy per frame. The team evaluates accelerator utilization, memory traffic, idle intervals, wake-up costs, enclosure temperature, and three-year electricity consumption rather than comparing peak TOPS alone.

The team also considers manufacturing yield. A large monolithic design would have greater die area, whereas a processor-plus-accelerator package permits a smaller logic die and a separately tested accelerator. The package is more complex, but the expected good-die cost is lower at the planned production volume.

Strategy and solution

The selected design combines the accelerator with a modest multicore controller, power gates unused accelerator blocks between batches, and uses DVFS for periods of reduced camera activity. Thermal sensors trigger workload redistribution and a conservative frequency limit. The software pipeline performs early image filtering so that only relevant regions enter the expensive inference stage.

Outcome

The design meets the latency target under normal operation, remains within the enclosure thermal limit, and reduces energy per processed frame relative to the general-purpose alternative. It also avoids continuous image transmission. The team documents that the result depends on actual accelerator utilization; if future workloads change substantially, the assumed energy advantage may decline.

Learning points

The case demonstrates that sustainable architecture is not equivalent to selecting the component with the lowest nominal wattage. It requires workload analysis, thermal modelling, software-hardware cooperation, manufacturing assessment, privacy consideration, and lifecycle evaluation. Specialization is valuable when utilization is high enough to offset its area and integration cost.

Risks, Limitations, and Common Design Errors

Power models are abstractions. The activity factor may be unknown, capacitance may vary with physical implementation, leakage models may be inaccurate, and system-level conversion losses may be omitted. Early estimates should therefore include uncertainty ranges and later be validated through measurement.

A common mistake is optimizing average power while ignoring peak power. A second is reporting performance per watt without specifying workload, precision, utilization, or measurement boundary. A third is applying DVFS to a memory-bound workload and expecting a proportional energy reduction. A fourth is power-gating blocks that wake too frequently, causing more transition energy and latency than they save.

Designers may also neglect cooling energy, embodied carbon, software development cost, and end-of-life treatment. Another error is assuming that a smaller die always produces a cheaper product; multiple dies, advanced packaging, testing, and interconnects can reverse the result. Finally, sustainability claims can become misleading when they use favourable operational assumptions while excluding manufacturing or replacement effects.

Professional, Ethical, and Governance Considerations

Engineers should report energy and carbon results with clear system boundaries, workload definitions, operating conditions, and time horizons. Selective benchmarking can create technically impressive but environmentally misleading claims. Procurement teams should request evidence for power, reliability, repairability, component availability, and lifecycle assumptions.

Energy-efficient systems can also create rebound effects. Lower cost per computation may encourage more computation, offsetting some savings. Data collection for power monitoring must respect privacy and security, particularly when workload traces reveal business activity. Thermal throttling and power management in safety-critical systems require verification because an energy-saving action must not violate response-time or reliability requirements.

Environmental responsibility also includes responsible disposal of batteries, electronic components, and cooling materials. Regulatory requirements may address energy efficiency, hazardous substances, right to repair, electronic waste, and emissions reporting. Architecture decisions should be reviewed with procurement, operations, compliance, and sustainability stakeholders rather than treated as purely technical choices.

Current Developments and Emerging Directions

Several developments are reshaping sustainable computer design. Heterogeneous computing combines general-purpose cores, graphics units, vector engines, neural accelerators, and reconfigurable logic. Near-memory and processing-in-memory approaches seek to reduce data movement, which is often a major energy cost. Advanced chiplets and 3D integration improve density but intensify thermal and testing challenges.

Machine-learning-based power management can predict workload phases, temperature, and idle intervals to select operating points more effectively than simple threshold policies. Digital twins and detailed thermal simulation support early exploration of floorplans, cooling, and workload placement. Carbon-aware orchestration can schedule flexible workloads according to electricity carbon intensity, while workload-level carbon accounting attempts to associate emissions with particular services.

New non-volatile memories, photonic interconnects, approximate computing, and domain-specific architectures may reduce energy for selected workloads. Their benefits are application-dependent and may be offset by manufacturing complexity, programming difficulty, limited precision, or immature supply chains. Sound architecture requires evaluating these technologies against complete system requirements rather than assuming that novelty implies sustainability.

Best Practices for Design Teams

A disciplined team should establish energy, thermal, cost, and carbon requirements at the beginning of architecture development. It should measure representative workloads, separate active, idle, and transition energy, and include the complete platform boundary. It should model both average and peak power, examine thermal hotspots, and verify cooling assumptions under realistic ambient conditions.

Design reviews should include yield, package, test, maintenance, utilization, and end-of-life considerations. Alternatives should be compared using energy per useful result rather than only watts or peak performance. Sensitivity analysis should expose assumptions that could change the decision. Finally, post-deployment telemetry should be used to validate models and improve future designs.

Chapter Summary

Energy, thermal behaviour, manufacturing economics, and sustainability are fundamental dimensions of computer architecture. Dynamic power is approximately proportional to switching activity, capacitance, frequency, and the square of voltage, while static power arises from leakage and grows in importance with device scaling and temperature. Energy depends on both power and execution time, so performance-per-watt must be complemented by energy per task and, where appropriate, energy-delay metrics.

DVFS, clock gating, power gating, specialization, locality, and parallelism provide ways to reduce energy, but each introduces timing, state-retention, area, software, or transition costs. Thermal resistance connects power to junction temperature, and thermal limits affect performance, reliability, packaging, and cooling energy. Die area influences yield and cost; chiplets can improve yield and flexibility but add package and communication complexity.

Total cost of ownership includes capital, energy, cooling, maintenance, downtime, and disposal. Sustainable assessment must include operational and embodied carbon, electricity carbon intensity, water, materials, and equipment lifetime. Effective architectural decisions use workload-based measurement, explicit constraints, uncertainty analysis, and Pareto trade-offs. The most sustainable design is the one that delivers required useful work reliably over its lifecycle with acceptable economic and environmental cost.

Key Terms

Dynamic power: Power consumed by charging and discharging capacitances during circuit transitions.

Static power: Power consumed when a circuit is not switching, primarily due to leakage currents.

Activity factor: Fraction or probability of circuit nodes undergoing switching activity.

DVFS: Dynamic adjustment of voltage and frequency according to workload demand.

Clock gating: Disabling the clock to inactive logic to reduce switching power while retaining state.

Power gating: Disconnecting inactive logic from its supply to reduce leakage power.

Energy-delay product: Product of energy consumption and execution time used to compare trade-offs.

Thermal resistance: Temperature rise per unit of dissipated power, measured in °C/W.

Thermal hotspot: Localized region whose temperature is significantly higher than the chip average.

TDP: Thermal design power used as a sustained cooling-design target.

Die area: Physical silicon area occupied by an integrated circuit.

Defect density: Expected number of manufacturing defects per unit wafer area.

Yield: Proportion of manufactured units that meet functional specifications.

Chiplet: Independently manufactured die integrated with other dies in a package.

Total cost of ownership: Lifetime cost including acquisition, operation, maintenance, and disposal.

PUE: Ratio of total data-centre facility energy to IT equipment energy.

Operational carbon: Emissions associated with electricity consumed during system operation.

Embodied carbon: Emissions associated with manufacture, transport, construction, and disposal.

Pareto-optimal design: Design for which improving one objective requires worsening another.

Carbon intensity: Emissions associated with a unit of consumed electricity.

Review Questions

Short Answer Questions

1. Differentiate power from energy using a computing example.

2. Why does voltage reduction usually have a stronger effect on dynamic power than frequency reduction?

3. What is the purpose of clock gating?

4. Define thermal resistance and state its unit.

5. Distinguish operational carbon from embodied carbon.

Long Answer Questions

1. Explain the dynamic and static power models and discuss the architectural variables that influence each.

2. Analyse DVFS and power gating, including their benefits, transition costs, and suitable use conditions.

3. Explain how power, thermal limits, reliability, and cooling infrastructure interact in processor design.

4. Discuss the relationships among die area, defect density, yield, packaging, chiplets, and manufacturing cost.

5. Develop a total-cost and lifecycle-sustainability framework for evaluating a data-centre server.

Analytical / Application Questions

1. A workload can run on one high-frequency core or four lower-frequency cores. Describe the measurements and constraints needed to determine which option has lower energy per completed task.

2. An accelerator saves 20 W while active but requires 4 J each time it is powered down and restarted. Explain how the minimum useful idle interval should be determined and what additional factors must be considered.

3. Compare a locally executed edge-inference design with a cloud-offloaded design using performance, privacy, operational energy, embodied impact, cooling, carbon intensity, and TCO as decision criteria.

22. Multiple Choice Questions with Answers

Question 1

Which change produces the strongest direct reduction in the simplified dynamic-power model when all other variables remain constant?

A. Halving frequency

B. Halving effective capacitance

C. Halving supply voltage

D. Doubling activity factor

Correct Answer: C. Halving supply voltage

Question 2

A processor completes a fixed task in 4 seconds at 50 W. What energy does it consume during the task?

A. 12.5 J

B. 54 J

C. 200 J

D. 250 J

Correct Answer: C. 200 J

Question 3

Which technique reduces switching activity while preserving the state of an inactive sequential block?

A. Power gating

B. Clock gating

C. Increasing leakage current

D. Raising supply voltage

Correct Answer: B. Clock gating

Question 4

Power gating is most appropriate when a block is expected to remain inactive long enough that:

A. Its clock frequency can be increased

B. The energy saved exceeds entry and exit energy costs

C. Its switching activity becomes higher

D. Its thermal resistance becomes zero

Correct Answer: B. The energy saved exceeds entry and exit energy costs

Question 5

In the simplified thermal model, increasing thermal resistance while holding power constant will generally:

A. Lower junction temperature

B. Increase junction temperature

C. Eliminate leakage power

D. Increase manufacturing yield

Correct Answer: B. Increase junction temperature

Question 6

Which statement best describes the economic effect of increasing die area?

A. It always improves yield

B. It can increase functionality but generally raises defect exposure and cost

C. It eliminates packaging costs

D. It has no effect on manufacturing economics

Correct Answer: B. It can increase functionality but generally raises defect exposure and cost

Question 7

What does PUE measure in a data centre?

A. Processor utilization divided by memory utilization

B. IT equipment energy divided by computing throughput

C. Total facility energy divided by IT equipment energy

D. Carbon emissions divided by cooling power

Correct Answer: C. Total facility energy divided by IT equipment energy

Question 8

A workload is moved to a region with lower-carbon electricity but higher network latency. Which principle is most relevant?

A. Optimize carbon without considering service constraints

B. Evaluate sustainability together with performance and operational requirements

C. Ignore electricity carbon intensity

D. Measure only peak processor frequency

Correct Answer: B. Evaluate sustainability together with performance and operational requirements

Question 9

Why can chiplets improve manufacturing economics?

A. They guarantee zero communication energy

B. They allow smaller dies that may have better yield and process specialization

C. They remove the need for package testing

D. They always reduce total package complexity

Correct Answer: B. They allow smaller dies that may have better yield and process specialization

Question 10

Which metric most directly reflects the energy efficiency of completing a useful workload?

A. Peak clock frequency

B. Die area alone

C. Energy per completed task

D. Thermal resistance alone

Correct Answer: C. Energy per completed task