Inverters and Pulse-Width Modulation

Introduction and context

An inverter is a static power converter that produces an alternating-voltage or alternating-current output from a direct-current source. Inverters are central to photovoltaic systems, battery energy storage, motor drives, uninterruptible power supplies, flexible AC transmission, induction heating, and grid-forming converters. Their principal design problem is not merely switching a semiconductor on and off; it is synthesizing a prescribed fundamental waveform while controlling harmonic distortion, switching loss, electromagnetic interference, common-mode voltage, semiconductor stress, and thermal rise.

Pulse-width modulation (PWM) solves this problem by controlling the duration of switching states. A high-frequency sequence of discrete converter states is selected so that its average voltage over a switching interval follows a low-frequency reference. At postgraduate level, inverter analysis must therefore connect switching functions, Fourier spectra, space vectors, modulation limits, energy storage, loss mechanisms, and control implementation.

Learning objectives

After completing this chapter, the reader should be able to:

1. Explain the operation and classification of voltage-source and current-source inverters.
2. Derive the principal voltage relationships of half-bridge, full-bridge, and three-phase inverters.
3. Compare sinusoidal PWM, third-harmonic injection, and space-vector PWM (SVPWM).
4. Calculate dwell times, modulation limits, harmonic quantities, ripple, semiconductor stress, and thermal requirements.
5. Explain dead-time distortion, overmodulation, common-mode voltage, and practical gate-drive constraints.
6. Select an appropriate modulation strategy for a specified converter application.

1. Inverter structures and switching functions

A voltage-source inverter (VSI) is supplied by a stiff DC-link voltage and uses controllable switches, normally with antiparallel diodes, to impose output voltage. A current-source inverter (CSI) is supplied by a nearly constant current and uses commutation arrangements that shape output current. This chapter focuses mainly on VSIs because they dominate modern motor drives and grid converters.

For an ideal two-level half-bridge, the switching function s_a takes values +1 and −1. With a split DC link of total voltage V_dc, the pole voltage is

where O is the midpoint. In a full bridge, the output voltage is the difference between two pole voltages:

The complementary switches in one leg must not conduct simultaneously. A dead time is inserted between turn-off and turn-on commands. Real switching states also include diode conduction, device voltage drops, finite transition times, and parasitic inductance.

For a balanced three-phase, two-level VSI, each leg has two valid states. The eight possible switching combinations contain six active voltage vectors and two zero vectors. In the stationary αβ plane, the active vectors have magnitude 2V_dc/3 and are separated by 60°. The zero vectors are 000 and 111.

2. Fundamental waveform relationships

For a single-phase full bridge producing a bipolar square wave ±V_dc, the Fourier series is

The nth odd harmonic has peak magnitude 4V_dc/(nπ). The square wave has a large fundamental but unacceptable low-order harmonics in many applications.

For a three-phase six-step inverter, triplen harmonics cancel in the line voltage because they are common-mode components. However, low-order non-triplen harmonics remain, producing torque pulsation and additional machine loss. PWM shifts much of the distortion toward the switching-frequency region, where it can be attenuated by motor inductance or an output filter.

The RMS value of a periodic waveform is

For a sinusoidal phase voltage with peak value V_1,pk, V_1,rms = V_1,pk/√2. For a balanced sinusoidal three-phase system, line RMS voltage is √3 times phase RMS voltage.

3. Sinusoidal PWM

In sinusoidal PWM (SPWM), a sinusoidal reference is compared with a triangular carrier. For a two-level leg, define the carrier-based modulation ratio

within the linear region 0 ≤ m_a ≤ 1. For a three-phase VSI using a sinusoidal phase reference, the fundamental phase-voltage peak is

and the fundamental line-to-line RMS voltage is

These equations assume ideal switches, a stiff DC link, centered carrier comparison, balanced references, and no overmodulation or dead-time error.

The ratio of carrier frequency to fundamental frequency is the frequency-modulation ratio:

where f_s is switching frequency and f₁ is fundamental frequency. A larger m_f generally reduces low-frequency distortion but increases switching loss.

Third-harmonic injection

A zero-sequence third-harmonic component can be added to all three references without changing ideal line-to-line voltage. Proper third-harmonic injection increases the usable linear DC-bus utilization by approximately 15.5% compared with pure sinusoidal carrier PWM. The improvement is obtained by reshaping the reference so its maximum and minimum remain within the carrier bounds; it does not mean that a fixed reference automatically produces a 15.5% larger fundamental.

4. Space-vector PWM

4.1 Modulation convention

A frequent source of error is the use of different modulation-index definitions. In this chapter, the SVPWM index is defined as

where V_ref,pk is the magnitude of the desired fundamental space-vector reference. Under this definition, the linear limit is

because the reference must remain inside the hexagon’s inscribed circle. The corresponding fundamental phase peak is

and the line-to-line RMS voltage is

Some literature instead defines m = V_ref,pk/(V_dc/2). Under that convention, the linear limit is 2/√3 ≈ 1.1547, and the phase-peak relationship is V_ph,1,pk=mV_dc/2. These are equivalent descriptions, not different physical capabilities. Any numerical comparison must identify the convention.

4.2 Dwell-time derivation

During one switching period T_s, a reference vector in sector k is synthesized from the two adjacent active vectors and a zero vector. Let θ be the angle measured from the first active vector in that sector, with 0≤θ≤π/3. The adjacent active-vector dwell times are

The total zero-vector time is

These equations apply in the linear region, where T₀≥0. With the chapter’s index, m_s=√3V_ref/V_dc, so

A symmetrical sequence distributes the zero time equally at the beginning and end, for example 000–V1–V2–111–V2–V1–000. This reduces certain low-order errors and balances switching transitions. The exact sequence can be modified for reduced switching, clamping, common-mode reduction, or thermal balancing.

4.3 Worked example: dwell times

Let V_dc=600 V, f_s=10 kHz, m_s=0.8, and θ=20°. Then T_s=100 μs. Since sin(60°−20°)=sin40°≈0.6428 and sin20°≈0.3420,

The result is physically admissible because all dwell times are non-negative and sum to T_s.

4.4 SVPWM does not automatically amplify a fixed command

SVPWM and third-harmonic injection improve DC-bus utilization by allowing a larger reference before entering overmodulation. If the same physical fundamental reference is commanded at the same DC voltage, changing from SPWM to SVPWM does not automatically increase that fundamental by 15.5%. An increase occurs only if the reference is renormalized or increased into the additional available linear range. This distinction is essential in comparing controllers and interpreting experimental data.

5. Harmonics, ripple, and output filters

The output voltage contains the desired fundamental, switching sidebands, dead-time distortion, sampling effects, and common-mode components. In a motor, the phase inductance provides filtering. In a grid converter, an L or LCL filter is usually required.

For an inductor carrying approximately sinusoidal current, the switching ripple over a short interval is estimated from

For a two-level leg with an applied voltage error bounded approximately by V_dc, a conservative triangular-ripple estimate is

The coefficient depends on modulation instant and switching sequence; therefore this is a design estimate, not a universal exact value. The required inductance for a specified peak-to-peak ripple is approximately

Worked example: filter inductance

For V_dc=800 V, f_s=20 kHz, and allowable ripple Δi_pp,max=4 A,

A practical design selects a higher nominal value after accounting for tolerance, saturation, switching-state dependence, and control bandwidth. The inductor’s copper and core losses must then be checked.

For a simple L filter, the corner frequency is

only when a damping resistance R is intentionally used as the relevant first-order model. For an ideal LC filter, the natural frequency is instead

An undamped LCL filter has resonances and requires damping, either passive or active. Filter design must keep the resonance well above the fundamental and sufficiently below the switching frequency, while satisfying grid-code attenuation and control-stability requirements.

6. Semiconductor stress and thermal design

In a two-level VSI, each blocking device must normally withstand at least the DC-link voltage. Engineering design adds a voltage margin for overshoot caused by stray inductance:

The current rating must include RMS current, peak current, short-circuit behavior, overload duration, and diode reverse-recovery effects. A device’s average loss can be approximated by

For a simplified MOSFET model,

For an IGBT-like constant-drop approximation,

Switching loss is commonly estimated from measured or datasheet energy per transition:

The thermal path is represented by a resistance network. For a steady-state junction-temperature estimate,

or, with a heatsink,

where the resistances are junction-to-case, case-to-sink, sink-to-ambient, and their units are °C/W.

Worked example: thermal feasibility

Suppose a switch dissipates 90 W, ambient temperature is 40 °C, and the thermal resistances are R_θJC=0.20, R_θCS=0.10, and R_θSA=0.35 °C/W. Then

If the specified maximum junction temperature is 150 °C, the steady-state thermal margin is 51.5 °C. Transient thermal impedance, altitude, airflow blockage, capacitor heating, and unequal phase loading must still be evaluated.

7. Dead time and nonideal switching

Dead time prevents shoot-through but changes the average pole voltage. Define the voltage error explicitly as

For a sufficiently inductive load and a simple complementary-leg model, the average error is approximately

where t_d is dead time, T_s is switching period, and sgn(i_phase) is +1 for positive current and −1 for negative current. The sign follows the stated actual-minus-commanded convention; reversing the error definition reverses the sign. Device turn-on and turn-off delays, diode forward drops, and current zero crossings make the real error more complex.

Dead-time compensation estimates current polarity and advances or retards the commanded pulse. Near a current zero crossing, polarity detection is uncertain, so compensation can introduce noise or pulse distortion. Minimum-pulse suppression and timer quantization also matter in digital controllers.

Common-mode voltage is another important nonideality. The three pole voltages may produce a common-mode component that drives bearing currents, motor-shaft voltage, insulation stress, and conducted electromagnetic interference. Appropriate zero-vector selection, common-mode-reduced PWM, output filtering, and bearing protection can mitigate these effects.

8. Overmodulation and control implementation

In linear PWM, the average reference is reproduced without saturation. When the reference reaches the boundary of the feasible voltage hexagon, T₀ approaches zero. Beyond this point, dwell times must be limited and the waveform enters overmodulation, gradually approaching six-step operation. The fundamental increases, but low-order harmonics and torque ripple also increase.

A digital implementation normally performs these operations:

1. Sample currents, DC voltage, and position or phase angle.
2. Transform three-phase quantities into αβ or dq coordinates.
3. Generate a voltage reference from the current or speed controller.
4. Determine the sector and calculate T₁, T₂, and T₀.
5. Convert dwell times into timer compare values.
6. Apply dead time, interlocks, minimum-pulse rules, and fault handling.
7. Verify current limits, desaturation, DC-link protection, and safe shutdown.

Sampling should be synchronized with the PWM carrier to reduce measurement noise and delay uncertainty. Computational delay affects the achievable current-loop bandwidth and may require prediction or delay compensation.

9. Comparative evaluation of modulation methods

No modulation method is universally optimal. The choice is a multi-objective engineering decision involving efficiency, acoustic noise, current ripple, EMI, thermal distribution, computational resources, and grid or motor requirements.

10. Illustrative application case: 400 V battery inverter for a motor drive

Background

Consider a battery-fed three-phase, two-level inverter with a measured DC-link voltage of 400 V, switching at 10 kHz, and a commanded SVPWM index m_s=0.9. The motor phase current is approximately 20 A RMS. The design team must determine voltage capability, ripple, thermal feasibility, and dead-time implications.

Analysis

With the SVPWM convention defined in this chapter,

This is the commanded fundamental capability in the linear range. It is not 15.5% greater merely because SVPWM is used. The current-ripple estimate for a 2 mH phase inductance is

If the allowable design ripple is 4 A, the inductance estimate becomes

Suppose one switch has estimated conduction loss 35 W and switching loss 25 W. With ambient temperature 45 °C and total junction-to-ambient resistance 0.60 °C/W,

The calculation appears acceptable, but it excludes transient overload, unequal losses, thermal-interface variation, and capacitor temperature rise. If t_d=1 μs, then the approximate dead-time voltage-error magnitude is

with direction determined by −sgn(i_phase) under the defined convention.

Approach and outcome

The design should use synchronized sampling, a validated SVPWM sector algorithm, dead-time compensation with zero-crossing protection, a 2.5 mH or otherwise validated filter inductance, and thermal measurements on all phase-leg devices. Laboratory tests should measure line-voltage spectrum, current ripple, common-mode voltage, switching overshoot, and junction-temperature proxies. The outcome is not simply a selected modulation index; it is a verified operating envelope in which voltage, current, thermal, EMI, and protection limits are simultaneously satisfied.

Learning points

1. Voltage utilization claims are meaningful only when the modulation-index convention is stated.
2. A filter estimate must be checked against the actual switching sequence and control bandwidth.
3. Dead time is both a protection requirement and a waveform-distortion mechanism.
4. Semiconductor selection requires electrical, thermal, transient, and fault analysis together.

11. Challenges, safety, and contemporary developments

High-frequency switching creates electromagnetic interference and potentially hazardous leakage currents. DC-link capacitors remain charged after shutdown; safe discharge, interlocked enclosures, insulation coordination, creepage, clearance, and documented lockout procedures are essential. Grid-connected products must meet applicable electromagnetic-compatibility, protection, anti-islanding, and power-quality standards.

Wide-bandgap SiC and GaN devices enable higher switching frequency, lower switching energy, and smaller filters, but they impose stricter layout, gate-loop, insulation, dv/dt, and measurement requirements. AI and machine learning are increasingly used for thermal prediction, fault diagnosis, parameter estimation, and modulation optimization. They should supplement, not replace, deterministic protection and physically validated control laws. Training-data bias, explainability, cybersecurity, and fail-safe behavior are important governance issues in safety-critical power converters.

Best practice is to validate the complete chain: analytical model, circuit simulation, processor-in-the-loop, hardware-in-the-loop, low-voltage prototype, rated-power test, fault test, and compliance test. Measurements must use probes with adequate common-mode rating and bandwidth; otherwise switching-node results can be misleading.

Chapter Summary

Inverters synthesize AC from DC by controlling semiconductor switching states. Two-level VSIs produce six active and two zero space vectors. SPWM is simple and robust, while third-harmonic injection and SVPWM extend the linear voltage range. SVPWM dwell times are determined from the reference magnitude and sector angle, and the zero-vector time must remain non-negative in linear operation.

The modulation-index convention must always be stated. In this chapter, m_s=√3V_ref,pk/V_dc and the linear limit is one. SVPWM improves the maximum available reference range; it does not automatically increase a fixed commanded fundamental. Ripple, semiconductor stress, switching and conduction losses, thermal resistance, dead time, common-mode voltage, and filter resonance must be considered in practical design. Reliable inverter engineering combines analytical calculation with simulation, measurement, protection design, thermal verification, and standards compliance.

Key Terms

Inverter: Static converter that produces AC from DC.

Voltage-source inverter: Inverter supplied by a stiff DC voltage.

Current-source inverter: Inverter supplied by a nearly constant DC current.

Switching function: Mathematical variable representing the state of a converter leg.

DC link: Energy-storage and distribution interface between source and inverter.

SPWM: PWM obtained by comparing a sinusoidal reference with a carrier.

Modulation index: Ratio defining the requested reference magnitude relative to a carrier or DC-bus base.

Space vector: Complex representation of balanced three-phase voltage or current.

SVPWM: PWM method that combines adjacent inverter voltage vectors and zero vectors.

Dwell time: Duration for which a selected switching vector is applied.

Zero vector: Inverter state producing zero line-to-line voltage in a two-level VSI.

Overmodulation: Operation beyond the linear voltage-synthesis region.

Dead time: Deliberate delay preventing simultaneous conduction in one inverter leg.

Common-mode voltage: Voltage common to all output terminals relative to a reference.

Switching loss: Energy dissipated during semiconductor transitions multiplied by switching frequency.

Conduction loss: Loss caused by voltage drop or resistance during current conduction.

Thermal resistance: Temperature rise per unit dissipated power.

LCL filter: Grid filter composed of two inductors and a capacitor.

Wide-bandgap semiconductor: SiC or GaN device technology enabling fast, efficient switching.

Review Questions

Short Answer Questions

1. Why are antiparallel diodes used in a voltage-source inverter?
2. Define the switching-frequency ratio m_f.
3. What are the six active and two zero states of a two-level three-phase inverter used for?
4. Why is dead time inserted in complementary gate signals?
5. State the SVPWM modulation-index convention used in this chapter.

Long Answer Questions

1. Derive the fundamental line-voltage relationship for three-phase sinusoidal PWM.
2. Explain SVPWM sector selection and derive the expressions for T₁, T₂, and T₀.
3. Compare SPWM, third-harmonic injection, SVPWM, and discontinuous PWM from efficiency and harmonic perspectives.
4. Explain the electrical and thermal stresses experienced by a power semiconductor in a two-level VSI.
5. Discuss the causes, consequences, and compensation of dead-time distortion.

Analytical / Application Questions

1. A 600 V DC link operates at 12 kHz with m_s=0.75 and reference angle 35°. Calculate T₁, T₂, and T₀.
2. A converter has 500 V DC link, 16 kHz switching frequency, and allowable peak-to-peak ripple of 3 A. Estimate the inductance using the conservative ripple expression in this chapter.
3. A switch dissipates 75 W with R_θJC=0.18, R_θCS=0.08, and R_θSA=0.40 °C/W at 35 °C ambient. Calculate junction temperature and assess a 150 °C limit.

Multiple Choice Questions with Answers

Question 1

Under the SVPWM convention used in this chapter, what is the linear modulation limit?

A. m_s = 0.5

B. m_s = 1

C. m_s = √3

D. m_s = 2

Correct Answer: B. m_s = 1

Question 2

For V_dc = 600 V, f_s = 10 kHz, m_s = 0.8 and θ = 20°, what is T_1 approximately?

A. 21.2 μs

B. 27.4 μs

C. 51.4 μs

D. 80.0 μs

Correct Answer: C. 51.4 μs

Question 3

The approximate dead-time error Δv in this chapter is defined as:

A. commanded voltage minus actual voltage

B. actual voltage minus commanded voltage

C. peak voltage divided by RMS voltage

D. switching voltage divided by carrier voltage

Correct Answer: B. actual voltage minus commanded voltage

Question 4

Which condition indicates linear SVPWM operation?

A. T_0 < 0

B. T_1 + T_2 > T_s

C. T_0 ≥ 0

D. The reference lies outside the hexagon

Correct Answer: C. T_0 ≥ 0

Question 5

For V_dc = 800 V, f_s = 20 kHz and allowable ripple of 4 A, the conservative inductance estimate is:

A. 0.25 mH

B. 1.0 mH

C. 2.5 mH

D. 10 mH

Correct Answer: C. 2.5 mH

Question 6

Which relationship gives the chapter’s SVPWM fundamental line-to-line RMS voltage?

A. V_LL,1,rms = m_sV_dc

B. V_LL,1,rms = m_sV_dc/√2

C. V_LL,1,rms = m_sV_dc/2

D. V_LL,1,rms = √2m_sV_dc

Correct Answer: B. V_LL,1,rms = m_sV_dc/√2

Question 7

If a switch dissipates 90 W and total thermal resistance is 0.65 °C/W at 40 °C ambient, its estimated junction temperature is:

A. 58.5 °C

B. 98.5 °C

C. 130 °C

D. 148.5 °C

Correct Answer: B. 98.5 °C

Question 8

What is the principal purpose of dead time?

A. Increase the DC-link voltage

B. Prevent shoot-through in one inverter leg

C. Eliminate all switching losses

D. Raise the fundamental frequency

Correct Answer: B. Prevent shoot-through in one inverter leg

Question 9

Which device stress is directly increased by stray inductance during rapid current change?

A. Voltage overshoot

B. Fundamental frequency

C. Carrier amplitude

D. Thermal resistance of the heatsink

Correct Answer: A. Voltage overshoot

Question 10

Why does SVPWM not automatically increase a fixed commanded fundamental by approximately 15.5%?

A. It operates only with DC current sources

B. It changes the motor inductance

C. It extends the allowable reference range but does not alter an unchanged reference

D. It eliminates the DC link

Correct Answer: C. It extends the allowable reference range but does not alter an unchanged reference