Digital Implementation, Simulation and Validation

Introduction and context

Power-electronic converters are increasingly controlled by microcontrollers, digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and programmable logic controllers. Digital control enables sophisticated modulation, protection, communication, parameter adaptation, and condition monitoring. It also introduces sampling, computation, quantization, scheduling, transport delay, numerical saturation, and software-verification issues that do not appear in the same form in an analog controller.

A digitally implemented power-electronic controller is therefore a sampled-data cyber-physical system. Its performance depends jointly on the converter, sensors, power stage, computational hardware, embedded software, and validation process. A continuous-time design that is stable in simulation may become poorly damped or unstable after discretization and implementation delay. Conversely, a carefully designed digital controller can provide predictable performance over a wide operating range.

This chapter develops a systematic workflow from mathematical modelling to real-time validation. Particular attention is given to exact zero-order-hold (ZOH) discretization, delay analysis, fixed-point effects, simulation fidelity, and reproducible validation.

Learning objectives

By the end of this chapter, the reader should be able to:

1. formulate sampled-data models of power-electronic systems;
2. derive exact ZOH discrete models for linearized plants;
3. select sampling frequency, computational delay, and numerical precision appropriately;
4. implement discrete PI control, saturation, and anti-windup without causal ambiguity;
5. analyse z-domain stability and delay effects;
6. distinguish averaged, switching, real-time, and hardware-in-the-loop simulation;
7. quantify finite-word-length and quantization effects; and
8. construct a defensible simulation-to-hardware validation plan.

1. Digital control as a sampled-data system

Consider a continuous plant represented near an operating point by

where x is the state vector, u is the control input, y is the measured output, and A, B, C, and D have compatible dimensions. In a digitally controlled converter, the measurement is sampled at t = kT_s, where T_s is the sampling period. The digital algorithm calculates a command, which is commonly held constant by a zero-order hold until the next update.

The complete loop may contain the following delays:

• sensor conditioning and analogue-to-digital conversion;
• interrupt latency and task scheduling;
• numerical computation;
• pulse-width-modulator update delay; and
• power-stage response and measurement filtering.

The effective delay should be represented explicitly when it is a significant fraction of T_s. A model based only on the continuous plant and an ideal controller is insufficient for final validation.

Sampling and aliasing

A periodic signal above half the sampling frequency can be aliased into a lower apparent frequency. The Nyquist frequency is f_s/2, where f_s = 1/T_s. An anti-alias filter is therefore normally required before the ADC. In a converter, switching ripple is often intentionally attenuated by analogue filtering, synchronized sampling, digital filtering, or a combination of these methods.

Sampling frequency is not selected from the switching frequency alone. It must also provide adequate bandwidth for the controlled dynamics and enough computation time. A common engineering starting point is to place the closed-loop bandwidth well below the sampling frequency, but the acceptable ratio depends on delay, modulation method, plant phase, and robustness requirements. It must be verified rather than treated as a universal rule.

2. Exact ZOH discretization

For a linear continuous model with input held constant over each interval [kT_s,(k+1)T_s), the exact discrete model is

where

and

This result is exact for the stated linear model and ZOH assumption. If A is nonsingular, an equivalent expression is

The integral form remains valid when A is singular. A numerically robust computational method is to calculate the matrix exponential of the augmented matrix

where the block dimensions are chosen consistently.

First-order example

For the plant

with τ > 0, the state is y and the exact ZOH model is

where

For K = 2, τ = 1 ms, and T_s = 0.1 ms, T_s/τ = 0.1, so a ≈ 0.90484 and b ≈ 0.19033. The discrete pole is 0.90484, inside the unit circle, as expected from the stable continuous pole −1/τ.

The corresponding pulse-transfer function, with zero initial conditions, is

The z-domain form is especially useful for analysing computational delay, closed-loop poles, and discrete compensator design.

Discretizing a controller

A continuous PI controller may be written as

where K_p has units of controller-output/error and K_i has units of controller-output/(error·s). Under forward Euler integration,

and the preliminary command is

This is simple but not always the best frequency-domain approximation. Tustin’s method replaces the integral by

The choice must be consistent with the controller design and implementation timing. Exact plant discretization does not make an approximate controller discretization exact.

3. z-domain stability, delay, and robustness

A discrete-time linear system is asymptotically stable if and only if every closed-loop pole satisfies

For a plant G(z), controller C(z), and feedback sign convention with negative feedback, the closed-loop characteristic equation is

where H(z) represents the measurement path. A one-sample computational delay contributes a factor z⁻¹. It increases system order and adds phase lag on the unit circle: at z = e^(jωT_s), the delay has phase −ωT_s radians.

For the first-order plant G(z) = b z⁻¹/(1 − a z⁻¹), proportional control C(z) = K_c, and one additional sample delay, the characteristic equation is

Multiplication by z² gives

The delay has changed a first-order closed-loop relation into a second-order relation. Stability can be tested by calculating both roots or by applying the Jury criterion. For a monic polynomial z² + α₁z + α₂, the second-order Jury conditions are

These conditions apply to real coefficients and a second-order polynomial; they should not be applied indiscriminately to higher-order or complex-coefficient systems.

For the delayed example, α₁ = −a and α₂ = K_c b. Consequently, the conditions become

For positive a, b, and K_c, the restrictive upper condition is K_c b < 1, while the other inequalities must still be checked for the actual signs and operating point. This illustrates why delay cannot be appended informally after a controller has been tuned.

Delay modelling choices

A delay of an integer number of samples is represented exactly by z⁻ᴺ. A fractional delay requires an approximation, such as a fractional-delay filter, or a higher-rate simulation. In switching simulations, the effective delay may vary with PWM update convention: trailing-edge, centre-aligned, and double-update PWM do not have identical timing. The implemented timing diagram should therefore be treated as part of the plant model.

4. Digital implementation of PI control and anti-windup

Saturation occurs when the demanded command exceeds the allowable modulator or actuator range. Let u_min ≤ u[k] ≤ u_max. A robust implementation separates the preliminary unsaturated command from the applied command.

At sample k, execute the following causal sequence:

1. acquire and scale the measurement;
2. calculate e[k] = r[k] − y[k];
3. calculate a preliminary integrator value I₀[k];
4. calculate u₀[k] using I₀[k];
5. saturate u₀[k] to obtain u[k];
6. apply the anti-windup correction to obtain I[k]; and
7. store I[k] for the next sample.

For conditional integration, integration is disabled when the actuator is saturated in the direction that would increase saturation. A back-calculation form is

Here K_aw has units s⁻¹ when I and u have the same controller-output units. The formula is causal because u₀[k] is calculated before the saturation and correction; it does not use an ambiguously simultaneous value of I[k]. If the integrator state has different scaling, the units of K_aw must be adjusted accordingly.

Correctly scaled worked example

Assume a current loop with reference r = 2.0 A and measured current y = 0.5 A. Let the controller output be a dimensionless duty ratio, with limits 0 ≤ u ≤ 1. Choose K_p = 0.08 duty/A, K_i = 400 duty/(A·s), T_s = 50 μs, and an already stored integrator state I[k−1] = 0.20 duty. Use forward Euler integration and K_aw = 2000 s⁻¹.

The error is e[k] = 1.5 A. The integral increment is

Thus I₀[k] = 0.20 + 0.03 = 0.23 duty. The proportional term is 0.08 duty/A × 1.5 A = 0.12 duty, so

Because 0.35 lies within [0,1], u[k] = 0.35 duty and the back-calculation term is zero. Therefore I[k] = 0.23 duty. Notice that K_i is not written as merely 400 s⁻¹: because the error is expressed in amperes and the output is a dimensionless duty ratio, its correct unit is duty/(A·s). If the error had first been normalized by a base current, K_i could instead be expressed in s⁻¹ relative to that normalized error.

5. Finite-word-length and numerical effects

A fixed-point implementation represents a real quantity by a finite number of bits. If a signed Qm.n format has n fractional bits and no overflow, the quantization step is

in the chosen full-scale unit. Rounding error is commonly bounded by ±Δ/2, although truncation has a biased error in many implementations.

For a sampled measurement y_q[k] = y[k] + q[k], an ideal rounding model treats q[k] as approximately uniform over [−Δ/2, Δ/2], giving

This model is useful for estimation but is not exact for deterministic limit cycles, correlated signals, overload, or quantization near a deadband.

Quantization amplification in an integrator

An integrator accumulates error. With quantized error q[k], the accumulated perturbation in a forward-Euler integrator is approximately

Without leakage, a nonzero mean quantization error can drift until saturation. Even zero-mean quantization can produce idle oscillations through nonlinear switching and PWM resolution. Practical protections include sufficient accumulator width, saturation-safe arithmetic, conditional integration, integrator leakage where acceptable, and explicit deadband design.

Numerical example

Suppose a normalized duty command uses Q1.15, so Δ = 2⁻¹⁵ ≈ 3.0518×10⁻⁵. The maximum rounding error is approximately 1.5259×10⁻⁵ duty. If a proportional gain is 0.25 duty per normalized error, the corresponding command error from one quantized measurement step is at most approximately

for that single operation. This small value does not prove negligible system impact: PWM resolution, ADC noise, accumulated integral error, and limit-cycle dynamics must also be evaluated.

Overflow is more dangerous than ordinary quantization. Every multiplication and accumulation should have a stated scaling rule, intermediate width, saturation behaviour, and overflow test. The implementation should not rely on undefined processor wraparound.

6. Simulation hierarchy

Different simulation models answer different engineering questions.

Averaged models are appropriate when switching-frequency details are not the object of study and the averaging assumptions hold. They are not sufficient for validating current spikes, diode reverse recovery, dead-time distortion, common-mode voltage, or protection triggered within a switching interval.

Solver and event considerations

Switching models contain discontinuities. Variable-step solvers can locate switching events accurately but may not represent deterministic real-time execution. Fixed-step solvers are closer to embedded execution and HIL, but the step must resolve the switching events and control update schedule. Numerical tolerances, algebraic loops, initialization, and solver interpolation can materially affect results.

A credible simulation report states the model equations, parameter values, initial conditions, solver type, step size, tolerances, PWM timing, sampling instant, and stopping criteria. Merely reporting a plotted waveform is not reproducible validation.

7. Validation methodology

Validation should proceed from low risk and high observability toward full power operation.

Model verification

Verification asks whether the model and software were implemented correctly. Examples include:

• dimensional and sign checks;
• comparison of analytical and numerical step responses;
• limiting-case tests, such as zero load or zero reference;
• conservation checks for energy and power;
• regression tests for controller code;
• comparison of floating-point and fixed-point outputs; and
• code-coverage and fault-injection tests.

Experimental validation

Validation asks whether the model adequately represents the physical system. The comparison should use common inputs, synchronized time bases, calibrated sensors, and uncertainty bounds. Useful metrics include the root-mean-square error

and maximum absolute error

These metrics must be interpreted with bandwidth, sensor accuracy, noise, and transient alignment in mind. A low RMSE can conceal a serious peak error if most samples are at steady state.

A useful validation matrix includes operating point, reference step, load disturbance, input-voltage disturbance, start-up, shutdown, saturation, sensor fault, communication loss, and protection response. Each test should specify acceptance criteria before the experiment.

8. Applied case: digitally controlled DC–DC converter

The following is an illustrative engineering case, not a report of a particular commercial product.

Background and problem

A synchronous buck converter supplies a regulated 12 V bus from a 24 V source. It operates at 100 kHz and must maintain output voltage during load changes. A digital controller samples voltage once per switching period and updates a duty command through a centre-aligned PWM module. The design team initially tuned a continuous PI controller using an averaged model, but hardware testing showed overshoot and intermittent oscillation.

Analysis

The first investigation identified a one-sample effective computational/PWM delay. The team discretized the linearized averaged plant using exact ZOH rather than forward Euler and included the delay as z⁻¹. The measured voltage was filtered, and the filter was included in H(z). Root-locus and pole calculations showed that the original gain placed a complex pole pair close to the unit circle after the delay was included.

A second investigation used fixed-point emulation. The ADC scale, duty resolution, and integrator accumulator were reproduced exactly. The emulation revealed a small limit cycle near the reference caused by the combined voltage quantization and PWM resolution. The limit cycle was not visible in floating-point averaged simulation.

Approach and solution

The revised design used:

1. exact-ZOH plant discretization at the actual sampling period;
2. a controller design that explicitly included the measured delay;
3. a wider accumulator than the output word length;
4. saturation-safe arithmetic and back-calculation anti-windup;
5. synchronized sampling away from the largest switching transient;
6. switching-model tests for dead time and ripple; and
7. processor-in-the-loop and HIL regression tests before energizing the power stage.

The PWM update timing was documented as part of the control specification. The acceptance tests included line steps, load steps, start-up, reference changes, saturation recovery, and sensor-disconnection response.

Outcome and learning points

The revised model predicted the measured settling trend more accurately because it represented delay and filtering. Fixed-point emulation predicted the observed small ripple, allowing the team to distinguish a quantization limit cycle from an unstable pole. The central lesson is that validation is not a final plotting exercise: sampling, timing, numerical representation, and protection logic must be validated as an integrated system.

9. Professional, safety, and governance considerations

Power-electronic software can command hazardous voltage, current, and stored energy. Laboratory validation requires isolation, pre-charge procedures, emergency shutdown, current limiting, guarded test areas, and documented competence. Protection functions should not depend solely on a non-real-time supervisory task; hardware over-current and over-voltage paths are often required.

Configuration control is essential. The tested binary, compiler version, parameter set, calibration data, schematic, model revision, and test logs should be traceable. Cybersecurity is also relevant where converters communicate over networks: authenticated firmware, controlled access, secure update procedures, and fail-safe behaviour reduce the risk of malicious or accidental commands.

AI-assisted code or model generation may accelerate development, but generated material requires independent review, unit testing, static analysis, and hardware-safe qualification. It must not be treated as evidence of correctness.

10. Contemporary developments and best practice

Current developments include automated code generation, FPGA-based parallel control, event-triggered computation, digital twins, wide-bandgap-device models, and machine-learning-assisted fault diagnosis. These technologies are useful only when their timing, uncertainty, interpretability, and failure modes are understood.

Recommended practice is to:

• define sampling and PWM timing before controller tuning;
• use exact ZOH discretization where the plant is linear and input-hold assumptions apply;
• include measured and computational delays explicitly;
• specify units and scaling for every controller state;
• separate preliminary and saturated commands in anti-windup code;
• emulate finite precision before hardware tests;
• use model, software, processor, HIL, and power-stage tests in sequence;
• preserve test artefacts and acceptance criteria; and
• report uncertainty, limitations, and operating boundaries honestly.

Chapter Summary

Digital power-electronic control is a sampled-data problem in which sampling, holding, delay, computation, quantization, and switching interact with the physical converter. Exact ZOH discretization gives Φ = e^(AT_s) and Γ = ∫₀^(T_s)e^(Aτ)B dτ for a linear plant under held input. Discrete stability requires all closed-loop poles to lie inside the unit circle, and computational delay must be represented because it adds phase lag and system order. PI implementation requires dimensionally consistent gains and a clearly causal anti-windup sequence based on the preliminary command. Finite-word-length effects can create overflow, drift, and limit cycles, particularly in integrators. Averaged, switching, real-time, and power-HIL simulations serve different purposes. Defensible validation combines analytical checks, software tests, fixed-point emulation, synchronized experiments, quantitative error metrics, safety controls, and configuration traceability.

Key Terms

Sampled-data system: A system in which continuous physical dynamics interact with discrete measurements and control updates.

Zero-order hold: A device or assumption that holds the computed input constant between samples.

Exact ZOH discretization: Conversion of a continuous linear model to its exact discrete equivalent under held input.

Sampling period: Time between successive digital measurements or controller updates.

Computational delay: Time or sample displacement caused by execution, scheduling, and PWM update processes.

Pulse-transfer function: A discrete-time transfer-function representation using the z-transform.

Unit circle: The locus |z| = 1 in the complex z-plane; discrete poles must lie inside it for asymptotic stability.

Anti-windup: A method that prevents integrator accumulation during actuator saturation.

Back-calculation: Anti-windup method that feeds the difference between saturated and preliminary commands into the integrator.

Finite-word length: The limited numerical precision of a digital representation.

Quantization: Mapping a continuous-valued numerical quantity to discrete representable levels.

Limit cycle: Persistent bounded oscillation caused by nonlinearities such as quantization or dead zones.

Averaged model: A model representing mean behaviour over a switching interval or cycle.

Switching model: A model that explicitly represents semiconductor switching states and events.

Hardware-in-the-loop: Real-time simulation in which actual control hardware interacts with a simulated plant.

Model verification: Demonstration that equations and software implement the intended model correctly.

Experimental validation: Assessment of how accurately a model represents physical behaviour.

Regression test: A repeatable test used to detect unintended changes after modifications.

Configuration control: Formal tracking of software, parameters, models, hardware, and test revisions.

Review Questions

Short Answer Questions

1. What assumptions are required for exact ZOH discretization?
2. Why does a one-sample computational delay affect discrete stability?
3. Distinguish the preliminary command u₀[k] from the saturated command u[k].
4. What is the purpose of an anti-alias filter?
5. Why can an integrator be especially sensitive to finite-word-length effects?

Long Answer Questions

1. Derive the exact discrete model of a continuous linear state-space system under ZOH and explain the role of Φ and Γ.
2. Explain how sampling, PWM timing, measurement filtering, and computational delay should be represented in a digital converter model.
3. Compare averaged, switching, processor-in-the-loop, and HIL simulation in terms of purpose, fidelity, and limitation.
4. Develop a causal PI controller with saturation and back-calculation anti-windup, including units and execution order.
5. Explain a complete verification and experimental-validation workflow for a digitally controlled converter.

Analytical / Application Questions

1. A first-order plant has K = 1.5, τ = 2 ms, and T_s = 0.2 ms. Derive its exact ZOH coefficients and determine its discrete open-loop pole.
2. For a Q1.15 duty representation, calculate the quantization step and maximum rounding error, then discuss whether that error alone is sufficient to predict output ripple.
3. A controller exhibits oscillation only after code deployment. Construct a diagnostic plan that separates delay-induced instability, fixed-point limit cycles, incorrect scaling, and PWM timing error.

Multiple Choice Questions with Answers

Question 1

For a linear state model under a zero-order hold, which expression is the exact discrete state-transition matrix?

A. Φ = A T_s

B. Φ = e^(A T_s)

C. Φ = I + B T_s

D. Φ = e^(B T_s)

Correct Answer: B. Φ = e^(A T_s)

Question 2

A stable discrete-time closed loop requires which pole condition?

A. |z_i| > 1 for every pole

B. Re(z_i) < 0 for every pole

C. |z_i| < 1 for every pole

D. Im(z_i) = 0 for every pole

Correct Answer: C. |z_i| < 1 for every pole

Question 3

In causal back-calculation anti-windup, which command should be compared with the saturated command?

A. The next sample's command

B. The preliminary unsaturated command u₀[k]

C. The reference signal alone

D. The previous measured output

Correct Answer: B. The preliminary unsaturated command u₀[k]

Question 4

A duty-ratio output is dimensionless and the error is measured in amperes. What are the units of K_i in a PI controller?

A. A/(duty·s)

B. duty·A·s

C. duty/(A·s)

D. s/duty

Correct Answer: C. duty/(A·s)

Question 5

For a Q1.15 representation, the quantization step is approximately:

A. 3.0518×10⁻⁵

B. 1.5259×10⁻⁵

C. 6.5536×10⁴

D. 0.5

Correct Answer: A. 3.0518×10⁻⁵

Question 6

What factor represents an integer one-sample delay in the z-domain?

A. z

B. z²

C. 1 + z

D. z⁻¹

Correct Answer: D. z⁻¹

Question 7

Which simulation is most directly intended to test an actual controller against a real-time simulated plant?

A. A hand calculation

B. Hardware-in-the-loop simulation

C. A static schematic review

D. An offline parameter table

Correct Answer: B. Hardware-in-the-loop simulation

Question 8

For τ = 1 ms and T_s = 0.1 ms, the exact ZOH pole of a first-order plant is approximately:

A. 0.10000

B. 0.50000

C. 0.90484

D. 1.10517

Correct Answer: C. 0.90484

Question 9

Which statement about quantization noise is most accurate?

A. It always has zero mean and cannot create oscillations

B. It is exactly independent of the signal in every implementation

C. It can contribute to limit cycles, especially with nonlinearities and integrators

D. It eliminates the need for sensor filtering

Correct Answer: C. It can contribute to limit cycles, especially with nonlinearities and integrators

Question 10

Which activity primarily addresses model verification rather than experimental validation?

A. Comparing a predicted waveform with a calibrated oscilloscope measurement

B. Testing conservation and limiting cases in the equations

C. Measuring converter efficiency on the laboratory prototype

D. Comparing transient settling time between model and hardware

Correct Answer: B. Testing conservation and limiting cases in the equations