Nanoscale MOSFETs and CMOS Scaling

Introduction

Metal–oxide–semiconductor field-effect transistors (MOSFETs) have remained the fundamental switching devices of digital integrated circuits because their electrostatic control, manufacturability, and complementary operation support very high density and low static power. As transistor dimensions have entered the nanometre regime, however, the assumptions behind long-channel MOSFET theory have progressively failed. The source and drain electric fields extend into the channel, the gate loses exclusive control of the channel potential, tunnelling currents increase, process variations become comparable with nominal dimensions, and power density constrains further voltage scaling.

Modern CMOS scaling is therefore not simply geometric shrinkage. It is a coordinated strategy involving device architecture, materials, process integration, circuit design, interconnect technology, and system-level power management. Planar bulk MOSFETs have been supplemented or replaced by silicon-on-insulator (SOI), FinFET, gate-all-around (GAA), nanosheet, and complementary FET (CFET) structures. Each architecture improves electrostatic control in a different way while introducing fabrication, thermal, parasitic, or reliability challenges.

This chapter develops models for short-channel effects, leakage, variability, and nanoscale electrostatics. It then compares major transistor architectures and examines practical scaling strategies and research directions.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain why long-channel MOSFET models become inaccurate at nanometre dimensions.

2. Model and interpret threshold-voltage roll-off, drain-induced barrier lowering, velocity saturation, subthreshold conduction, and gate leakage.

3. Relate subthreshold swing and electrostatic scaling length to gate control.

4. Analyze sources of variability and their circuit consequences.

5. Compare bulk CMOS, SOI, FinFET, GAA, nanosheet, and CFET architectures.

6. Evaluate technology choices using performance, power, density, manufacturability, and reliability criteria.

7. Apply nanoscale device concepts to a realistic design scenario.

1. From Long-Channel to Nanoscale MOSFETs

For a long-channel nMOS transistor in strong inversion and saturation, the ideal square-law expression is

\[

I_D=\frac{1}{2}\mu_n C_{ox}\frac{W}{L}(V_{GS}-V_T)^2,

\]

where \(I_D\) is drain current, \(\mu_n\) is carrier mobility, \(C_{ox}=\varepsilon_{ox}/t_{ox}\) is oxide capacitance per unit area, \(W\) and \(L\) are channel width and length, \(V_{GS}\) is gate-to-source voltage, and \(V_T\) is threshold voltage. The expression assumes gradual channel variation, constant mobility, negligible series resistance, and a channel sufficiently long that the drain field does not significantly affect the source-side barrier.

At short channel lengths, these assumptions fail. The drain field influences the entire channel, carriers approach a velocity limit, the effective channel length differs from the drawn length, and source/drain depletion regions occupy a substantial fraction of the device. A useful engineering view is that the transistor changes from a gate-controlled resistor or charge sheet into a two-dimensional electrostatic system whose behaviour depends on the source, drain, gate, body, and surrounding dielectric geometry.

The intrinsic delay of a logic gate is often approximated by

\[

t_p \approx \frac{C_L V_{DD}}{I_{on}},

\]

where \(t_p\) is propagation delay, \(C_L\) is effective load capacitance, \(V_{DD}\) is supply voltage, and \(I_{on}\) is on-state current. Scaling seeks to reduce capacitance and increase current, but lowering \(V_{DD}\) reduces dynamic power and also reduces available overdrive. The familiar dynamic-power relation is

\[

P_{dyn}=\alpha C_L V_{DD}^{2}f,

\]

where \(\alpha\) is switching activity and \(f\) is clock frequency. This quadratic voltage dependence made voltage scaling highly beneficial, but threshold-voltage and leakage constraints limit indefinite reduction of supply voltage.

2. Electrostatic Control and Short-Channel Effects

2.1 Threshold-voltage roll-off

In a long-channel device, the threshold voltage is primarily determined by gate work function, oxide capacitance, substrate doping, and body bias. As channel length decreases, source and drain depletion regions share a larger fraction of the channel charge. The gate consequently needs less voltage to induce inversion, producing threshold-voltage roll-off.

A simplified conceptual expression is

\[

\Delta V_T(L)=V_T(L)-V_{T,\mathrm{long}},

\]

where \(\Delta V_T\) is the short-channel shift and \(V_{T,\mathrm{long}}\) is the long-channel threshold. The precise dependence is technology-specific; it is not generally valid to assume a universal inverse-power law. Roll-off is controlled by junction depth, body thickness, channel doping, dielectric geometry, and source/drain design.

2.2 Drain-induced barrier lowering

Drain-induced barrier lowering (DIBL) occurs when increasing drain voltage lowers the source-to-channel potential barrier. The threshold voltage therefore decreases with drain voltage. A common extraction metric is

\[

\mathrm{DIBL}= -\frac{\Delta V_T}{\Delta V_{DS}},

\]

usually reported in mV/V, where the threshold values are measured at two drain biases using a specified constant-current criterion. The negative sign produces a positive DIBL value when threshold voltage decreases as \(V_{DS}\) increases.

DIBL increases off-state current and causes drain-voltage-dependent switching behaviour. It is reduced by improving gate control, reducing electrostatic scaling length, using shallower junctions, and employing fully depleted or multi-gate structures.

2.3 Subthreshold conduction and subthreshold swing

When \(V_{GS}<V_T\), a MOSFET is not ideally off. Diffusion of minority carriers produces approximately exponential current:

\[

I_D \approx I_0 \exp\left(\frac{V_{GS}-V_T}{nU_T}\right),

\]

where \(I_0\) is a technology- and bias-dependent prefactor, \(U_T=kT/q\) is the thermal voltage, \(k\) is Boltzmann’s constant, \(T\) is absolute temperature, \(q\) is electronic charge, and \(n\) is the subthreshold factor. The subthreshold swing is

\[

S=\frac{dV_{GS}}{d\log_{10} I_D}=n(\ln 10)U_T.

\]

For an ideal MOSFET at 300 K with perfect gate control, \(n=1\), giving approximately 60 mV/decade. In an ordinary device,

\[

n=1+\frac{C_{dep}}{C_{ox}},

\]

where \(C_{dep}\) is depletion capacitance per unit area. Interface traps add an additional capacitance-like contribution, so practical subthreshold swing is larger than the ideal thermal limit. At a fixed off-state specification, a larger swing requires a larger difference between on-state and off-state gate voltages, restricting low-voltage operation.

2.4 Velocity saturation and quasi-ballistic transport

In long channels, drift velocity approximately follows \(v=\mu E\). At high lateral electric field, carrier velocity approaches a saturation value \(v_{sat}\). A first-order current estimate in the velocity-saturated regime is

\[

I_D \approx W Q_{inv} v_{sat},

\]

where \(Q_{inv}\) is inversion charge per unit width. This dependence is closer to linear in gate overdrive than the long-channel square law. The equation is an engineering approximation and assumes a well-defined high-field region and neglects detailed injection and scattering effects.

When the channel becomes comparable with the mean free path, transport can become quasi-ballistic. The current is then limited partly by carrier injection at the source rather than by uniform channel scattering. Contact resistance, source/drain extensions, and quantum confinement become increasingly important.

2.5 Channel-length modulation and saturation behaviour

The effective channel shortens as drain voltage increases, causing a residual increase in saturation current. This is represented in a simple model by

\[

I_D \approx I_{Dsat}(1+\lambda V_{DS}),

\]

where \(\lambda\) is the channel-length-modulation parameter. At nanoscale dimensions, this parameter is strongly geometry-dependent, and the simple linear correction may be inadequate. Output conductance, drain resistance, and intrinsic gain \(g_m/g_{ds}\) generally degrade as scaling proceeds.

3. Electrostatic Scaling Length

A central design objective is to make the gate dominate the channel potential. The electrostatic scaling length, often denoted \(\lambda\), characterizes the distance over which a perturbation at a source or drain penetrates into the channel. Exact expressions depend on geometry and boundary conditions. For a planar fully depleted structure, a representative scaling relation has the form

\[

\lambda \propto \sqrt{t_{si}t_{ox}\frac{\varepsilon_{si}}{\varepsilon_{ox}}},

\]

where \(t_{si}\) is silicon body thickness, \(t_{ox}\) is oxide or equivalent oxide thickness, and \(\varepsilon_{si}\) and \(\varepsilon_{ox}\) are permittivities. The proportionality constant depends on the device structure. Good electrostatic integrity requires channel length to be several times larger than the relevant scaling length; the exact acceptable ratio depends on the target DIBL, swing, and leakage.

This relation explains several technology trends:

• thinner bodies improve gate control;
• thinner equivalent oxide thickness increases gate-to-channel coupling;
• high-permittivity dielectrics provide large capacitance without requiring physically ultrathin films;
• surrounding the channel with multiple gates reduces electrostatic penetration from the drain.

At very small dimensions, quantum confinement changes the carrier energy levels and effective threshold voltage. Quantum effects are especially important in thin fins, nanowires, and nanosheets. They must be included using quantum-corrected compact models or Schrödinger–Poisson and drift-diffusion/ballistic simulations when predictive accuracy is required.

4. Leakage Mechanisms

Nanoscale CMOS leakage is multidimensional and should not be treated as a single current.

4.1 Subthreshold leakage

Subthreshold leakage is the diffusion current described above. It increases with temperature, DIBL, threshold-voltage variation, and transistor width. Since a digital chip contains billions of devices, even a small per-device off-current can create substantial standby power.

4.2 Gate dielectric tunnelling

If the physical dielectric is extremely thin, electrons and holes can tunnel through it. Replacing SiO₂ with a high-\(k\) dielectric increases physical thickness at a similar equivalent oxide thickness (EOT), reducing direct tunnelling. EOT is commonly expressed as

\[

\mathrm{EOT}=t_{phys}\frac{k_{SiO_2}}{k_{dielectric}},

\]

where \(t_{phys}\) is physical dielectric thickness and \(k\) denotes relative permittivity. This relation is an electrostatic equivalence and does not capture all interface, phonon, or reliability effects.

4.3 Junction and band-to-band tunnelling leakage

Highly doped, abrupt junctions produce strong electric fields. Band-to-band tunnelling may contribute to junction leakage, especially under reverse bias. Aggressive halo doping and raised source/drain regions can improve short-channel control but may increase junction capacitance or tunnelling-related leakage.

4.4 Gate-induced drain leakage and reliability-related leakage

Gate-induced drain leakage (GIDL) occurs near the drain-side gate edge under high electric field, particularly when the gate and drain are at different potentials. Hot-carrier effects, bias-temperature instability, oxide traps, and random telegraph noise can alter current over time. Leakage analysis must therefore include both initial and aged behaviour.

5. Variability at the Nanoscale

Variability is a statistical property of a technology population, not merely a measurement error. Important sources include random dopant fluctuation, line-edge roughness, metal-gate work-function variation, oxide-thickness variation, fin-width variation, contact resistance variation, interface-trap density, and local stress differences.

A first-order sensitivity model expresses threshold variation as

\[

\sigma_{V_T}^{2}\approx \sum_i \left(\frac{\partial V_T}{\partial x_i}\right)^2\sigma_{x_i}^{2},

\]

assuming small variations, linearization around a nominal operating point, and independent parameters. If parameters are correlated, covariance terms must be added:

\[

\sigma_{V_T}^{2}=\sum_i\sum_j \frac{\partial V_T}{\partial x_i}\frac{\partial V_T}{\partial x_j}\mathrm{Cov}(x_i,x_j).

\]

The threshold-voltage variation caused by random dopants generally decreases when the number of dopants in the active channel is reduced, but discrete dopant effects can then become non-Gaussian and spatially localized. FinFETs reduce some planar variability by using lightly doped or undoped bodies, yet fin dimensions, line-edge roughness, and work-function granularity remain significant.

Variability affects delay, leakage, static noise margin, SRAM yield, analog matching, and lifetime. Designers use statistical corner analysis, Monte Carlo simulation, layout-dependent models, redundancy, adaptive body or supply bias, and error-tolerant architectures. A nominally faster transistor is not necessarily preferable if its distribution has a large tail of slow or leaky devices.

6. Device Architectures for Electrostatic Integrity

6.1 Bulk planar CMOS

Bulk CMOS uses a silicon substrate with wells and planar gates. It offers mature processing, high design ecosystem compatibility, and relatively low cost. Its principal limitation at short channel length is weak gate control over the body, leading to DIBL, roll-off, and leakage. Heavy channel doping can improve electrostatics but degrades mobility and increases variability.

6.2 Partially depleted and fully depleted SOI

In SOI, a thin silicon layer is separated from the substrate by a buried oxide (BOX). The BOX reduces parasitic junction capacitance and can improve switching speed. Fully depleted SOI (FD-SOI) uses a sufficiently thin silicon film that the body is depleted through its thickness. A back gate or body bias can adjust threshold voltage dynamically.

Advantages include low junction capacitance, body-bias flexibility, and useful low-power operation. Limitations include self-heating because the BOX is thermally resistive, floating-body effects in some structures, and wafer cost or integration complexity.

6.3 FinFET

A FinFET forms the channel in a vertical fin, with the gate controlling two or three fin surfaces. Multi-surface control increases effective gate coupling without requiring an extremely wide planar channel. Fin width is a key electrostatic parameter, while effective width is quantized by the number of fins and their geometry.

FinFETs provide improved short-channel control, lower leakage, and higher drive than comparable planar devices. However, fin quantization complicates precise transistor sizing, narrow fins create variability, and parasitic capacitance and contact resistance can limit performance. Gate, spacer, source/drain, and interconnect geometry must be co-optimized.

6.4 Gate-all-around nanowires and nanosheets

A GAA transistor surrounds the channel with gate material, offering stronger electrostatic control than a tri-gate FinFET. Nanowire channels provide excellent gate control but have limited drive per channel. Nanosheets or nanoribbons increase width while retaining all-around gating. Several vertically stacked sheets can raise drive current per footprint.

Nanosheet devices introduce challenges in selective channel release, inner spacer formation, sheet thickness control, gate filling, mechanical stability, and parasitic resistance. Their wider sheets also require careful control of electrostatic integrity and quantum confinement.

6.5 Complementary FETs

A CFET vertically stacks nFET and pFET devices rather than placing them side by side. This can reduce standard-cell footprint and improve logic density beyond conventional two-dimensional complementary layouts. Sequential or monolithic integration raises demanding issues: thermal budgets, alignment, isolation, vertical interconnects, device asymmetry, defect tolerance, and process yield.

CFET is therefore a system-level density strategy, not merely a new channel shape. Its value depends on whether reduced area offsets additional fabrication complexity and parasitic effects.

7. CMOS Scaling Strategies

7.1 Geometric and electrostatic scaling

Classical constant-field scaling reduces dimensions and voltages together so that electric fields remain approximately constant. In practice, supply voltage has not scaled as rapidly as physical dimensions because threshold voltage cannot be reduced proportionally without unacceptable leakage. Modern scaling is therefore often called voltage-limited or generalized scaling rather than ideal constant-field scaling.

Electrostatic scaling uses thin bodies, high-\(k\) dielectrics, multi-gate structures, optimized spacers, shallow extensions, and raised source/drain regions. The objective is to improve gate control while lowering access resistance and preserving carrier injection.

7.2 Materials and contact engineering

High-mobility channels, strain engineering, metal silicides, low-resistance contacts, and improved barrier materials can increase drive current. At very small dimensions, contact resistance may consume a large portion of the total resistance. Consequently, increasing intrinsic mobility alone may produce little system benefit if contacts and local interconnect dominate.

7.3 Design–technology co-optimization

Scaling increasingly requires co-optimization across device, standard cell, SRAM, interconnect, and packaging. A transistor with high peak current may not improve processor performance if its capacitance, variability, or wiring demand is excessive. Libraries may use multiple threshold voltages, selective transistor sizing, backside power delivery, and local interconnect optimization.

7.4 Power-management techniques

Leakage is managed using high-threshold devices on noncritical paths, power gating, state retention, body bias, adaptive voltage scaling, and workload-aware clock control. Dynamic power is reduced through lower switching activity, capacitance reduction, and voltage management. Thermal design must address both average power and local hot spots.

8. Worked Example: Subthreshold Swing and Leakage Sensitivity

Consider a transistor at 300 K with subthreshold factor \(n=1.4\). The thermal voltage is approximately \(U_T=25.85\) mV. Its subthreshold swing is

\[

S=n(\ln10)U_T

=1.4\times2.3026\times25.85\,\mathrm{mV}

\approx83.3\,\mathrm{mV/decade}.

\]

If the threshold voltage decreases by 40 mV while all other conditions remain constant, the subthreshold current changes by

\[

\frac{I_{new}}{I_{old}}=10^{\Delta V_T/S}

=10^{40/83.3}\approx 3.0.

\]

Thus, a 40 mV reduction in threshold voltage approximately triples subthreshold leakage for this device under the stated assumptions. The result illustrates why DIBL and random threshold variation are serious at low supply voltage: a voltage shift that appears small on a circuit scale produces a large exponential current change.

9. Illustrative Case Study: Choosing a Logic Platform for a Low-Power Processor

Background

An illustrative semiconductor design team must select a transistor platform for a battery-powered processor. The design requires low standby power, adequate peak performance, high SRAM yield, and a ten-year product lifetime. Candidate platforms are FD-SOI, FinFET, and GAA nanosheet CMOS.

Problem

FD-SOI offers body-bias control and low capacitance but may have lower density. FinFET provides a mature ecosystem and strong performance, but fin quantization restricts sizing. GAA nanosheets offer superior electrostatic control and high effective width but involve greater process complexity and early-yield risk.

Analysis

The team evaluates four categories: off-state leakage at high temperature, delay distribution under process variation, SRAM static noise margin, and manufacturing maturity. Device simulations show that GAA has the best DIBL and leakage distribution, while FD-SOI provides the widest adaptive body-bias range. FinFET has the most predictable design enablement and the lowest integration risk. Thermal simulation indicates that the BOX in FD-SOI requires careful hot-spot management, whereas stacked nanosheets require attention to heat removal and inner-spacer parasitics.

Approach and solution

For the first product generation, the team selects a mature FinFET platform for the high-performance core, uses high-threshold cells in noncritical logic, and applies aggressive power gating to inactive blocks. FD-SOI is retained for a companion ultra-low-power controller where body bias provides substantial energy savings. A future product is planned around GAA nanosheets after process qualification and SRAM data become available.

Outcome

The decision does not identify one universally superior transistor. Instead, it matches architecture to product constraints. The mature platform reduces schedule and yield risk, while differentiated use of threshold options and power management addresses leakage. The roadmap preserves GAA adoption when its electrostatic benefits justify its manufacturing cost.

Learning points

1. Device selection must include variability, thermal behaviour, and process maturity, not only peak current.

2. Architecture-level power techniques can be as important as transistor-level leakage reduction.

3. A technically superior device may be unsuitable if its yield or design ecosystem is immature.

4. Technology roadmaps should distinguish immediate product optimization from long-term density goals.

10. Challenges, Reliability, and Governance Considerations

Nanoscale devices face coupled reliability mechanisms. Bias-temperature instability shifts threshold voltage; hot-carrier injection damages interfaces; time-dependent dielectric breakdown threatens gate insulation; electromigration affects interconnects; and self-heating accelerates several failure processes. Reliability qualification must use statistically meaningful samples and physically justified acceleration models. Extrapolating lifetime from a single nominal device is unsafe.

Security is also relevant. Process variation and aging influence physically unclonable functions, side-channel signatures, and hardware fingerprinting. Manufacturing data, defect maps, and device-level telemetry can contain commercially sensitive information. AI-based yield optimization may identify correlations in high-dimensional process data, but models require traceability, representative training data, uncertainty estimates, and human engineering review. AI should support—not replace—physical modelling and reliability validation.

Environmental and governance concerns include energy consumption in fabrication, chemical handling, critical-material supply chains, and responsible disposal. Decisions involving advanced process technology should account for lifecycle impacts, worker safety, export controls, and supply-chain resilience.

11. Contemporary Developments and Best Practices

Current research and industrial development emphasize several directions:

• vertically stacked nanosheets and CFETs for continued density improvement;
• backside power delivery to reduce front-side routing congestion and voltage drop;
• complementary two-dimensional materials and alternative channel materials;
• advanced high-\(k\) gate stacks and metal-gate work-function engineering;
• contact-over-active-gate and buried power structures;
• co-optimization of transistors, interconnects, advanced packaging, and chiplets;
• compact models that include statistical variation, self-heating, quantum effects, and aging.

Best practice in nanoscale MOSFET analysis includes defining extraction conditions clearly, separating intrinsic from extrinsic resistance, reporting temperature and geometry, using statistical rather than single-device conclusions, validating compact models against measured data, and evaluating complete circuits rather than isolated transistor figures of merit. Comparisons should use consistent effective width, supply voltage, frequency, duty cycle, thermal boundary conditions, and reliability targets.

Chapter Summary

Nanoscale MOSFETs differ fundamentally from long-channel devices because source and drain fields influence the channel, carrier velocity saturates, tunnelling increases, and variability becomes a first-order design concern. Threshold-voltage roll-off and DIBL reduce electrostatic integrity, while subthreshold swing determines how effectively gate voltage separates on and off states. Leakage includes subthreshold, gate, junction, band-to-band, and gate-induced drain components.

Electrostatic scaling length provides a useful framework for relating body thickness, dielectric thickness, permittivity, and channel control. Thin-body and multi-gate architectures reduce source/drain influence. SOI improves capacitance and enables body bias; FinFETs use tri-gate control; GAA nanowires and nanosheets provide stronger surrounding-gate control; and CFETs pursue density through vertical complementary stacking.

Future scaling is constrained not only by transistor dimensions but also by voltage, contacts, interconnects, heat removal, variability, reliability, process complexity, and economic risk. Successful technology selection therefore requires design–technology co-optimization and statistical evaluation. The best architecture is application-dependent and must be judged by performance, power, area, manufacturability, lifetime, and system-level value.

Key Terms

Electrostatic control: The ability of the gate to determine the channel potential and suppress source/drain influence.

Short-channel effect: A deviation from long-channel behaviour caused by a channel length comparable to depletion and electrostatic dimensions.

Threshold-voltage roll-off: Reduction of threshold voltage as channel length decreases.

Drain-induced barrier lowering: Reduction of the source-channel barrier and threshold voltage caused by increased drain voltage.

Subthreshold conduction: Diffusion current flowing when the gate voltage is below threshold.

Subthreshold swing: Gate-voltage change required for one decade change in subthreshold current.

Velocity saturation: Limiting of carrier velocity at high electric field.

Electrostatic scaling length: Characteristic distance over which source or drain potential penetrates the channel.

Equivalent oxide thickness: Physical dielectric thickness expressed as the thickness of SiO₂ providing equivalent capacitance.

Gate leakage: Current tunnelling through the gate dielectric.

DIBL: Drain-induced barrier lowering, commonly measured in mV/V.

Variability: Statistical deviation of device parameters across devices or manufacturing lots.

FinFET: A transistor using a fin-shaped channel controlled by multiple gate surfaces.

SOI: Silicon-on-insulator technology using a buried insulating layer beneath the active silicon.

GAA transistor: A transistor in which the gate surrounds the channel.

Nanosheet: A laterally broad, vertically stacked channel controlled by a surrounding gate.

CFET: Complementary FET architecture that vertically stacks n-type and p-type devices.

Self-heating: Temperature rise caused by internally generated power and limited heat removal.

Design–technology co-optimization: Joint optimization of process, device, circuit, layout, and system choices.

Review Questions

Short Answer Questions

1. Why does DIBL increase as a MOSFET is scaled to shorter channel length?

2. Define subthreshold swing and state its ideal thermal-limit value at room temperature.

3. What is the purpose of a high-\(k\) gate dielectric?

4. Identify two advantages and two limitations of FinFET technology.

5. Why does threshold-voltage variability have an exponential effect on leakage?

Long Answer Questions

1. Explain the transition from long-channel MOSFET operation to velocity-saturated and quasi-ballistic transport.

2. Compare bulk planar CMOS, FD-SOI, FinFET, and GAA nanosheet architectures in terms of electrostatics, parasitics, variability, and manufacturability.

3. Derive the expression for subthreshold swing from the exponential subthreshold current relation and discuss the role of depletion capacitance.

4. Discuss the principal leakage mechanisms in nanoscale CMOS and the technology methods used to reduce each one.

5. Explain why modern CMOS scaling requires design–technology co-optimization rather than geometric shrinkage alone.

Analytical / Application Questions

1. A device has a subthreshold swing of 75 mV/decade. Estimate the leakage-current multiplication caused by a 30 mV reduction in threshold voltage, assuming all other quantities remain constant.

2. A low-power processor must choose between FD-SOI and GAA nanosheet technology. Develop a decision matrix using leakage, body-bias capability, density, thermal behaviour, process maturity, and yield risk.

3. A FinFET library exhibits large delay spread and SRAM failures. Propose an investigation plan that separates work-function variation, fin geometry variation, contact resistance, temperature, and aging effects.

Multiple Choice Questions with Answers

Question 1

Which effect directly describes threshold-voltage reduction caused by increasing drain voltage?

A. Channel-length modulation

B. Drain-induced barrier lowering

C. Velocity saturation

D. Body effect

Correct Answer: B. Drain-induced barrier lowering

Question 2

At approximately 300 K, the ideal subthreshold swing of a MOSFET is closest to:

A. 6 mV/decade

B. 30 mV/decade

C. 60 mV/decade

D. 120 mV/decade

Correct Answer: C. 60 mV/decade

Question 3

What is the principal electrostatic advantage of a gate-all-around transistor?

A. The channel is controlled by only the drain

B. The gate surrounds the channel and improves potential control

C. The substrate is necessarily heavily doped

D. The device eliminates all parasitic capacitance

Correct Answer: B. The gate surrounds the channel and improves potential control

Question 4

For a dielectric with physical thickness 3 nm and relative permittivity 12, using silicon dioxide relative permittivity 3.9, the approximate EOT is:

A. 0.98 nm

B. 3.08 nm

C. 9.23 nm

D. 36.9 nm

Correct Answer: A. 0.98 nm

Question 5

Which architecture enables dynamic threshold adjustment through a back-gate or body-bias terminal?

A. FD-SOI

B. Conventional bulk planar CMOS only

C. A passive resistor

D. A metal interconnect

Correct Answer: A. FD-SOI

Question 6

Why does a high-\(k\) dielectric reduce direct gate tunnelling for a given EOT?

A. It permits a physically thicker dielectric

B. It removes the channel

C. It forces the supply voltage to zero

D. It eliminates interface states completely

Correct Answer: A. It permits a physically thicker dielectric

Question 7

If subthreshold swing is 80 mV/decade, a 40 mV decrease in threshold voltage ideally changes leakage by approximately:

A. 1.2 times

B. 2 times

C. 3.16 times

D. 40 times

Correct Answer: C. 3.16 times

Question 8

Which variability source is especially associated with the discrete number and placement of dopants in a channel?

A. Random dopant fluctuation

B. Clock skew

C. Package inductance

D. Optical diffraction only

Correct Answer: A. Random dopant fluctuation

Question 9

What is the defining density strategy of a CFET?

A. Replacing CMOS with a resistor

B. Vertically stacking complementary n-type and p-type devices

C. Using only one transistor type

D. Removing the gate dielectric

Correct Answer: B. Vertically stacking complementary n-type and p-type devices

Question 10

The dynamic power of a CMOS circuit is proportional to which quantity under the standard switching model?

A. \(V_{DD}\) only

B. \(1/V_{DD}^{2}\) only

C. \(\alpha C_L V_{DD}^{2}f\)

D. \(C_L/V_{DD}\)

Correct Answer: C. \(\alpha C_L V_{DD}^{2}f\)