Nanofabrication and Process Integration

Introduction

Nanoelectronics depends not only on the invention of nanoscale devices but also on the ability to manufacture them repeatedly, economically, and with controlled variation. Nanofabrication is the set of physical and chemical processes used to create structures whose critical dimensions commonly range from a few nanometres to several hundred nanometres. At these dimensions, surface effects, statistical variation, contamination, defect density, interface quality, and process history strongly influence device behaviour.

Fabrication is traditionally divided into top-down and bottom-up approaches. Top-down processing begins with a bulk material and defines structures by patterning, removal, implantation, and modification. Bottom-up processing constructs structures from atoms, molecules, clusters, or nanoscale building blocks. Modern nanoelectronic manufacturing combines both approaches: lithography defines device locations and interconnections, while deposition, epitaxy, self-assembly, and atomic-layer processes establish material composition and thickness.

Process integration is the disciplined sequencing of unit processes so that each step produces the intended structure without damaging previously formed features. Integration therefore involves more than selecting technically effective processes. It requires compatibility of temperature, chemistry, stress, contamination level, pattern alignment, defect tolerance, throughput, and cost.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Compare top-down and bottom-up nanofabrication strategies.

2. Explain the principles and limitations of optical, electron-beam, and nanoimprint lithography.

3. Select appropriate deposition, etching, doping, and epitaxial techniques.

4. Describe self-assembly and atomic-layer processing in nanoelectronics.

5. Explain cleanroom control, contamination management, and process monitoring.

6. Analyse yield, variability, and design-for-manufacturability issues.

7. Develop a coherent process-integration strategy for a nanoscale device.

8. Evaluate emerging fabrication technologies and their industrial limitations.

1. Fabrication Paradigms

1.1 Top-down fabrication

Top-down fabrication uses lithography to define a pattern, followed by material addition, removal, or modification. A typical sequence is wafer cleaning, film deposition, photoresist coating, exposure, development, etching or implantation, resist stripping, and inspection. Silicon complementary metal–oxide–semiconductor (CMOS) manufacturing is the most important example.

Advantages include accurate placement, compatibility with wafer-scale manufacturing, mature process control, and integration with multilayer wiring. Limitations include tool cost, patterning complexity, line-edge roughness, damage from energetic particles or plasmas, and increasing difficulty in controlling dimensions at very small scales.

1.2 Bottom-up fabrication

Bottom-up fabrication forms structures through nucleation, crystal growth, chemical synthesis, molecular recognition, or self-assembly. Examples include semiconductor nanowires grown by vapour–liquid–solid methods, block-copolymer pattern formation, colloidal quantum dots, molecular monolayers, and atomic-layer deposition.

Bottom-up methods can provide excellent material quality and atomic-scale thickness control. They may also reduce material waste and enable structures difficult to produce by conventional lithography. However, placement, orientation, defect control, compatibility with thermal budgets, and integration with conventional contacts remain difficult.

1.3 Comparative evaluation

Top-down methods offer positional control; bottom-up methods often offer material and dimensional control. The practical direction of nanoelectronics is therefore hybrid integration. For example, a lithographically defined trench may determine where a nanowire is placed, while selective epitaxy determines its composition and crystal quality. A lithographic electrode may contact a self-assembled molecular layer.

A useful process-selection framework evaluates: required feature size, placement accuracy, material compatibility, throughput, defect tolerance, thermal budget, environmental burden, equipment availability, and cost per wafer. The smallest nominal feature is not necessarily the best process choice; variability and integration reliability are equally important.

2. Substrates, Surface Preparation, and Contamination

The substrate provides mechanical support and often participates electrically or chemically in the device. Common substrates include silicon, silicon-on-insulator (SOI), sapphire, glass, III–V semiconductors, silicon carbide, and flexible polymeric materials. Substrate selection affects lattice matching, thermal conductivity, dielectric isolation, parasitic capacitance, and allowable processing temperature.

Surface preparation normally includes solvent cleaning, aqueous cleaning, oxide removal when required, dehydration, and controlled surface termination. A clean surface is essential because nanometre-scale films are strongly affected by particles, organic residues, native oxides, metallic impurities, and adsorbed moisture. Cleaning chemistry must be selected with awareness of substrate compatibility and worker safety.

Contamination is classified as particulate, organic, ionic, metallic, or biological. A particle larger than a critical device dimension can cause an open circuit, short circuit, or pattern defect. Metallic contamination can introduce deep electronic states or alter minority-carrier lifetime. Cross-contamination is controlled by chemical segregation, dedicated tools, wafer carriers, process qualification, and strict material-flow rules.

3. Lithography and Pattern Transfer

Lithography transfers geometric information from a mask, direct-write system, or template into a resist or directly into a functional film. Important performance measures are resolution, overlay accuracy, depth of focus, sensitivity, throughput, contrast, line-edge roughness, and defect probability.

3.1 Optical lithography

In optical lithography, ultraviolet radiation exposes a photosensitive resist through a mask or projection system. A commonly used approximate resolution relationship is

R = k_1 lambda/NA

where R is the minimum printable feature dimension, lambda is the exposure wavelength, NA is the numerical aperture, and k_1 is a process-dependent factor. The relation is a scaling guideline, not a fundamental exact law. It assumes a specified imaging configuration and does not by itself account for resist collapse, stochastic variation, mask error, or etch bias. Reducing wavelength or increasing numerical aperture generally improves resolution, while process optimization reduces k_1 within practical limits.

Depth of focus decreases as numerical aperture increases. Consequently, high-resolution lithography requires excellent wafer planarity, focus control, resist uniformity, and overlay control. Resolution enhancement techniques include phase-shifting masks, optical proximity correction, multiple patterning, and computational lithography.

3.2 Electron-beam lithography

Electron-beam lithography scans a focused electron beam across a resist. It provides high resolution and flexible pattern generation, making it valuable for research, mask writing, and low-volume devices. Its principal limitation is serial writing, which leads to low throughput. Proximity effects arise because electrons undergo forward scattering in the resist and backscattering from the substrate. Dose correction and suitable resist thickness are therefore necessary.

3.3 Nanoimprint lithography

Nanoimprint lithography mechanically transfers a template pattern into a resist. It can achieve high resolution over a large area and may have lower optical-system complexity than advanced projection lithography. Challenges include template fabrication, defect replication, particle control, residual-layer uniformity, alignment, and demoulding damage.

3.4 Resist processing

Resist processing includes coating, soft bake, exposure, post-exposure bake, development, inspection, and sometimes hard bake. Positive resists become more soluble in exposed regions; negative resists become less soluble or cross-linked in exposed regions. Resist thickness must be sufficient for pattern transfer but not so large that resolution and focus control deteriorate.

Line-edge roughness is particularly important in nanoscale transistors because local width variation changes electrical characteristics. It originates from photon or electron statistics, resist chemistry, developer fluctuations, and subsequent etching. Statistical process control must therefore monitor both mean dimensions and roughness distributions.

4. Deposition and Film Formation

Deposition adds material to a substrate. Physical vapour deposition (PVD), including evaporation and sputtering, uses physical transport of atoms. Chemical vapour deposition (CVD) uses gas-phase chemical reactions. Atomic-layer deposition (ALD) uses sequential, self-limiting surface reactions.

4.1 Physical vapour deposition

Evaporation can produce high-purity films with relatively low substrate damage, but its line-of-sight nature produces poor coverage on deep or narrow features. Sputtering provides energetic deposition and good material flexibility, but ion bombardment may damage sensitive surfaces and generate stress.

4.2 Chemical vapour deposition

CVD offers conformal coverage and is widely used for dielectrics, polysilicon, silicon nitride, silicon carbide, and compound semiconductors. Film properties depend on temperature, pressure, precursor flow, residence time, plasma conditions, and surface chemistry. Plasma-enhanced CVD reduces substrate temperature but can introduce ion damage and hydrogen incorporation.

4.3 Atomic-layer deposition

ALD separates precursor reactions into cycles. In an ideal process, precursor A reacts with available surface sites, excess A is purged, precursor B reacts with the modified surface, and excess B is purged. Because each half-reaction is self-limiting, thickness is controlled primarily by the number of cycles. If the growth per cycle is g and the number of cycles is N, the nominal thickness is

t = Ng

where t and g use the same length units. This relation assumes a stable growth-per-cycle regime and neglects nucleation delay, precursor depletion, surface nonuniformity, and etch or densification effects.

ALD is valuable for high-k gate dielectrics, metal barriers, passivation layers, and three-dimensional structures. Its disadvantages include slow deposition, precursor cost, possible impurities, and incomplete nucleation on some surfaces. Plasma-enhanced ALD can improve reactivity at lower temperature but may increase damage risk.

5. Etching and Selective Material Removal

Etching transfers the resist pattern into an underlying film. Wet etching uses liquid chemicals and may be highly selective and economical. It is often isotropic, although crystallographic anisotropy can produce direction-dependent profiles. Dry etching uses reactive plasmas, energetic ions, or both. Reactive-ion etching combines chemical reaction with directional ion bombardment and is essential for nanoscale pattern transfer.

Important etch metrics include rate, selectivity, anisotropy, uniformity, surface damage, residue formation, and endpoint detectability. Etch selectivity between material A and material B may be expressed as

S_A/B = rate of A removal / rate of B removal

The rates must be measured under the same conditions and in consistent units. High selectivity is desirable when B is an etch stop or critical underlying layer.

Physical sputtering can produce anisotropic profiles but may cause lattice damage and charging. Chemical plasma etching can be more selective but may be less directional. Atomic layer etching extends the self-limiting concept to removal: surface modification and activation occur cyclically, allowing highly controlled material removal with reduced over-etch damage.

Etch-induced problems include footing, notching, microloading, aspect-ratio-dependent etching, sidewall roughness, polymer deposition, and charging. Process engineers use hard masks, pulsed plasmas, bias control, endpoint spectroscopy, and post-etch cleaning to mitigate them.

6. Doping, Activation, and Epitaxy

Doping changes carrier concentration by introducing controlled impurity atoms. Ion implantation accelerates dopant ions into a substrate. The approximate projected range and concentration distribution depend on ion species, energy, dose, substrate composition, and crystallographic orientation. Implantation provides excellent dose control but creates lattice damage and requires annealing.

The implanted dose Q is the number of dopant atoms per unit area, commonly expressed in cm^-2. If a simplified uniform profile extends over depth x, the average concentration is approximately

C_avg = Q/x

This approximation is useful only when the concentration is reasonably uniform over the stated depth. Real implantation profiles are nonuniform, and channeling can produce deeper tails.

Thermal annealing repairs crystal damage and electrically activates dopants by moving them onto substitutional lattice sites. Excessive thermal exposure causes dopant diffusion, which can broaden abrupt junctions. Rapid thermal processing, spike annealing, and millisecond or laser annealing reduce unwanted diffusion.

Diffusion is often described, under idealized constant-diffusivity conditions, by Fick’s laws. In real process integration, diffusivity depends on temperature, crystal defects, dopant concentration, and time; therefore calibrated process simulation and measurement are required.

Epitaxy is the growth of a crystalline layer with a defined relationship to the substrate. Homoepitaxy uses the same material, while heteroepitaxy uses a different material. Epitaxy enables strained channels, quantum wells, superlattices, buried layers, and three-dimensional selective structures. Lattice mismatch, thermal-expansion mismatch, dislocations, surface preparation, and parasitic nucleation determine quality. Selective epitaxy requires control of exposed crystal surfaces, masks, precursor chemistry, and loading effects.

7. Self-Assembly and Molecular-Scale Processing

Self-assembly is the spontaneous organization of components through local interactions such as van der Waals forces, hydrogen bonding, electrostatic attraction, phase separation, or chemical affinity. Block copolymers can form periodic domains whose pitch is determined by molecular architecture and processing conditions. Directed self-assembly combines these natural patterns with guiding lithographic features to improve placement.

Self-assembled monolayers modify surface energy, provide chemical functionality, act as etch barriers, or form molecular electronic elements. Their performance depends on chain length, packing density, defects, terminal groups, substrate preparation, and environmental exposure.

The central integration problem is that self-assembly can generate excellent local order without providing the global registration and defect control required by a circuit. Hybrid strategies use top-down alignment and bottom-up structure formation, followed by selective removal, conversion, or metallization.

8. Process Integration and Thermal Budget

A process flow is a dependency graph: each step must be compatible with earlier structures and must not compromise later requirements. Integration decisions include:

• front-end versus back-end process sequence;
• maximum temperature after dopant activation or metallization;
• compatibility of wet chemicals and plasma species with exposed materials;
• alignment and overlay requirements;
• stress and wafer curvature;
• contact resistance and interface cleanliness;
• electrical isolation and parasitic capacitance;
• availability of etch stops and sacrificial layers.

The thermal budget is the cumulative thermal exposure experienced by the wafer. It is not represented by temperature alone; duration, ambient, and transient heating also matter. A low-temperature dielectric deposited after metal formation may be preferred even if a higher-temperature alternative has better intrinsic quality.

Process integration is verified with split lots, test structures, cross-sectional microscopy, film metrology, electrical characterization, and reliability testing. A split experiment changes one process variable while keeping others controlled, allowing causal interpretation.

9. Cleanroom Control and Process Monitoring

Cleanrooms control airborne particles, temperature, humidity, pressure, vibration, electrostatic conditions, and chemical contamination. A cleanroom classification describes allowable airborne particle concentrations under a specified standard and particle-size condition; it does not guarantee cleanliness of every wafer or tool.

Good practice includes gowning discipline, controlled wafer handling, chemical segregation, preventive maintenance, tool qualification, and documented recovery after excursions. Process gases require purity control, leak detection, filtration, and safe exhaust treatment. Hazardous chemicals and gases require engineering controls, standard operating procedures, training, emergency planning, and regulatory compliance.

Metrology should be integrated into the process rather than performed only at final inspection. Typical measurements include film thickness, refractive index, sheet resistance, critical dimension, overlay, surface roughness, defect maps, stress, composition, and electrical parameters. Statistical process control uses control charts to distinguish common-cause variation from special-cause events. Control limits must be established from appropriate baseline data; they are not automatically identical to product specification limits.

10. Yield, Variability, and Reliability

Yield is the fraction of acceptable units produced. Defects may be random, systematic, process-induced, design-induced, or parametric. A simple random-defect model is

Y = exp(-D A)

where Y is the probability that a unit contains no defect, D is the average defect density per unit area, A is the vulnerable area, and exp is the natural exponential function. The model assumes randomly distributed independent defects and is only an approximation. Clustering, redundancy, defect exclusion zones, and multiple defect mechanisms require more advanced models.

Variability arises from wafer nonuniformity, line-edge roughness, random dopant fluctuation, metal-grain structure, interface traps, temperature variation, and equipment drift. At nanoscale dimensions, a small geometric change can cause a large electrical change. Design-for-manufacturability therefore uses redundant contacts, relaxed critical dimensions where possible, statistical design margins, layout regularity, and process-aware device models.

Yield improvement follows a disciplined loop: detect the failure, classify its mechanism, isolate the responsible process step, test a corrective hypothesis, verify improvement on independent material, and institutionalize the solution. Correlation alone is insufficient; physical evidence and controlled experiments are required.

Reliability concerns include electromigration, dielectric breakdown, bias-temperature instability, hot-carrier degradation, stress-induced voiding, interface degradation, and thermal cycling. Nanoscale process integration must evaluate not only initial performance but also lifetime distributions and failure mechanisms.

11. Illustrative Case: Integrating a Gate-All-Around Nanowire Transistor

Background

Consider an illustrative research-to-pilot process for a silicon gate-all-around nanowire transistor. The objective is to obtain a thin, uniformly gated channel with low leakage and reproducible threshold voltage.

Problem

The device requires nanoscale channel formation, a high-quality surrounding dielectric, conformal metal deposition, source/drain access, and low-resistance contacts. Excessive etch damage or nonuniform dielectric thickness can cause leakage and threshold-voltage variation.

Analysis

A purely top-down route can define the nanowire but may produce rough sidewalls and nonuniform dimensions. A bottom-up epitaxial route can provide high-quality crystalline material but makes placement and contact formation more difficult. A hybrid sequence is therefore selected.

Approach

First, a silicon-containing multilayer is prepared by epitaxy, with a sacrificial layer incorporated beneath the intended channel. Lithography and anisotropic etching define aligned fins. Selective removal of the sacrificial layer releases the channel. Surface cleaning is followed by ALD of a high-k dielectric, using a qualified nucleation sequence. A conformal gate metal is then deposited, and source/drain regions are formed by selective epitaxy or implantation according to the chosen thermal budget. Contacts are patterned and annealed under conditions that limit dopant diffusion and dielectric degradation.

Test structures measure nanowire diameter, dielectric thickness, gate leakage, contact resistance, subthreshold behaviour, and device-to-device variation. Cross-sectional transmission electron microscopy is used on sampled wafers to verify interfaces and crystallinity.

Outcome

The hybrid process provides better gate coverage than a planar deposition sequence and better placement than an entirely bottom-up approach. The principal yield losses arise from sacrificial-layer removal nonuniformity, particle-induced gate shorts, and contact resistance. Process improvements include tighter wet-etch control, enhanced particle monitoring, and contact-surface preparation before metallization.

Learning points

The case demonstrates that process integration is a system problem. No individual step is sufficient: epitaxy, pattern transfer, release, ALD, metallization, cleaning, and metrology must be co-optimized. A process with excellent isolated film quality may still fail when its thermal, chemical, or defect constraints conflict with neighbouring steps.

12. Contemporary Developments and Critical Issues

Advanced manufacturing increasingly combines extreme-ultraviolet lithography, computational pattern correction, directed self-assembly, selective deposition, atomic-layer etching, backside processing, and three-dimensional integration. Monolithic three-dimensional electronics require low-temperature processing of upper tiers to protect lower-tier devices. Heterogeneous integration combines materials such as silicon, III–V compounds, wide-bandgap semiconductors, and two-dimensional materials, but interface contamination and thermal-expansion mismatch remain important barriers.

Artificial intelligence is becoming useful for defect classification, virtual metrology, equipment health monitoring, recipe optimization, and prediction of yield excursions. AI models should be trained on traceable, representative data and validated against physical measurements. A model that predicts correlation without identifying process causality can produce unsafe or costly decisions. Human process ownership, auditability, data security, and out-of-distribution testing remain essential.

Environmental and governance considerations include water consumption, greenhouse-gas emissions from process gases, hazardous chemical handling, waste treatment, supply-chain resilience, and responsible disposal of nanomaterials. Compliance with occupational-safety, chemical-management, environmental, and export-control requirements is part of professional process engineering rather than an optional administrative activity.

Best-Practice Framework

A robust nanofabrication programme should:

1. Define device requirements and allowable variation before selecting processes.

2. Use a process-of-record document with controlled revisions.

3. Qualify materials, tools, recipes, and metrology independently.

4. Characterize interfaces, not only bulk films.

5. Use monitor wafers and dedicated test structures.

6. Track critical dimensions, defect density, overlay, and electrical parameters statistically.

7. Establish contamination and chemical-safety controls before experimentation.

8. Evaluate thermal budget and cross-process compatibility early.

9. Separate exploratory split experiments from production baselines.

10. Verify yield improvements with independent lots and reliability data.

Chapter Summary

Nanofabrication combines top-down pattern definition with bottom-up material and molecular organization. Lithography establishes location and geometry, while deposition, etching, doping, epitaxy, and atomic-layer processes create and modify functional materials. Optical lithography provides throughput, electron-beam lithography provides flexible high resolution, and nanoimprint lithography offers template-based pattern transfer. ALD and atomic-layer etching use self-limiting reactions for excellent thickness or removal control.

Successful process integration requires compatibility of temperature, chemistry, stress, contamination level, alignment, and surface condition. Cleanroom discipline and in-line metrology control the process environment, while statistical methods distinguish normal variation from excursions. Yield depends on defect density, vulnerable area, systematic effects, and nanoscale variability. Hybrid top-down/bottom-up strategies are increasingly important for three-dimensional, heterogeneous, and molecular-scale electronics. Contemporary progress must be evaluated together with safety, environmental, data-governance, and reliability requirements.

Key Terms

Top-down fabrication: Manufacturing by patterning and modifying bulk materials.

Bottom-up fabrication: Construction from atoms, molecules, clusters, or nanoscale building blocks.

Lithography: Transfer of geometric patterns into a resist or functional material.

Numerical aperture: Optical measure governing light-collection and imaging capability.

Overlay: Alignment accuracy between successive patterning levels.

Line-edge roughness: Local variation of a patterned feature edge.

Physical vapour deposition: Film deposition by physical transport of vaporized material.

Chemical vapour deposition: Film growth through gas-phase chemical reactions.

Atomic-layer deposition: Sequential, self-limiting deposition by surface reactions.

Etch selectivity: Ratio of removal rates for two materials.

Anisotropy: Directional dependence of a process profile or rate.

Ion implantation: Introduction of dopant ions by energetic bombardment.

Annealing: Thermal treatment used to repair damage or activate dopants.

Epitaxy: Crystalline growth with an ordered relationship to a substrate.

Self-assembly: Spontaneous organization caused by local interactions.

Thermal budget: Integrated thermal exposure permitted by a process flow.

Process integration: Sequencing and coordinating unit processes into a functional technology.

Defect density: Average number of defects per unit area.

Yield: Fraction of manufactured units meeting requirements.

Design for manufacturability: Design practice that improves process tolerance and yield.

Review Questions

Short Answer Questions

1. Distinguish top-down and bottom-up nanofabrication.

2. What is the purpose of an etch stop?

3. Why is ALD described as self-limiting?

4. Name three important sources of nanoscale variability.

5. What is meant by thermal budget?

Long Answer Questions

1. Compare optical, electron-beam, and nanoimprint lithography in terms of resolution, throughput, and integration challenges.

2. Explain the operation and applications of atomic-layer deposition, including its limitations.

3. Discuss the role of epitaxy, doping, and annealing in semiconductor device fabrication.

4. Explain how cleanroom control and process monitoring contribute to yield improvement.

5. Analyse why hybrid top-down/bottom-up fabrication is important for future nanoelectronics.

Analytical / Application Questions

1. A process has a random defect density of 0.02 cm^-2 and a vulnerable area of 10 cm^2. Using Y = exp(-DA), estimate the defect-free yield and state the model assumptions.

2. An ALD process has a growth per cycle of 0.11 nm. How many cycles are required for a nominal 8.8 nm film, and what practical effects could cause deviation from the nominal thickness?

3. Design a process-integration strategy for a nanosheet transistor in which a high-k dielectric and metal gate must be formed after channel release. Identify at least four compatibility or yield risks and propose measurements for each.

Multiple Choice Questions with Answers

Question 1

Which characteristic most strongly distinguishes bottom-up fabrication from top-down fabrication?

A. It always uses optical masks

B. It constructs structures through atomic, molecular, or nanoscale assembly

C. It cannot produce crystalline materials

D. It requires bulk mechanical machining

Correct Answer: B. It constructs structures through atomic, molecular, or nanoscale assembly

Question 2

In the approximate optical lithography relation R = k1 lambda/NA, increasing NA generally has what effect on resolution R?

A. It increases R and worsens resolution

B. It has no effect on R

C. It decreases R and improves resolution

D. It changes only film thickness

Correct Answer: C. It decreases R and improves resolution

Question 3

What is the principal reason ALD can provide excellent thickness control?

A. It uses only physical sputtering

B. Each precursor reaction is ideally self-limiting

C. It eliminates the need for surface preparation

D. It deposits only on horizontal surfaces

Correct Answer: B. Each precursor reaction is ideally self-limiting

Question 4

Which process is primarily used to introduce controlled impurity atoms into a semiconductor?

A. Ion implantation

B. Photoresist stripping

C. Chemical-mechanical polishing only

D. Nanoimprint replication

Correct Answer: A. Ion implantation

Question 5

If an etch removes material A at 60 nm/min and material B at 3 nm/min, what is the selectivity S_A/B?

A. 0.05

B. 5

C. 20

D. 180

Correct Answer: C. 20

Question 6

Which statement about electron-beam lithography is correct?

A. It is generally a parallel, high-throughput wafer exposure method

B. It provides flexible direct writing but is limited by serial throughput

C. It cannot pattern research devices

D. It eliminates proximity effects completely

Correct Answer: B. It provides flexible direct writing but is limited by serial throughput

Question 7

For a random-defect model with D = 0.01 cm^-2 and A = 20 cm^2, the defect-free yield is approximately:

A. 0.02

B. 0.20

C. 0.82

D. 0.98

Correct Answer: C. 0.82

Question 8

Which integration issue is most directly associated with excessive annealing after implantation?

A. Reduced dopant diffusion

B. Dopant diffusion and junction broadening

C. Elimination of all lattice defects without side effects

D. Improved lithographic focus

Correct Answer: B. Dopant diffusion and junction broadening

Question 9

What is a major limitation of self-assembly for circuit manufacturing?

A. It cannot form nanoscale features

B. It always requires high-energy ion bombardment

C. Global placement and defect control may be insufficient

D. It is incompatible with all chemical processes

Correct Answer: C. Global placement and defect control may be insufficient

Question 10

Which activity best supports identification of a special-cause process excursion?

A. Ignoring wafer-to-wafer data

B. Using only final visual inspection

C. Statistical monitoring combined with controlled experiments and physical evidence

D. Changing several unrelated process steps simultaneously

Correct Answer: C. Statistical monitoring combined with controlled experiments and physical evidence