Beyond-CMOS Devices and Emerging Computing

Introduction and Context

For more than five decades, complementary metal–oxide–semiconductor (CMOS) technology has benefited from scaling, improved lithography, and increasingly sophisticated design automation. CMOS remains the dominant platform for digital logic, memories, sensors, and mixed-signal systems. Nevertheless, continued scaling faces important constraints: leakage power, interconnect delay, variability, heat dissipation, limited voltage scaling, and the increasing cost and complexity of fabrication.

Beyond-CMOS research seeks devices and architectures that exploit physical phenomena not central to conventional charge-based CMOS logic. These include electron spin, magnetic order, ferroelectric polarization, structural phase transitions, ionic motion, superconductivity, and collective or analog dynamics. Some devices are intended to replace or complement CMOS transistors; others are best used as dense memories, reconfigurable elements, stochastic processors, or accelerators for machine learning.

A central theme is that a device should not be judged solely by its switching energy or density. A useful technology must also provide adequate endurance, retention, variability control, manufacturability, interconnect compatibility, error tolerance, and a complete system-level advantage. This chapter examines these technologies from that system perspective.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain the operating principles of spintronic, magnetic, ferroelectric, phase-change, resistive-switching, memristive, superconducting, and neuromorphic devices.

2. Distinguish nonvolatile memory, logic, and in-memory-computing applications.

3. Compare technologies using energy, latency, density, endurance, retention, variability, and integration criteria.

4. Analyze representative device equations and constraints.

5. Evaluate a technology choice for an emerging-computing application.

6. Identify reliability, manufacturing, ethical, and governance issues associated with intelligent hardware.

1. From Charge-Based Switching to State-Based Computing

A CMOS transistor primarily controls a channel current through an electrostatic gate. Information is generally represented by a voltage or charge, and logic is obtained by restoring signals to well-defined voltage levels. Beyond-CMOS devices often represent information using a physical state that persists after power removal. Examples include magnetization direction, ferroelectric polarization, crystalline phase, resistance, or superconducting phase.

Important terminology includes:

• Volatile device: loses its state when power is removed.
• Nonvolatile device: retains its state without continuous power.
• Write energy: energy required to establish a state.
• Read disturb: unintended alteration of a stored state during reading.
• Endurance: number of reliably completed program/erase or switching cycles.
• Retention: duration for which a state remains valid.
• Variability: statistical or device-to-device deviation from nominal behavior.
• In-memory computing (IMC): performing computation within or near the memory array to reduce data movement.
• Compute-in-memory (CIM): a commonly used term for analog or digital computation physically embedded in memory.

A memory technology is often characterized by a state variable, a control mechanism, a readout mechanism, and a failure mechanism. For example, a resistive memory may use resistance as its state variable, voltage or current as the programming stimulus, current as the readout, and filament rupture or drift as reliability mechanisms.

2. Spintronic and Magnetic Devices

2.1 Physical basis

Spintronics uses the electron’s spin in addition to its charge. In a ferromagnet, a population imbalance between spin-up and spin-down electrons produces spin polarization. A magnetic device can therefore store information in magnetization orientation rather than electrical charge.

The most established spintronic memory is magnetoresistive random-access memory (MRAM). A typical magnetic tunnel junction (MTJ) contains a fixed magnetic layer, an insulating tunnel barrier, and a free magnetic layer. The resistance depends on the relative orientation of the fixed and free layers:

• Parallel orientation: lower resistance.
• Antiparallel orientation: higher resistance.

The tunnel magnetoresistance ratio is commonly written as

TMR = (R_AP − R_P) / R_P,

where R_AP is the antiparallel resistance and R_P is the parallel resistance. The expression assumes that the two resistance states are measured under comparable bias and temperature conditions.

2.2 MRAM classes

Spin-transfer-torque MRAM (STT-MRAM) switches the free layer by passing a spin-polarized current through the MTJ. It offers nonvolatility, high endurance, and good speed, but the write current can be substantial and may stress the tunnel barrier.

Spin-orbit-torque MRAM (SOT-MRAM) uses a current in an adjacent heavy-metal or topological layer to generate a transverse spin current. It can separate read and write paths and may support faster switching, but its cell structure is more complex and often requires additional area.

Racetrack memory moves magnetic domain walls along a nanowire. It promises high density and reduced access complexity, but domain-wall pinning, depinning-current variation, and precise positioning remain difficult.

Magnetic skyrmions are nanoscale topological spin textures. Their small size and motion suggest applications in memory and unconventional logic. However, skyrmion nucleation, detection, edge interaction, and thermal stability are still active research problems.

2.3 Magnetic logic and applications

Magnetic devices are attractive for embedded nonvolatile memory, instant-on systems, secure hardware, radiation-tolerant storage, and probabilistic computing. Logic can be implemented using magnetization interactions, spin waves, or majority gates. A practical limitation is that magnetic logic frequently requires signal restoration and conversion between magnetic and electrical domains. Thus, hybrid CMOS–spintronic systems are generally more realistic than a complete CMOS replacement.

3. Ferroelectric Devices

3.1 Polarization and hysteresis

A ferroelectric material has a spontaneous electric polarization that can be reversed by an applied electric field. Its polarization–electric-field relationship exhibits hysteresis. The two stable polarization states can represent binary information.

The remanent polarization is the polarization remaining after the external field returns to zero. A ferroelectric must have sufficient coercive field, retention, endurance, and compatibility with the surrounding semiconductor process.

3.2 FeRAM and ferroelectric FETs

In ferroelectric RAM (FeRAM), a ferroelectric capacitor stores information as polarization. FeRAM provides low-voltage operation, fast access, and high endurance, but its density is limited by the capacitor and cell architecture.

A ferroelectric field-effect transistor (FeFET) incorporates a ferroelectric layer in the gate stack. The polarization shifts the transistor threshold voltage, creating nonvolatile states. FeFETs are attractive for embedded memory and analog weight storage. Important concerns include wake-up behavior, imprint, fatigue, threshold-voltage distribution, and depolarization fields.

3.3 Negative-capacitance concepts

Ferroelectric layers have also been investigated for negative-capacitance field-effect transistors. In an idealized quasi-static model, a stabilized negative differential capacitance region could amplify the internal gate voltage and reduce the external voltage required for a specified channel response. However, stability, hysteresis, dynamic behavior, interface traps, and the distinction between transient amplification and useful subthreshold-slope improvement must be carefully evaluated. Negative capacitance is therefore a device-engineering concept rather than a guaranteed universal solution to CMOS scaling.

4. Phase-Change Memory and Computing

4.1 Operating principle

Phase-change materials, such as chalcogenide alloys, can reversibly switch between amorphous and crystalline phases. The phases have substantially different electrical resistance and optical properties. A short, high-power pulse can melt and rapidly quench a region into the amorphous state; a longer, lower-power pulse can crystallize it.

The resistance ratio between states enables nonvolatile memory. Intermediate resistance values can be created by partially crystallizing the active volume, allowing multilevel storage and analog computation.

4.2 Strengths and limitations

Phase-change memory offers high density, nonvolatility, and compatibility with three-dimensional crossbar concepts. It can support neuromorphic synapses because its conductance may be gradually programmed. However, write energy is often higher than in some competing resistive memories, resistance drift complicates multilevel storage, and repeated thermal cycling affects endurance.

Resistance drift is often modeled empirically as

R(t) = R_0 (t/t_0)^ν,

where R_0 is the resistance at reference time t_0, t is elapsed time, and ν is a material- and state-dependent drift exponent. This relationship is an empirical approximation over a specified time range; it is not a universal physical law. Drift compensation, periodic calibration, differential encoding, and error correction are important in practical systems.

4.3 Neuromorphic use

A phase-change cell can represent a synaptic weight as conductance. An array can perform a weighted sum by applying input voltages to rows and measuring column currents. The idealized column current is

I_j = Σ_i G_ij V_i,

where G_ij is the conductance representing the weight connecting input i to output j, V_i is the applied input voltage, and I_j is the resulting column current. This expression assumes linear device behavior, negligible parasitic voltage drops, and operation within the small-signal regime. Real arrays require compensation for nonlinear programming, line resistance, sneak currents, device noise, and limited conductance range.

5. Resistive-Switching Devices and Memristive Systems

5.1 Resistive random-access memory

RRAM or ReRAM changes resistance through electrically induced movement of defects, ions, vacancies, or conductive filaments. A metal–insulator–metal cell may switch between a high-resistance state and a low-resistance state.

Switching can be filamentary, in which a narrow conductive path forms and ruptures, or interface-type, in which a larger region near an interface changes resistance. Filamentary switching can provide strong resistance contrast and small active volumes, but stochastic filament formation produces variability.

5.2 Memristive behavior

A memristive system is a dynamical resistive system whose conductance depends on an internal state influenced by past electrical excitation. A general representation is

v(t) = R(w,i,t)i(t),

and

dw/dt = f(w,i,t),

where v is voltage, i is current, w is an internal state variable, R is a state-dependent resistance, and f describes state evolution. This formulation is deliberately general. A particular device model must specify boundary conditions, state limits, polarity, temperature dependence, and programming dynamics.

The term “memristor” is sometimes used broadly for all resistive memories, but not every resistive-switching device has the same ideal mathematical properties. Careful technical writing should distinguish an ideal memristor model, a physical memristive system, and a practical RRAM cell.

5.3 Crossbar arrays

Crossbar arrays place programmable resistive elements at intersections of word lines and bit lines. They provide high density and natural matrix-vector multiplication. A major problem is the sneak-path current through unselected cells. One-transistor–one-resistor, one-selector–one-resistor, and complementary resistive-switching structures are methods for controlling unwanted current.

The ideal matrix operation is attractive, but nonidealities include conductance variation, asymmetric potentiation and depression, limited dynamic range, read noise, IR drop, selector nonlinearity, stuck-at faults, and temperature dependence. Algorithm–hardware co-design is therefore essential.

6. Superconducting Devices

Superconductors exhibit zero DC resistance below a critical temperature and expel magnetic flux through the Meissner effect. Josephson junctions, formed by two superconductors separated by a weak link, are central to superconducting electronics.

The Josephson relations are

I = I_c sin(φ)

and

V = (Φ_0 / 2π)(dφ/dt),

where I is junction current, I_c is critical current, φ is the phase difference, V is junction voltage, and Φ_0 = h/(2e) is the magnetic flux quantum. These equations assume the ideal Josephson model; practical junctions also include capacitance, quasiparticle resistance, noise, and parasitic electromagnetic effects.

Single-flux-quantum (SFQ) logic represents information using quantized voltage pulses associated with magnetic-flux quanta. It offers extremely high switching speed and potentially low dynamic energy at the device level. Applications include scientific computing, radio astronomy, high-performance signal processing, and quantum-control electronics.

The principal system disadvantage is cryogenic operation. Cooling power, packaging, thermal interfaces, clock distribution, fabrication yield, and limited memory integration can dominate system energy. Superconducting logic is therefore particularly compelling where extreme performance justifies cryogenic infrastructure, rather than as a universal replacement for room-temperature CMOS.

7. Neuromorphic Devices and Architectures

Neuromorphic computing seeks to emulate selected computational principles of biological nervous systems: distributed memory, event-driven communication, temporal processing, sparse activity, and local adaptation. It does not require exact biological replication.

A neuromorphic system typically contains neurons, synapses, communication pathways, learning rules, and event-generation mechanisms. Devices such as FeFETs, RRAM, phase-change memory, magnetic elements, and organic electrochemical devices may serve as artificial synapses or neurons.

A simplified leaky integrate-and-fire neuron can be described by

τ_m dV_m/dt = −(V_m − V_L) + R_m I(t),

where V_m is membrane potential, V_L is leak potential, R_m is membrane resistance, τ_m is the membrane time constant, and I(t) is input current. When V_m reaches a threshold, the neuron emits a spike and is reset. This model is an abstraction; biological neurons are substantially more complex.

Neuromorphic hardware is useful for event-based vision, sensor fusion, robotics, edge inference, anomaly detection, and temporal classification. Its benefits depend on matching the algorithm to sparse, asynchronous hardware. Conventional dense neural networks may not automatically gain efficiency if frequent data conversion, synchronization, or weight updates eliminate the device-level advantage.

8. Comparing Technologies for Logic, Memory, and In-Memory Computing

No single technology dominates every criterion.

| Technology | Principal state | Main opportunity | Major limitation |

|---|---|---|---|

| STT/SOT-MRAM | Magnetization | Fast nonvolatile memory | Write current, density and integration trade-offs |

| FeRAM/FeFET | Polarization or threshold voltage | Embedded memory, analog weights | Fatigue, imprint, variability |

| Phase-change memory | Material phase | Dense memory, analog synapses | Drift, thermal write energy |

| RRAM/memristor | Resistance or filament state | Crossbar IMC | Variability, sneak paths, endurance |

| Superconducting logic | Flux and phase | Ultra-fast specialized computing | Cryogenic infrastructure |

| Spin-wave/skyrmion devices | Magnetic texture or wave | Wave and non-Boolean logic | Detection, propagation, fabrication complexity |

Useful evaluation metrics include:

1. Latency: device switching time plus interconnect, sensing, and control overhead.

2. Energy per operation: includes drivers, sense amplifiers, converters, and cooling where applicable.

3. Area density: physical cell area is insufficient if selectors, routing, and peripheral circuits dominate.

4. Endurance and retention: both must meet the target workload.

5. Variability and yield: distributions matter more than nominal demonstrations.

6. Scalability: includes lithography, thermal budget, materials integration, and three-dimensional stacking.

7. System compatibility: voltage levels, CMOS back-end processing, packaging, and design tools.

8. Security and reliability: side channels, fault injection, radiation response, and aging.

For analog IMC, the energy benefit is often threatened by analog-to-digital and digital-to-analog conversion. A crossbar that computes a current sum efficiently may still require expensive converters and calibration. Consequently, application-level benchmarking must include the complete data path.

9. Worked Application: Selecting a Technology for Edge-AI Inference

Consider an illustrative edge-vision node that must classify sensor data locally while operating from a limited battery. The system requires nonvolatile parameters, moderate model updates, low standby power, and tolerance to device variation.

Problem. Select a plausible memory/compute approach from embedded MRAM, FeFET arrays, phase-change crossbars, and RRAM crossbars.

Analysis. Embedded MRAM provides excellent retention and endurance but is commonly used as digital memory; analog multiply–accumulate operation is less natural. FeFET arrays can provide multilevel threshold states and low-voltage operation, but polarization variability and limited analog linearity must be managed. Phase-change arrays offer mature analog conductance concepts and multilevel operation, but drift and write energy are concerns. RRAM crossbars offer high density and efficient matrix operations, but filament variability, sneak paths, and endurance require careful architecture.

Approach. Suppose the workload performs mostly inference, with infrequent updates. A practical design could use a resistive or phase-change array for stored weights, digital CMOS control, low-resolution converters, and periodic calibration. Differential pairs can represent positive and negative weights. Redundant cells and software-aware retraining can compensate for conductance variation. Frequently updated parameters may instead be placed in MRAM or SRAM.

Outcome. The best choice is workload-dependent rather than material-dependent. A phase-change array may be attractive when multilevel analog weights and infrequent updates dominate. An RRAM array may be preferable when density and low-voltage matrix operations dominate. FeFETs may be selected for embedded integration and low-power multilevel storage, while MRAM is strong for reliable digital nonvolatile storage.

Learning points. The selection must include peripheral energy, calibration, update frequency, endurance, model accuracy, and manufacturing maturity. A device-level record energy does not establish a system-level advantage.

10. Challenges, Reliability, and Responsible Development

10.1 Reliability

Common failure mechanisms include thermal instability, dielectric breakdown, electromigration, fatigue, imprint, resistance drift, filament overgrowth, read disturb, magnetic switching errors, and radiation-induced state changes. Reliability assessment should use statistically meaningful populations and realistic workload duty cycles, not only isolated best-case devices.

10.2 Manufacturing and integration

New materials may introduce contamination risks, thermal-budget conflicts, interface defects, and yield loss. Three-dimensional integration can shorten interconnects but increases thermal-management and process-complexity problems. Standardized compact models, parameter extraction, design rules, and process design kits are needed before broad commercial adoption.

10.3 Security and governance

Nonvolatile and analog states can create new attack surfaces. Physical probing, magnetic-field perturbation, side-channel analysis, fault injection, and model extraction may compromise systems. Security must be designed at device, circuit, architecture, and software levels.

AI accelerators also raise governance issues. Hardware used in medical, industrial, or autonomous systems must support traceability, verification, fail-safe behavior, and appropriate human oversight. Energy claims should report full-system boundaries, including cooling, conversion, programming, and manufacturing assumptions. Responsible research should disclose uncertainty and avoid presenting laboratory demonstrations as production-ready technologies.

11. Contemporary Research Directions and Best Practices

Current research increasingly emphasizes hybrid systems rather than single-device replacement. Examples include CMOS control with magnetic memory, ferroelectric transistors for embedded nonvolatile logic, 3D-stacked resistive arrays, superconducting processors coupled to cryogenic memory, and neuromorphic sensors connected directly to event-driven processors.

Best practices include:

• Define the target workload before selecting a device.
• Benchmark complete systems, including peripherals and data movement.
• Report distributions, endurance, retention, and temperature dependence.
• Use calibrated device models in circuit and architecture simulations.
• Co-design algorithms with device nonidealities.
• Separate demonstrated results from projections.
• Include manufacturing, packaging, security, and lifecycle considerations.
• Compare against a strong CMOS baseline using identical workload and technology assumptions.

Chapter Summary

Beyond-CMOS devices exploit physical states beyond conventional charge-based switching. Spintronic and magnetic devices provide nonvolatile storage and potentially novel logic. Ferroelectric devices encode information in polarization and support embedded and analog memory applications. Phase-change materials offer multilevel resistance and useful analog synaptic behavior but suffer drift and thermal-write constraints. RRAM and memristive systems enable dense crossbars and in-memory matrix operations, although variability and sneak paths remain major challenges. Superconducting devices provide exceptionally fast flux-based logic but require cryogenic infrastructure. Neuromorphic systems combine stateful devices with event-driven architectures for temporal and energy-efficient processing.

Technology selection must consider the complete system: latency, energy, density, endurance, retention, variability, converters, interconnects, cooling, yield, security, and workload characteristics. The most credible path is generally heterogeneous integration with CMOS, supported by device–circuit–architecture co-design and statistically rigorous evaluation.

Key Terms

Spintronics: Electronics that uses electron spin as an information variable.

Magnetic tunnel junction: Two magnetic electrodes separated by a tunnel barrier.

TMR: Relative resistance difference between antiparallel and parallel magnetic states.

MRAM: Nonvolatile memory based on magnetic states.

Ferroelectricity: Reversible spontaneous electric polarization in a material.

FeFET: Field-effect transistor containing a ferroelectric gate material.

Phase-change memory: Memory using reversible amorphous and crystalline phases.

Resistance drift: Time-dependent change in resistance after programming.

RRAM: Resistive random-access memory based on resistance switching.

Memristive system: Dynamic resistive system with history-dependent internal state.

Crossbar array: Grid of intersecting conductors containing devices at junctions.

Sneak path: Unintended current path through unselected memory cells.

In-memory computing: Computation performed within or adjacent to memory.

Neuromorphic computing: Computing inspired by neural event-driven processing.

Josephson junction: Superconducting weak link governed by phase-dependent current.

SFQ: Single-flux-quantum logic using quantized voltage pulses.

Endurance: Number of reliable switching or programming cycles.

Retention: Ability to preserve a state over time without refresh.

Variability: Deviation of device behavior across cycles, devices, or conditions.

Hybrid integration: Combining different device technologies in one system.

Review Questions

Short Answer Questions

1. What distinguishes volatile from nonvolatile memory?

2. Define tunnel magnetoresistance and identify the two magnetic configurations used in an MTJ.

3. Why is resistance drift important in phase-change memory?

4. What is a sneak path in a resistive crossbar?

5. State one major advantage and one major limitation of superconducting logic.

Long Answer Questions

1. Explain the structure, operation, advantages, and limitations of STT-MRAM and SOT-MRAM.

2. Compare FeRAM, FeFET, phase-change memory, and RRAM for embedded nonvolatile memory.

3. Explain how a resistive crossbar performs analog matrix-vector multiplication and discuss its nonidealities.

4. Describe the operating principles of Josephson junctions and SFQ logic, including the system implications of cryogenic operation.

5. Discuss why neuromorphic computing requires co-design of devices, circuits, architectures, and learning algorithms.

Analytical / Application Questions

1. A system performs frequent weight updates and requires very high endurance. Which of MRAM, phase-change memory, and RRAM would you initially favor, and what additional measurements would be required before making a final decision?

2. Design a comparative evaluation plan for an analog in-memory accelerator. Specify workload, baseline, energy boundary, accuracy metric, variability tests, and endurance tests.

3. A proposed crossbar has excellent device-level multiply–accumulate energy but requires high-resolution converters and frequent calibration. Analyze why its system-level energy advantage may disappear and propose two architectural remedies.

Multiple Choice Questions with Answers

Question 1

In an MTJ, which configuration generally has the lower resistance?

A. Parallel magnetization

B. Antiparallel magnetization

C. Random magnetization

D. Nonmagnetic magnetization

Correct Answer: A. Parallel magnetization

Question 2

What physical state is primarily used to store information in a ferroelectric memory cell?

A. Magnetic flux

B. Spontaneous electric polarization

C. Superconducting current only

D. Optical wavelength

Correct Answer: B. Spontaneous electric polarization

Question 3

Which phenomenon most directly complicates multilevel phase-change memory?

A. Resistance drift

B. Absence of hysteresis

C. Zero carrier mobility

D. Permanent superconductivity

Correct Answer: A. Resistance drift

Question 4

The idealized crossbar relation I_j = Σ_i G_ij V_i represents which operation?

A. Matrix-vector multiplication

B. Fourier transformation only

C. Clock synthesis

D. Magnetic domain nucleation

Correct Answer: A. Matrix-vector multiplication

Question 5

What is a major cause of variability in filamentary RRAM?

A. Random formation and rupture of conductive filaments

B. Perfectly uniform polarization reversal

C. Absence of ionic motion

D. Quantization of magnetic flux

Correct Answer: A. Random formation and rupture of conductive filaments

Question 6

Which quantity appears in the ideal Josephson voltage-phase relation?

A. Thermal conductivity only

B. Time derivative of phase difference

C. Gate oxide thickness only

D. Ferroelectric coercive field only

Correct Answer: B. Time derivative of phase difference

Question 7

Why are superconducting systems difficult to deploy widely?

A. They cannot switch rapidly

B. They require cryogenic operating conditions

C. They cannot represent binary information

D. They always have high DC resistance

Correct Answer: B. They require cryogenic operating conditions

Question 8

What is the principal purpose of a selector in a resistive memory array?

A. To increase sneak-path currents

B. To control unintended current through unselected cells

C. To eliminate all device variability

D. To convert magnetic states into photons

Correct Answer: B. To control unintended current through unselected cells

Question 9

Which application is especially suited to event-driven neuromorphic hardware?

A. Sparse temporal sensor processing

B. Only static file storage

C. Mechanical heat sinking

D. Crystal growth measurement exclusively

Correct Answer: A. Sparse temporal sensor processing

Question 10

Which criterion must be included in a credible system-level comparison of emerging memories?

A. Only the smallest reported device area

B. Only nominal switching speed

C. Peripheral circuits and data-conversion overhead

D. Only material composition

Correct Answer: C. Peripheral circuits and data-conversion overhead