Representative Legacy and Modern Architectures

Introduction

Microprocessor architecture is the organization of programmer-visible registers, instruction execution, memory addressing, interrupts, and system interfaces. Studying 8085, 8086, 8051, ARM Cortex-M, and RISC-V is valuable because these devices represent successive design priorities: educational simplicity, compatibility, embedded integration, low-power deterministic control, and open extensibility.

The 8085 and 8086 are historically important CISC-oriented processors. The 8051 is an influential 8-bit microcontroller with integrated memory and peripherals. ARM Cortex-M and RISC-V microcontrollers represent contemporary approaches based largely on load/store RISC principles. Comparing them requires more than comparing word sizes: bus organization, address-space rules, register conventions, interrupt entry, toolchains, and software compatibility all affect design decisions.

Learning objectives

After studying this chapter, the learner should be able to:

1. Describe the programmer-visible organization of the 8085, 8086, 8051, Cortex-M, and RISC-V.
2. Explain segmented addressing and the 8086 modulo-2²⁰ physical-address rule.
3. Compare memory models, instruction sets, and interrupt mechanisms.
4. Distinguish Cortex-M APSR, CONTROL, IPSR, EPSR, and xPSR roles.
5. Select an architecture for an embedded application and identify migration risks.

1. Architectural comparison framework

An architecture can be evaluated through six related questions:

• Data model: What is the natural operand width, and how are larger values represented?
• Register model: Which registers are general-purpose, special-purpose, or banked?
• Memory model: How are code, data, stack, and peripheral addresses represented?
• Instruction model: Are instructions fixed or variable length? Is memory directly operated on?
• Exception model: How are interrupts prioritized, vectored, acknowledged, and returned from?
• Compatibility model: What existing binaries, source languages, tools, and peripherals can be reused?

Word size alone is not a performance measure. A 32-bit processor may execute an 8-bit peripheral transaction, while an 8-bit microcontroller may efficiently control a relay or read a sensor.

Figure: Architectural layers that must be compared when selecting a processor.

2. The 8085 educational architecture

The 8085 is an 8-bit microprocessor with an 8-bit data bus and a 16-bit address capability, allowing up to 65,536 byte addresses. Its principal registers are accumulator A, general-purpose registers B, C, D, E, H, and L, the 16-bit program counter (PC), the 16-bit stack pointer (SP), and the flag register.

B–C, D–E, and H–L can form 16-bit register pairs. H–L is especially useful as a memory pointer. The accumulator is central to arithmetic, logic, rotate, and many data-transfer operations. The flags commonly used are Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY).

The 8085 has a unified 64 KiB memory address space. Its lower address lines are multiplexed with data lines, so external latches are needed to hold the low-order address during a bus cycle. I/O may be memory-mapped or accessed through a separate 8-bit I/O address space using IN and OUT instructions, depending on system design.

8085 instruction and interrupt characteristics

Instructions are variable length, generally one to three bytes. Operations include data transfer, arithmetic, logical manipulation, branching, stack operations, and machine control. The architecture is accumulator-oriented rather than a modern large-register load/store design.

Important hardware interrupt inputs include TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. TRAP has the highest priority and is non-maskable; the RST inputs are vectored; INTR is maskable and requires an external interrupting device to supply an instruction during interrupt acknowledge. EI and DI globally enable and disable maskable interrupts, while SIM and RIM support mask and status control. An interrupt service routine returns with RET, and software restart instructions provide fixed vector locations.

The 8085 is excellent for teaching fetch–decode–execute operation, flags, stack behavior, and bus timing. Its limitations include small address space, limited registers, slow memory access relative to modern systems, and lack of integrated peripherals.

3. The 8086: segmented memory and interrupt architecture

The 8086 has a 16-bit execution data path and a 20-bit physical address bus. Its visible registers are divided into:

• General registers AX, BX, CX, and DX; each can be accessed as two 8-bit halves.
• Pointer and index registers SP, BP, SI, and DI.
• Segment registers CS, DS, SS, and ES.
• Instruction pointer IP.
• FLAGS, containing status and control flags.

The 8086 uses a 1 MiB physical address space because the address bus has 20 lines. A logical address consists of a 16-bit segment and a 16-bit offset. The physical address is:

Here Segment and Offset are unsigned hexadecimal values in the range 0000H–FFFFH; multiplication by 16 means a four-bit left shift. The modulo operation is essential because the external bus carries only 20 address bits. Thus, addresses above FFFFFH wrap around to the bottom of the 1 MiB address space when the hardware implements the original 8086 bus behavior.

Worked example: ordinary segment calculation

For CS = 1234H and IP = 5678H:

16 × 1234H = 12340H

12340H + 5678H = 179B8H

Therefore the physical address is 179B8H, which is below FFFFFH and requires no wraparound.

Worked example: wraparound

For a logical address F000H:FFF0H:

16 × F000H = F0000H

F0000H + FFF0H = FFFF0H.

This still lies within the 20-bit range. However, for FFFFH:0010H:

16 × FFFFH = FFFF0H

FFFF0H + 0010H = 100000H.

Applying modulo 2²⁰ gives 00000H. The carry beyond bit 19 is discarded by the original 20-bit address bus.

Several logical addresses can refer to the same physical byte because segment bases overlap. For example, 1000H:0010H and 1001H:0000H both produce 10010H. This offers flexible relocation but complicates protection and debugging; original 8086 segmentation is not a privilege-based protection mechanism.

8086 instruction organization

The 8086 has variable-length instructions and supports register, immediate, direct, register-indirect, based, indexed, and based-indexed addressing. It permits memory operands in many instructions, unlike strict load/store RISC machines. The Bus Interface Unit fetches instruction bytes and maintains a six-byte prefetch queue, while the Execution Unit decodes and executes instructions. The queue can improve throughput but is invalidated by control transfers.

8086 interrupt architecture

The 8086 supports 256 interrupt types, numbered 00H through FFH. Each type uses a four-byte pointer in the interrupt vector table (IVT), which occupies physical addresses 00000H–003FFH. For interrupt type n, the vector begins at:

The first two bytes contain IP and the next two contain CS, using the processor's little-endian byte order.

Interrupts arise from three sources:

1. Internal exceptions: For example, type 0 is divide error, type 1 is single-step, type 3 is breakpoint, and type 4 is INTO overflow.
2. Non-maskable hardware interrupt: NMI invokes type 2 and cannot be disabled by the IF flag.
3. Maskable hardware interrupt: INTR is recognized when IF = 1. The external hardware supplies an interrupt type during interrupt acknowledge cycles.

Software can invoke a selected type with INT n. On entry, the processor pushes FLAGS, CS, and IP onto the stack, clears IF and TF for normal interrupt entry, and loads a new CS:IP from the IVT. The service routine completes with IRET, which restores IP, CS, and FLAGS. This differs from a normal near or far CALL because IRET restores the saved flag state and is specifically designed for interrupt return.

The 8086 interrupt design therefore combines fixed vector-table addressing, type-based dispatch, maskable and non-maskable sources, and stack-based context preservation. Applications must reserve the IVT, initialize stack memory, protect shared data, and ensure that an ISR preserves registers required by the calling convention.

4. The 8051 microcontroller

The classic 8051 combines processor, program memory interface, data memory, timers, serial communication, interrupt logic, and parallel I/O. It has an 8-bit CPU, a 16-bit program counter, an 8-bit stack pointer, and four register banks. Each bank contains R0–R7. The register-bank selection bits reside in the Program Status Word (PSW).

The accumulator A and B register support arithmetic and multiplication/division instructions. The Data Pointer (DPTR) is a 16-bit register used especially for table access and external memory addressing. The PSW includes Carry, Auxiliary Carry, Overflow, Parity, and bank-selection bits.

The traditional 8051 separates program and data address spaces. Code memory is addressed through a 16-bit program counter, while internal data RAM contains register banks, bit-addressable RAM, and general-purpose RAM. Special Function Registers occupy a defined upper portion of the internal data address space. This Harvard-like separation permits instructions such as MOVC for code-memory reads and MOVX for external data-memory transfers.

8051 interrupts commonly include external interrupt inputs, timer overflows, and serial-port events. The Interrupt Enable (IE) register controls global and individual enables; the Interrupt Priority (IP) register supports two priority levels in the classic device. A vector address identifies the service routine entry point. Device derivatives add sources and nesting features, so the exact interrupt map must be taken from the selected manufacturer's data sheet.

The 8051 remains useful in teaching bit manipulation, timers, serial interfaces, and resource-constrained control. Its limitations include a small register set, unusual memory spaces, compiler efficiency challenges, and substantial variation among modern derivatives.

5. ARM Cortex-M architecture

Cortex-M processors are 32-bit ARM microcontroller cores designed for embedded control. The programmer-visible register set generally includes R0–R12, SP (R13), LR (R14), and PC (R15). R13 may be represented as MSP or PSP depending on the selected stack pointer. LR holds a return value or an exception-return encoding. The architecture uses Thumb/Thumb-2 instructions; exact instruction availability depends on the Cortex-M profile.

Cortex-M systems are primarily load/store: arithmetic normally uses registers, while explicit load and store instructions access memory. Instructions are compact and can be 16 or 32 bits. Memory-mapped peripherals are accessed through ordinary load/store operations, subject to the processor's memory attributes and ordering rules.

Status and control registers: an essential distinction

The APSR contains condition flags used by instruction execution, such as N (negative), Z (zero), C (carry), and V (overflow); some profiles also implement Q (saturation). APSR is not the complete control or exception-state register.

The IPSR identifies the currently executing exception number. The EPSR contains execution-state information, including Thumb state and control-flow-related state bits. The xPSR is the combined programmer's view of APSR, IPSR, and EPSR. The CONTROL register selects privilege and, where implemented, the active stack pointer. Thus, control and exception state must not be attributed solely to APSR.

Cortex-M exception entry automatically saves a basic stack frame containing R0–R3, R12, LR, PC, and xPSR. The processor obtains a handler address from the vector table, changes execution state as specified by the architecture, and can return using an exception-return mechanism encoded in LR. This hardware stacking reduces common ISR prologue overhead and supports nested exceptions.

The Nested Vectored Interrupt Controller (NVIC) provides configurable interrupt enable, pending, active, priority, and vectoring functions. Priority grouping and implemented priority bits vary by core. System exceptions include reset, NMI, hard fault, and system service exceptions; exact sets vary across Cortex-M generations. The vector table can generally be relocated through the Vector Table Offset Register, subject to implementation restrictions.

6. RISC-V microcontroller architecture

RISC-V is an open instruction-set architecture rather than one single processor. A microcontroller may implement RV32I, the base 32-bit integer ISA, plus extensions such as M for multiplication/division, A for atomics, C for compressed instructions, and other vendor or standard extensions. The exact implemented extensions must be read from the hart and platform documentation.

The base integer ISA has 32 integer registers x0–x31; x0 is hard-wired to zero. Register x1 is conventionally the return-address register, and x2 is conventionally the stack pointer, although software conventions are defined by the ABI rather than enforced by the hardware. The program counter is architecturally distinct from the integer register file.

RISC-V is primarily load/store. RV32I instructions are normally 32 bits, while the C extension adds 16-bit compressed encodings. Control and Status Registers (CSRs) hold machine state. Common machine-mode interrupt registers include mstatus, mie, mip, mtvec, mepc, mcause, and mtval, but implementation and privilege level determine which are present. Interrupt delegation may route selected events to supervisor mode in systems that implement it.

At trap entry, the machine saves a return PC in mepc, records the cause in mcause, may record additional information in mtval, and transfers control according to mtvec. Software saves the general registers it needs and returns with an appropriate xRET instruction. Unlike Cortex-M, RISC-V does not impose one universal NVIC-like interrupt controller: platforms commonly use a local timer/software interrupt block and an external interrupt controller such as the platform-defined PLIC, but details vary.

7. Comparative analysis

A fair comparison must distinguish ISA from implementation. “ARM” does not identify one memory size, cache arrangement, or peripheral set; “RISC-V” likewise identifies an ISA family, not a complete board-level system.

8. Compatibility and migration considerations

Migration is not simply recompiling source code. The following layers must be audited:

1. Data representation: Check integer width, alignment, endianness, pointer size, and volatile access.
2. Assembly and ABI: Rewrite assembly, startup code, interrupt wrappers, calling conventions, and context-switch code.
3. Memory map: Replace 8086 segments or 8051 code/data assumptions with linker-defined regions and memory-protection or privilege rules where available.
4. Interrupts: Map vector numbers, acknowledge/clear mechanisms, priority semantics, nesting, and return sequences. Never copy an ISR prologue from one architecture to another.
5. Peripherals: Timers, UARTs, GPIO registers, clock trees, DMA, and reset behavior are vendor-specific.
6. Timing: Replace instruction-count delays with timer-based delays. Pipelines, caches, flash wait states, and compiler optimization make legacy delay loops unreliable.
7. Toolchain: Validate compiler ABI, linker scripts, startup files, debugger support, and unit tests.
8. Verification: Test boundary arithmetic, interrupt races, watchdog recovery, brownout behavior, and electromagnetic operating conditions.

Legacy binary compatibility is strongest within the original ISA family. An 8086 binary does not execute natively on Cortex-M or RISC-V. Source-level portability improves when hardware access is isolated behind a hardware-abstraction layer, but abstractions cannot remove differences in interrupt latency, memory ordering, atomicity, or peripheral behavior.

9. Applied case: migrating an educational 8051 controller

Background

Consider an illustrative laboratory controller that reads a temperature sensor, drives a fan, and transmits measurements over a serial link. Its original implementation uses an 8051 timer interrupt, a serial interrupt, bit-addressable flags, and a polling loop.

Problem

The 8051 derivative is obsolete. The replacement must support a faster control loop, lower energy consumption, and a maintained compiler ecosystem. A Cortex-M0+-class device and an RV32I-class device are candidates.

Analysis

The original code cannot be transferred directly. The 8051 register-bank assumptions, SFR addresses, interrupt vectors, timer modes, and serial registers have no architectural meaning on either candidate. The control algorithm itself—sample, filter, compare threshold, actuate, transmit—can be retained if expressed in portable C.

Approach and solution

The engineering team first specifies timing requirements: sensor sampling every 10 ms, serial transmission at a selected baud rate, and a maximum control-response latency. A hardware timer generates the sampling event; the ISR records a timestamp and sets a flag, while heavier filtering runs in the main context. UART access is encapsulated in a driver. Shared variables are declared volatile, and multi-byte data exchanged between ISR and main code is protected by an appropriate atomic or critical-section mechanism.

On Cortex-M, the vector table and NVIC priorities are configured, and the startup code establishes MSP before enabling interrupts. On RISC-V, mtvec and the platform interrupt controller are configured, and the trap handler dispatches according to mcause. In both cases, the data sheet—not ISA documentation alone—determines timer and UART registers.

Outcome

The portable application logic is reused, while startup, drivers, linker configuration, and interrupt dispatch are rewritten. Tests confirm that timer jitter, serial loss, reset recovery, and sensor fault handling satisfy requirements. The migration succeeds because architectural dependencies were isolated rather than because the instruction sets were assumed equivalent.

Learning points

• Preserve behavior, not register-level code.
• Treat interrupt entry and peripheral acknowledgement as architecture-specific.
• Specify timing and safety requirements before selecting a replacement.
• Use vendor documentation for implementation details and ISA manuals for architectural rules.

10. Limitations, safety, and professional practice

Educational processors simplify important realities. Actual systems include clock tolerances, bus contention, metastability, non-ideal reset circuits, flash wait states, watchdogs, security states, and certification constraints. A correct instruction-level design can still fail if an input is not synchronized or an interrupt flag is cleared incorrectly.

For safety-related systems, engineers should apply a documented hazard analysis, requirements traceability, defensive programming, watchdog strategy, fault logging, and independent verification. Interrupt handlers should be short, reentrant where required, and explicit about shared-state ownership. Security-sensitive designs must also consider privilege separation, secure boot, debug-port control, firmware update authenticity, and protection of secrets. These concerns are not automatically solved by choosing ARM or RISC-V.

Contemporary developments include TrustZone-M or equivalent security mechanisms on selected ARM profiles, RISC-V privilege and security extensions, real-time operating systems, formal verification of small control components, and hardware-assisted isolation. Such features are optional or implementation-specific; claims must always be checked against the selected core and chip.

Best-practice checklist

• Read the exact processor-core and microcontroller data sheets.
• Draw the memory map before writing drivers.
• Document every interrupt source, priority, flag-clear rule, and maximum latency.
• Use symbolic register definitions and reviewed linker scripts.
• Avoid undocumented instruction behavior and timing assumptions.
• Test reset, overflow, wraparound, nested interrupts, and illegal accesses.
• Separate portable application logic from architecture-specific startup and drivers.
• Record the target ISA extensions and ABI in the build system.

Chapter Summary

The 8085 introduces accumulator operation, flags, register pairs, a 64 KiB unified memory space, and fixed interrupt inputs. The 8086 extends the educational model with a 20-bit physical bus, segmented logical addresses, variable-length CISC instructions, prefetching, and a 256-entry interrupt vector table. Its physical-address equation requires modulo 2²⁰ behavior because addresses beyond FFFFFH wrap on the original bus.

The 8051 integrates CPU, memory organization, timers, serial communication, GPIO, and vectored interrupts. Cortex-M provides a 32-bit Thumb load/store architecture, automatic exception stacking, and NVIC-based interrupt control; APSR contains condition flags, whereas CONTROL, IPSR, EPSR, and the combined xPSR provide control and exception-state views. RISC-V supplies an extensible open ISA with general registers, CSRs, and platform-dependent interrupt systems.

Migration requires analysis of data representation, ABI, memory maps, interrupts, peripherals, timing, tools, and verification. Portable algorithms can often be retained, but startup code, drivers, vectoring, and low-level synchronization must be redesigned.

Key Terms

Architecture: Programmer-visible organization of a processor.

Accumulator: Central arithmetic and logic register in architectures such as 8085 and 8051.

ABI: Application Binary Interface defining calling conventions and binary interoperability.

APSR: Cortex-M application status register containing condition flags.

CSRs: RISC-V control and status registers.

Cortex-M: ARM embedded processor family for microcontroller applications.

Exception: Synchronous or asynchronous event requiring controlled transfer of execution.

Interrupt vector table: Memory structure containing interrupt or exception entry addresses.

IVT: The 8086 interrupt vector table at physical addresses 00000H–003FFH.

Load/store architecture: ISA in which memory is accessed primarily by explicit load and store instructions.

Memory-mapped I/O: Peripheral registers assigned addresses in the processor memory map.

NVIC: Nested Vectored Interrupt Controller in Cortex-M systems.

Physical address: Address placed on a processor's external or internal memory interface.

RISC: Reduced Instruction Set Computer design approach.

Segment: 8086 16-bit value used to form a shifted logical-address base.

SFR: Special Function Register in an 8051-style microcontroller.

Thumb: ARM compact instruction encoding used by Cortex-M.

Trap: RISC-V term for an exception or interrupt transfer to a handler.

Wraparound: Reduction of an address modulo the address-space size.

Review Questions

Short Answer Questions

1. Why does the 8086 physical-address calculation require modulo 2²⁰?
2. Name the principal register groups of the 8085.
3. What is the function of the 8051 DPTR?
4. Distinguish APSR from CONTROL in Cortex-M.
5. What information is recorded in the RISC-V mcause CSR?

Long Answer Questions

1. Compare the 8085 and 8086 memory and interrupt architectures.
2. Explain the 8086 interrupt sequence from recognition through IRET.
3. Describe the 8051 memory spaces, register banks, and interrupt organization.
4. Explain Cortex-M exception entry and the roles of APSR, IPSR, EPSR, xPSR, and CONTROL.
5. Compare Cortex-M and RISC-V migration issues for a timer-driven embedded application.

Analytical / Application Questions

1. Calculate the 8086 physical address for ABCDH:1234H and determine whether wraparound occurs.
2. An ISR shares a 32-bit counter with foreground code on an 8-bit 8051. Explain why a simple read may be unsafe and propose a synchronization method.
3. Select between a Cortex-M and RISC-V microcontroller for a new product whose main priorities are an established safety-certified toolchain versus ISA openness. State the additional evidence required before deciding.

Multiple Choice Questions with Answers

Question 1

For the original 8086, what is the physical address of FFFFH:0010H?

A. FFFF0H

B. 100000H

C. 00000H

D. 00010H

Correct Answer: C. 00000H

Question 2

Which structure occupies physical addresses 00000H–003FFH in the 8086?

A. The six-byte prefetch queue

B. The interrupt vector table

C. The stack segment

D. The 8051 SFR area

Correct Answer: B. The interrupt vector table

Question 3

Which Cortex-M register contains condition flags such as N, Z, C, and V?

A. APSR

B. CONTROL

C. IPSR

D. NVIC

Correct Answer: A. APSR

Question 4

Which Cortex-M register identifies the currently executing exception number?

A. EPSR

B. IPSR

C. APSR

D. LR

Correct Answer: B. IPSR

Question 5

Which 8051 feature directly supports selection among its register banks?

A. The DPTR high byte

B. PSW bank-selection bits

C. The serial buffer

D. The external interrupt pin

Correct Answer: B. PSW bank-selection bits

Question 6

What is the defining memory-access characteristic of a load/store architecture?

A. All arithmetic must use memory operands

B. Only the stack can be addressed

C. Explicit load and store instructions access memory

D. Code and data must share one physical segment

Correct Answer: C. Explicit load and store instructions access memory

Question 7

In the 8086, which event is non-maskable by the IF flag?

A. INTR

B. INT 21H

C. NMI

D. Single-step trap

Correct Answer: C. NMI

Question 8

Which RISC-V register is hard-wired to zero in the base integer register set?

A. x0

B. x1

C. x2

D. x31

Correct Answer: A. x0

Question 9

For an 8086 logical address 1234H:5678H, what is the physical address?

A. 1234H

B. 179B8H

C. 18AACH

D. 05678H

Correct Answer: B. 179B8H

Question 10

Which action is generally required when migrating an 8051 interrupt routine to Cortex-M or RISC-V?

A. Copying the original SFR addresses unchanged

B. Keeping the original register-bank instructions

C. Rewriting vectoring, peripheral access, and interrupt entry code

D. Removing all timing requirements

Correct Answer: C. Rewriting vectoring, peripheral access, and interrupt entry code