Memory Systems and Address Decoding

Introduction

A processor communicates with program storage, working memory, nonvolatile storage, and peripheral registers through an address space. Designing this subsystem requires more than selecting a memory device with sufficient capacity. The engineer must establish an unambiguous memory map, generate valid chip-select signals, accommodate electrical and timing constraints, handle different bus widths, and ensure that cache, direct memory access (DMA), and protection mechanisms preserve system correctness.

Address-decoding errors can cause multiple devices to drive the bus simultaneously, produce unintended address aliases, or expose security-critical registers. Timing errors may be intermittent and temperature-dependent. Memory-system design must therefore combine logical decoding, interface design, timing analysis, firmware awareness, and validation.

Learning Objectives

After studying this chapter, students should be able to:

• compare RAM, ROM, Flash, EEPROM, cache, and memory-mapped devices;
• calculate memory capacity and address ranges;
• design full and partial address decoders;
• interface memories having different data-bus widths;
• construct and validate a memory map;
• analyze asynchronous read and write timing;
• determine required wait states;
• explain alignment, endianness, cache coherence, and DMA interactions;
• apply MPU/MMU protection attributes; and
• diagnose common memory-interface failures.

1. Memory-System Organization

A byte-addressable processor assigns one address to each byte. If it provides n physical address lines, its theoretical byte-address space is

where C is the address-space capacity and n is the number of independently decoded address bits. This is an address-space limit, not necessarily the amount of installed physical memory.

For example, 32 address bits identify 2³² bytes, or 4 GiB. Some locations may contain RAM, others may select peripheral registers, while large regions may be unimplemented.

Figure: The processor supplies address and access information to the decoder; decoder outputs select the target devices, while the controller manages timing and data transfer.

A chip select does not originate from a memory device. It is generated by decoding processor address and control information. In integrated microcontrollers, the decoder and memory controller may be internal, but their logical functions remain distinct.

2. Memory Technologies and Interface Characteristics

Memory-mapped registers must normally be marked as device or strongly ordered memory. Speculative reads, caching, or access reordering can be unsafe because reading a register may clear a flag and writing it may start an operation.

2.1 SRAM

Asynchronous SRAM commonly provides address inputs, bidirectional data pins, chip enable \overline{CE}, output enable \overline{OE}, and write enable \overline{WE}. During a read, the selected SRAM drives data only when chip and output enables are active. During a write, the processor or controller drives the data bus while the SRAM output drivers remain disabled.

2.2 ROM

A parallel ROM requires address, data-output, chip-select, and output-enable connections. Because no ordinary write cycle exists, accidental processor writes must not activate the device. Mask ROM offers low unit cost at high volume but cannot be field-updated. EPROM and one-time-programmable devices have similar read interfaces but different programming processes.

2.3 Flash

Parallel NOR Flash can often support execute-in-place because individual addresses are readable. Programming requires command sequences and obeys one-way bit transitions until an erase restores an entire sector. NAND Flash is generally accessed through a controller that performs page transfers, bad-block management, and error correction.

A Flash interface may additionally use reset, ready/busy, write-protect, and byte/word-mode pins. Power-failure-safe firmware must not assume that a program or erase operation is atomic.

2.4 EEPROM

EEPROM supports fine-grained updates but has millisecond-scale write cycles and finite endurance. After initiating a write, firmware should poll a ready/busy indication or status bit rather than holding the processor bus active for the entire internal programming interval. Page boundaries must be respected because some devices wrap data written beyond a page.

3. Address Ranges and Memory Maps

A device containing N byte locations occupies N consecutive byte addresses. If its base address is B, its inclusive final address is

where E and B are byte addresses. A naturally aligned power-of-two region of size 2^k has its lowest k address bits equal to zero at the base.

Worked Example 1: Constructing a Region

A 128 KiB SRAM is assigned base address 0x2000_0000. Since 128 KiB = 2¹⁷ bytes,

The SRAM therefore occupies 0x2000_0000–0x2001_FFFF. Address bits A16:0 select bytes inside the device; higher bits identify the region.

A memory map is a design contract shared by hardware, linker scripts, startup software, device drivers, debuggers, and protection configuration. Reserved gaps are valuable for expansion and for detecting invalid accesses.

4. Address-Decoding Methods

4.1 Full Decoding

Full decoding uses every address bit needed to distinguish the assigned region from all other regions. A useful mask comparison is

where A is the current address, B is the required base pattern, and mask M contains 1s in all bits that must match. This expression applies when the region can be described by fixed address bits; arbitrary non-power-of-two ranges may require magnitude comparators or multiple masked regions.

For a 64 KiB region beginning at 0x4002_0000, the mask is 0xFFFF_0000. The decoder selects the device when

4.2 Partial Decoding and Aliasing

Partial decoding ignores one or more significant address bits. It reduces hardware but causes the same device to appear at multiple addresses. If r relevant bits are omitted, up to 2^r aliases may result, assuming those bits vary independently and no other logic constrains them.

Aliasing complicates debugging and memory protection. It is acceptable only when intentionally documented and when every alias receives equivalent protection and cache attributes.

4.3 Hierarchical Decoding

A high-level decoder may first select a broad region, after which local logic selects an individual device or register. Programmable logic devices, FPGA fabric, comparators, and integrated bus interconnects are common implementations. Decoder propagation delay must be included in timing analysis.

5. Detailed Device-Interface Designs

5.1 Two 8-Bit ROMs on a 16-Bit Byte-Addressed Bus

Suppose a processor has a 16-bit data bus, byte addresses, and two byte-enable signals. Two 64K × 8 ROMs are used to form a 128 KiB, 16-bit-wide program region at 0x0000_0000–0x0001_FFFF.

Connections are as follows:

• CPU A16:1 connect to A15:0 on both ROMs.
• The low ROM connects to D7:0; the high ROM connects to D15:8.
• The low-byte strobe enables the low ROM, and the high-byte strobe enables the high ROM.
• The region select is true when CPU A31:17 are all zero.
• CPU read control drives the ROM output-enable input through correctly polarized logic.
• Write control is not connected to a programming function.

CPU A0 is not an internal ROM address bit. It participates in byte-lane selection because incrementing a byte address changes lanes before advancing the 16-bit word index. At address 0x0000_0000, the low ROM supplies the first byte and the high ROM supplies the second byte on a full-word read. This example assumes little-endian byte ordering; the physical lane assignment must match the processor architecture.

5.2 Parallel NOR Flash Interface

Consider a 1 MiB × 8 NOR Flash mapped at 0x0800_0000–0x080F_FFFF on an 8-bit external bus:

• CPU/controller A19:0 connect to Flash A19:0.
• Flash D7:0 connect to the external data bus.
• A region comparator asserts \overline{CS} only for the assigned 1 MiB interval.
• Read control generates \overline{OE}, and write control generates \overline{WE}.
• Reset and write-protect pins are driven to defined states.
• Ready/busy, if available, connects to the controller or an interrupt-capable input.

Firmware must issue the manufacturer-defined unlock, program, or erase command sequence. During sector erase, reads from the affected bank may be unavailable. A dual-bank device or RAM-resident update routine may therefore be necessary. The memory controller must add sufficient read wait states for the Flash access time, especially during execute-in-place operation.

5.3 EEPROM Interface

A 32 KiB × 8 parallel EEPROM assigned to 0x6000_0000–0x6000_7FFF uses A14:0 as internal address inputs. The upper address comparator produces chip select. D7:0 form the data path, while read and write strobes drive output-enable and write-enable.

If the EEPROM specifies a 5 ms maximum internal write time, the external bus write pulse still lasts only long enough to latch the address and data. Firmware then releases the bus and polls completion. Holding the processor in wait for 5 ms would waste many thousands of cycles and might block real-time tasks.

Software should implement wear reduction, checksums, version fields, and redundant records. For example, alternating between two records with monotonically increasing sequence numbers permits recovery after power loss.

5.4 Bus-Width Conversion

A 32-bit bus may be connected to four 256K × 8 SRAM devices to form 1 MiB of 32-bit memory:

• chip 0 connects to D7:0;
• chip 1 connects to D15:8;
• chip 2 connects to D23:16;
• chip 3 connects to D31:24;
• CPU A19:2 connect to A17:0 of every SRAM;
• four byte-enable signals independently control the four chips; and
• CPU A1:0 identify byte lanes and are represented by those byte enables rather than SRAM address pins.

Each word location contains four bytes. There are 2¹⁸ word locations, giving 2¹⁸ × 4 = 2²⁰ bytes, or 1 MiB.

Connecting only one 8-bit device to a 32-bit processor requires either byte-only accesses or a bus bridge that performs four 8-bit transfers for one 32-bit request. Such conversion increases latency and must preserve byte order. A bridge must also handle unaligned operations that cross device or word boundaries.

6. Alignment, Endianness, and Access Semantics

An access of s bytes is naturally aligned when

where A is the byte address and s is generally 1, 2, 4, or 8 bytes. Thus, a 32-bit word is naturally aligned at an address divisible by four.

Some processors split unaligned accesses into multiple bus transactions; others generate an alignment fault. An unaligned word spanning two devices or a protected boundary can produce non-atomic and unsafe behavior.

Endianness specifies how multibyte values map to ascending byte addresses. In a little-endian system, the least significant byte occupies the lowest address. Endianness does not reverse bits within each byte.

Peripheral registers may restrict legal transfer sizes. A byte write to a 32-bit command register might be ignored or interpreted differently from a full-word write. The device specification, not merely the CPU instruction set, determines legality.

7. Timing Analysis and Wait States

In an asynchronous read, the processor launches an address, decoding and propagation occur, the memory produces data, and the processor samples it. A conservative timing condition is

where:

• t_DEC is maximum decoder delay;
• t_ACC is maximum memory access time under specified voltage and temperature;
• t_PATH is board/controller path delay;
• N is the number of clock periods allowed;
• T_CLK is the clock period;
• t_LAUNCH is delay before address/control become valid; and
• t_SU is the processor input setup requirement.

The inequality assumes these delays lie serially on the critical path. A device specification may instead define access time from chip select or output enable; the correct worst-case path must then be constructed from the applicable timing parameters rather than summing unrelated maxima.

Worked Example 2: Wait-State Calculation

An 80 MHz bus has

Let t_DEC=2 ns, t_ACC=12 ns, t_PATH=1 ns, t_LAUNCH=2 ns, and t_SU=1 ns. The required data-path time is 15 ns. For one clock period, the available time is

which is insufficient. For two periods, the available time is

Therefore, the transfer requires two clock periods, corresponding to one added wait state if the normal transfer occupies one period.

Write analysis must separately verify write-pulse width, address setup, data setup, and hold times. Read timing success does not prove write timing success.

8. Cache Organization and Coherence

A cache stores recently used blocks to reduce average access latency. If h is the hit ratio, t_C is cache-hit time, and t_M is the additional miss penalty, then a simplified average memory access time is

This model assumes one cache level and defines miss penalty as additional time after hit lookup. Multilevel caches require a recursive or expanded model.

Caches may be direct-mapped, set-associative, or fully associative. Write-through caches immediately propagate writes to lower memory; write-back caches defer propagation until eviction or explicit cleaning.

Memory-mapped I/O must not normally be cached. Instruction and data caches also matter during self-programming: after changing executable code, software may need to clean the data cache, invalidate the instruction cache, and execute architecture-defined synchronization barriers.

9. DMA and Memory Consistency

DMA transfers data without having the CPU execute each load and store. A DMA controller becomes a bus master, arbitrates for access, and reads or writes memory directly. Key design issues include:

• whether the DMA engine can address the entire physical memory range;
• burst length and bus arbitration latency;
• transfer alignment and boundary restrictions;
• cache coherence; and
• protection from unauthorized device access.

In a non-coherent write-back system, CPU-modified cache lines may not yet exist in RAM when DMA begins reading. The CPU must clean those lines first. Before the CPU consumes data written by DMA, it must invalidate corresponding stale cache lines. These operations require correctly aligned ranges and memory barriers.

An input-output memory management unit (IOMMU) can restrict DMA to approved buffers. Without such control, a defective or malicious peripheral may overwrite code, credentials, or control structures.

10. Memory Protection and System Safety

A memory protection unit (MPU) defines regions using base addresses, sizes, access permissions, privilege levels, and memory attributes. A memory management unit (MMU) translates virtual addresses through page tables and also controls permissions and caching.

A defensible embedded policy typically makes:

• executable Flash read-only during normal operation;
• RAM writable but non-executable where supported;
• peripheral space privileged and non-cacheable;
• unused regions inaccessible;
• secret storage inaccessible to untrusted tasks; and
• DMA buffers explicitly bounded.

Overlapping MPU regions require careful attention to the architecture's priority rules. Every alias created by partial decoding must receive equivalent protection; otherwise, an attacker may bypass a protected address through an unprotected alias.

Secure boot, signed firmware updates, rollback prevention, and controlled debug access extend memory protection beyond ordinary access permissions. Privacy-sensitive data should be erased when no longer required, while safety-critical logs may require retention and tamper evidence.

11. Applied Case: Industrial Data-Logger Controller

Background

This is an illustrative case. A 32-bit industrial data logger executes firmware from internal Flash, buffers sensor samples in SRAM, stores field-update images in external NOR Flash, and preserves calibration constants in EEPROM. A DMA-capable ADC continuously fills sample buffers.

Problem

Early prototypes occasionally record corrupted samples after DMA completion. Firmware updates also fail when code attempts to execute from the same Flash bank being erased. The initial decoder uses incomplete high-order address decoding, creating undocumented aliases.

Analysis

The revised map is:

Corrupted samples result from stale cache lines: DMA writes SRAM, but the CPU reads an older cached copy. Flash-update failure results from fetching instructions from a bank temporarily unavailable during erase. Partial decoding allows external storage to respond at several unintended addresses.

Approach and Solution

The team implements full high-order address decoding, validates that only one chip select can be active, and assigns reserved regions as faulting addresses. DMA buffers are cache-line aligned. Before an output DMA operation, software cleans the buffer; after an input DMA operation, it invalidates the buffer and executes the required barrier.

The Flash programming routine is copied to SRAM, interrupts whose handlers reside in the affected Flash bank are disabled or relocated, and ready/busy status is polled. EEPROM records use duplicate slots, sequence counters, and checksums. The MPU marks SRAM non-executable and peripheral windows privileged and non-cacheable.

Timing analysis reveals that external NOR Flash requires one wait state at the selected bus frequency. Validation is performed at supply and temperature limits, not merely under laboratory nominal conditions.

Outcome

DMA corruption is eliminated, update recovery survives controlled power interruptions, aliases disappear, and invalid accesses produce diagnosable faults.

Learning Points

A reliable memory subsystem depends on coordinated decoding, timing, cache maintenance, update strategy, and protection. Correct wiring alone is insufficient.

12. Validation, Challenges, and Best Practices

Important practical challenges include voltage compatibility, output-drive contention, propagation-delay variation, signal integrity, reset-state uncertainty, endurance limits, and undocumented software assumptions.

Recommended practices are:

1. Maintain one authoritative memory-map document.
2. Decode enough address bits to prevent unintended aliases.
3. Prove that mutually exclusive chip selects cannot overlap.
4. Analyze read and write timing independently using worst-case data-sheet values.
5. Tie unused control inputs to defined logic levels.
6. Apply non-cacheable device attributes to peripheral registers.
7. Specify legal access widths and alignment.
8. Test byte lanes using asymmetric patterns such as 0x12, 0x34, 0x56, and 0x78.
9. Test DMA with cache enabled and disabled.
10. Include brownout and interrupted-write tests for nonvolatile storage.
11. Verify MPU/MMU and IOMMU settings during startup.
12. Use logic analyzers or oscilloscopes to confirm chip-select, strobe, data, and ready timing.

Contemporary systems increasingly integrate ECC, memory encryption, secure enclaves, coherent interconnects, and serial memories such as OSPI Flash. These technologies change implementation details but retain the fundamental requirements of unique selection, valid timing, consistent attributes, and controlled access.

Chapter Summary

A memory subsystem maps processor addresses to storage devices and peripheral registers. Full address decoding prevents aliases and bus contention, while a documented memory map coordinates hardware and software. ROM, Flash, EEPROM, and RAM differ in programming method, timing, endurance, and control requirements. Bus-width conversion requires deliberate address and byte-lane connections.

Timing analysis must account for launch, decode, device, path, and setup delays; wait states are added when one bus period is insufficient. Alignment and endianness determine how multibyte values occupy byte lanes. Cache and DMA improve performance but require coherence operations in non-coherent systems. MPU, MMU, and IOMMU controls enforce permissions, memory attributes, and DMA isolation. Robust designs combine worst-case analysis with measurement, fault testing, and disciplined documentation.

Key Terms

Address decoder: Logic that recognizes an address region and generates chip-select or routing signals.

Address alias: A second address that unintentionally or intentionally selects the same physical location.

Alignment: Placement of data at an address compatible with its transfer size.

Byte enable: A signal selecting a particular byte lane during a transfer.

Cache: Small fast memory that stores copies of recently accessed blocks.

Chip select: A control signal that activates one memory or peripheral device.

DMA: Direct transfer between a peripheral and memory without instruction-by-instruction CPU involvement.

EEPROM: Electrically erasable nonvolatile memory supporting fine-grained updates.

Endianness: Ordering of bytes of a multibyte value in memory.

Flash memory: Nonvolatile memory programmed electrically and erased in sectors or blocks.

Full decoding: Address decoding that distinguishes a device throughout the entire relevant address space.

IOMMU: Hardware that translates and protects addresses generated by I/O devices.

Memory map: Assignment of address ranges to memories and devices.

MMU: Hardware that translates virtual addresses and enforces page permissions and attributes.

MPU: Region-based hardware for enforcing access permissions and memory attributes.

Partial decoding: Decoding that ignores relevant address bits and may create aliases.

SRAM: Volatile random-access memory implemented without refresh.

Wait state: An additional bus clock period inserted to accommodate a slower target.

Write endurance: Number of program or erase cycles a nonvolatile memory can reliably tolerate.

Review Questions

Short Answer Questions

1. Distinguish address-space capacity from installed physical memory.
2. Why should memory-mapped peripheral registers normally be non-cacheable?
3. What is the difference between full and partial address decoding?
4. Why is CPU A0 often used for byte-lane selection on a 16-bit byte-addressed bus?
5. What cache operation is normally required before a non-coherent DMA engine reads a write-back cached buffer?

Long Answer Questions

1. Explain the interface requirements and operational differences of SRAM, ROM, NOR Flash, and EEPROM.
2. Describe how four 8-bit memories can implement a 32-bit memory bank, including address and byte-enable connections.
3. Develop a worst-case asynchronous read timing analysis and explain how wait states are selected.
4. Discuss how MPU, MMU, and IOMMU mechanisms protect a memory subsystem.
5. Explain the causes and consequences of cache incoherence during DMA transfers and propose a safe software sequence.

Analytical / Application Questions

1. Design a decoder and interface for a 256 KiB × 16 ROM beginning at 0x1000_0000 on a 32-bit processor bus. State the address range, lane connections, and legal access sizes.
2. A 100 MHz bus has 1.5 ns launch delay, 2 ns decode delay, 14 ns memory access time, 1 ns path delay, and 1 ns setup time. Determine the minimum number of clock periods and added wait states for a transfer whose baseline length is one period.
3. Construct a memory map for a controller containing 1 MiB Flash, 256 KiB SRAM, a 64 KiB peripheral region, and 2 MiB external storage. Justify alignment, cache attributes, permissions, and reserved gaps.

Multiple Choice Questions with Answers

Question 1

A byte-addressable processor has 20 fully decoded address lines. What is its theoretical address-space capacity?

A. 64 KiB

B. 1 MiB

C. 2 MiB

D. 20 MiB

Correct Answer: B. 1 MiB

Question 2

A 128 KiB device begins at address 0x2000_0000. What is its inclusive final address?

A. 0x2000_FFFF

B. 0x2001_FFFE

C. 0x2001_FFFF

D. 0x2002_0000

Correct Answer: C. 0x2001_FFFF

Question 3

Which processor signals should provide the information used by an address decoder?

A. Address and access-control signals

B. Only data outputs from Flash

C. Only data outputs from RAM

D. The EEPROM ready/busy output alone

Correct Answer: A. Address and access-control signals

Question 4

Two 64K × 8 ROMs form a 16-bit-wide, byte-addressed bank. Which processor address lines normally connect to ROM A15:0?

A. A15:0

B. A16:1

C. A17:2

D. A31:16

Correct Answer: B. A16:1

Question 5

Four 256K × 8 SRAMs are connected in parallel as four byte lanes. What total storage capacity results?

A. 256 KiB

B. 512 KiB

C. 1 MiB

D. 4 MiB

Correct Answer: C. 1 MiB

Question 6

An 80 MHz bus allows 9.5 ns of usable data-path time in one period, but decoding, memory, and routing require 15 ns. Two periods provide 22 ns. How many added wait states are needed if the baseline transfer is one period?

A. Zero

B. One

C. Two

D. Three

Correct Answer: B. One

Question 7

Which address is naturally aligned for a 32-bit access?

A. 0x2000_0001

B. 0x2000_0002

C. 0x2000_0003

D. 0x2000_0004

Correct Answer: D. 0x2000_0004

Question 8

Before a non-coherent DMA controller reads a buffer modified in a write-back CPU cache, the CPU should normally do what?

A. Invalidate the buffer without writing it back

B. Clean the buffer's cache lines to memory

C. Mark the peripheral region executable

D. Erase the corresponding Flash sector

Correct Answer: B. Clean the buffer's cache lines to memory

Question 9

What is a direct consequence of omitting one independently varying address bit from a partial decoder?

A. The device may appear at two address aliases

B. The device capacity necessarily doubles

C. All accesses become naturally aligned

D. The data bus becomes one bit wider

Correct Answer: A. The device may appear at two address aliases

Question 10

Why should an EEPROM write routine poll completion instead of holding the processor bus for the entire internal programming interval?

A. EEPROM can only be read through DMA

B. The internal write can take milliseconds after the bus cycle has completed

C. Polling increases the EEPROM data-bus width

D. The processor address must remain unchanged permanently

Correct Answer: B. The internal write can take milliseconds after the bus cycle has completed