Input/Output and Peripheral Interfacing

Introduction

A microprocessor or microcontroller becomes useful only when it can observe and influence its environment. Input/output (I/O) interfaces connect software to switches, keyboards, displays, sensors, motors, relays, converters, and communication circuits. Successful interfacing therefore requires more than writing peripheral registers: the designer must satisfy voltage, current, timing, noise, loading, protection, and software-response requirements.

This chapter develops a systematic approach to peripheral interfacing. It covers general-purpose digital I/O (GPIO), keyboard matrices, displays, sensors, actuators, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), timers, counters, pulse-width modulation (PWM), and motor drivers. Particular attention is given to polling, switch debouncing, signal conditioning, electrical compatibility, and real-time timing.

Learning Objectives

After studying this chapter, students should be able to:

• configure and safely use GPIO pins;
• interface switches and matrix keyboards using polling or interrupts;
• apply hardware and software debouncing;
• drive LEDs and multiplexed displays within current and timing limits;
• condition and acquire analog sensor signals;
• calculate ADC resolution, sampling rate, and conversion error;
• generate analog or quasi-analog outputs using DACs and PWM;
• configure timers and counters from clock and prescaler requirements;
• drive relays, solenoids, DC motors, and stepper motors safely;
• integrate peripherals into a reliable real-time embedded application.

1. The Peripheral Interface as a System

An embedded interface normally contains four layers:

1. Physical device: switch, sensor, display, motor, or other transducer.
2. Electrical interface: pull resistors, amplifiers, filters, level shifters, protection, or power drivers.
3. microcontroller peripheral: GPIO, ADC, DAC, timer, interrupt controller, or serial interface.
4. software layer: device driver, timing logic, filtering, control, and diagnostics.

Figure: Layers of an embedded peripheral interface.

A correct program cannot compensate for an overvoltage applied to a pin, an under-rated motor transistor, or an analog signal outside the ADC range. Hardware and software must therefore be designed together.

2. General-Purpose Digital I/O

2.1 GPIO operating modes

A GPIO pin may support several configurations:

• digital input;
• push-pull output;
• open-drain or open-collector output;
• analog input;
• alternate peripheral function;
• high-impedance state;
• internal pull-up or pull-down resistor.

A push-pull output actively drives both HIGH and LOW. An open-drain output actively drives LOW but requires a pull-up resistor to obtain HIGH. Open-drain connections permit wired logic and level translation when all connected devices tolerate the pull-up voltage.

Inputs must not be left floating. A floating CMOS input may assume unpredictable logic levels, increase power consumption, and respond to electromagnetic interference. A pull-up or pull-down establishes a default state.

2.2 Logic-level compatibility

The receiving device must satisfy:

Here, V_OH(min) and V_OL(max) are the guaranteed output HIGH and LOW limits of the driver; V_IH(min) and V_IL(max) are the receiver's input thresholds. The corresponding noise margins are:

Positive margins are required. A 5 V output must not be connected directly to a non-5-V-tolerant 3.3 V input. Appropriate solutions include a resistor divider for suitable unidirectional signals, a buffer, a transistor, or a dedicated bidirectional level shifter.

2.3 Current and loading

Pin-current specifications include per-pin limits, per-port limits, and total-device limits. These are not interchangeable. The maximum absolute rating is a damage boundary, not a recommended operating current.

For an LED connected to a GPIO output, the approximate series resistance is:

where V_GPIO is the loaded output voltage in volts, V_F is LED forward voltage in volts, and I_LED is desired current in amperes.

Worked example: LED resistor

A 3.3 V GPIO drives a red LED having an approximate forward voltage of 2.0 V. For 6 mA:

A standard 220 Ω resistor gives approximately:

This calculation is preliminary: the final design must use the GPIO's loaded output-voltage specification and account for LED variation.

2.4 Safe initialization

Outputs can briefly assume unintended states during reset. Safety-critical loads should therefore have external pull resistors that establish a safe state until firmware configures the pin. A useful initialization sequence is:

1. enable the peripheral clock;
2. preload the intended output value;
3. configure output type and drive strength;
4. select GPIO or alternate function;
5. enable the external load only after initialization.

Atomic set/clear registers should be used when available. A read-modify-write operation on a shared GPIO register can otherwise overwrite changes made by an interrupt routine.

3. Switches, Keyboards, and Debouncing

3.1 Mechanical switch bounce

Mechanical contacts rarely produce one clean transition. During operation, the contacts may open and close repeatedly for several milliseconds. If every transition is interpreted as a key event, one press can produce several commands.

Hardware debouncing may use an RC network followed by a Schmitt-trigger input. Software debouncing may use:

• a fixed waiting interval followed by confirmation;
• consecutive equal samples;
• an up/down integrator;
• a finite-state machine distinguishing pressed, held, and released states.

A delay alone should not block time-critical processing. Periodic sampling driven by a timer is generally more scalable.

Debounce timing example

Suppose software samples a key every 1 ms and accepts a press after five consecutive active samples. The first and fifth samples are separated by four sampling intervals, so they span 4 ms—not 5 ms. For a clean transition, acceptance occurs approximately 4–5 ms after the physical transition: nearly 4 ms if the transition occurs immediately before a sample, and nearly 5 ms if it occurs immediately after one. Scheduler jitter can change these bounds, while renewed bouncing resets the sequence and increases latency. Debounce latency is therefore implementation-, phase-, and signal-dependent.

3.2 Matrix keyboards

An R × C matrix connects up to R C keys using R + C GPIO pins. Firmware drives one row at a time and reads the columns. Pull resistors establish inactive column levels.

The following schematic uses crossover bridges where row and column conductors cross; these crossings are not electrical junctions. Each normally open momentary switch connects its row to its column only when pressed.

Figure: Three row conductors and three column conductors connected only through nine normally open switches.

A scan cycle typically performs these operations:

1. configure one row active and the remaining rows inactive or high-impedance;
2. allow signals to settle;
3. read all columns;
4. repeat for every row;
5. apply debouncing and key-event detection.

Multiple simultaneous keys can create ghost keys if current finds unintended paths through closed switches. Options include accepting only one key at a time, using anti-ghosting software with limited capability, or placing a diode in series with each key for reliable multi-key rollover.

4. Display Interfacing

4.1 LEDs and seven-segment displays

A seven-segment display contains segments a–g and often a decimal point. Common-anode and common-cathode modules require opposite drive polarities. Each segment requires current limiting.

In a multiplexed display, segment lines are shared while one digit-enable line is activated at a time. Digit drivers may be required because a GPIO often cannot safely supply or sink the total instantaneous current.

For N equally timed digits, the ideal duty ratio per digit is:

If the complete display frame frequency is f_frame, each digit is selected once per frame and is therefore refreshed at f_frame. The digit-slot frequency is Nf_frame, and the slot duration is:

Worked example: four-digit multiplexing

For four digits and a complete-frame rate of 1 kHz:

Each digit is selected once every 1 ms, so each digit is refreshed at 1 kHz with 25% duty cycle. The digit is not refreshed at 250 Hz. Firmware should blank the old digit before changing segment data to avoid ghosting.

Peak segment current may exceed average current during multiplexing, but it must remain within the LED pulse rating, driver rating, GPIO aggregate limits, and thermal constraints.

4.2 Character and graphical displays

LCD and OLED modules often provide parallel, SPI, or I²C interfaces. Their drivers must observe setup time, hold time, clock limits, reset sequencing, and command delays. A framebuffer simplifies graphical drawing but consumes memory. Direct rendering uses less memory but may produce visible update artifacts.

5. Sensor Interfacing and Signal Conditioning

Sensors may produce voltage, current, resistance, frequency, pulse width, capacitance, or digital data. Signal conditioning adapts this output to the microcontroller.

Common conditioning functions include:

• amplification and attenuation;
• offset adjustment;
• low-pass filtering and anti-alias filtering;
• impedance buffering;
• bridge excitation and differential measurement;
• linearization and calibration;
• overvoltage, electrostatic-discharge, and reverse-polarity protection;
• galvanic isolation where hazardous potentials are present.

5.1 Resistive sensors

A resistive sensor can form a voltage divider:

where V_S is the supply, R_S is the sensor resistance, and R_F is the fixed resistance, assuming the ADC input does not significantly load the divider.

The divider's Thevenin source resistance is R_F \parallel R_S. It must be low enough to charge the ADC sample-and-hold capacitor within its acquisition time. Otherwise, a longer acquisition interval or buffer amplifier is required.

5.2 Filtering and aliasing

Sampling creates spectral replicas. To prevent high-frequency content from appearing as false low-frequency components, the analog input should be bandwidth-limited before conversion. For a band-limited signal with highest frequency f_max, ideal reconstruction requires:

where f_s is sampling frequency. Practical systems use a higher sampling ratio because real anti-alias filters do not have infinitely sharp cutoffs.

A first-order RC low-pass filter has cutoff frequency:

This relation assumes ideal components and negligible loading. Component tolerance and sensor impedance must be included in a real design.

6. Analog-to-Digital Conversion

An ADC maps a continuous input range to a finite code. For an ideal N-bit unipolar ADC with range 0 to V_REF, the nominal least-significant-bit size is:

For inputs within the allowed range, an ideal straight-binary code can be represented approximately by:

This model assumes an ideal transfer characteristic and excludes offset, gain, and nonlinearity errors. Endpoint conventions can differ between ADC architectures and datasheets.

Worked example: 12-bit conversion

For V_REF=3.3\ V and N=12:

For an ideal input of 1.65 V:

Ideal quantization uncertainty is commonly described as approximately ±0.5 LSB when the converted value is represented by the centre of its quantization interval. Total measurement error also includes reference error, noise, offset, gain error, integral nonlinearity, source error, and temperature drift.

ADC design considerations include:

• input range and reference stability;
• conversion and acquisition time;
• source impedance;
• sample rate and channel sequencing;
• effective number of bits;
• grounding and supply decoupling;
• calibration and sensor uncertainty.

Oversampling can reduce uncorrelated noise and improve effective resolution, but it cannot remove systematic error or recover bandwidth lost through inadequate sampling.

7. Digital-to-Analog Conversion

A DAC produces an analog voltage or current from a digital code. Common architectures include resistor-string, R–2R ladder, current-steering, and sigma-delta converters.

For an ideal unipolar N-bit DAC whose full-scale code is 2^N-1, a common transfer model is:

The exact transfer equation must be taken from the device datasheet because some DACs use a denominator of 2^N. Output buffering may be necessary when the load demands significant current.

Where no DAC is available, filtered PWM can generate an average voltage:

where D is duty ratio, and V_H and V_L are the PWM HIGH and LOW voltages. This approximation applies when the load or filter averages the switching waveform. Ripple depends on PWM frequency, filter characteristics, and load.

8. Timers, Counters, and PWM

8.1 Timer timing relationships

A hardware timer counts clock ticks. If the timer-input frequency is f_clk and the prescaler division factor is P, then:

If an up-counter counts from 0 through ARR inclusively, it uses ARR+1 ticks per update period:

These formulas apply to a simple edge-aligned up-counter. Centre-aligned modes and device-specific clock multipliers require modified calculations.

Worked example: 1 ms timer interrupt

A timer receives 48 MHz. On a microcontroller where the prescaler division equals the prescaler-register value plus one, setting the prescaler register to 47 gives P=48. The tick rate is:

Choosing ARR=999 gives 1000 ticks:

Thus, 47 is the register value and 48 is the division factor. Designers must verify the precise register definition for their device.

8.2 Counters, capture, and compare

A counter records external events such as encoder pulses or product detections. Inputs may require Schmitt triggering, filtering, or synchronization. The event rate must remain within the peripheral's specified bandwidth.

Input capture stores the timer count when an edge arrives. If two captured values differ by \Delta n ticks, then:

Counter wraparound must be handled using modular arithmetic. Output compare generates an event when the count matches a programmed value and is useful for precise waveform timing.

8.3 Pulse-width modulation

For a periodic PWM waveform:

where D is duty ratio, t_on is active time, and T is period. PWM controls LED brightness, heater power, motor voltage, servo commands, and switched-mode converters.

Higher PWM frequency reduces audible noise and output ripple but increases switching loss and may reduce duty-cycle resolution for a fixed timer clock. Complementary power-stage outputs require dead time to prevent both switches in one bridge leg from conducting simultaneously.

9. Actuator and Motor Drivers

GPIO pins cannot normally supply the voltage or current required by relays, solenoids, or motors. A driver stage provides current gain, voltage translation, protection, and sometimes isolation.

9.1 Inductive loads

When current through an inductor changes rapidly, the induced voltage follows:

A flyback diode across a DC relay or solenoid provides a safe current path when the switch turns off. The diode must be oriented so it is reverse-biased during normal energization. Alternatives such as Zener clamps or transient suppressors provide faster current decay at a higher controlled voltage.

9.2 DC motor control

A low-side MOSFET controls one direction of rotation. An H-bridge enables forward drive, reverse drive, braking, and coasting. Driver selection must consider:

• supply and transient voltage;
• continuous, startup, and stall current;
• MOSFET on-resistance and heat dissipation;
• switching frequency and losses;
• flyback-current paths;
• shoot-through prevention;
• current sensing and fault shutdown.

Motor stall current can be many times the normal running current. Designing only for average current can destroy the driver.

9.3 Stepper motors and servos

Stepper motors require sequenced phase currents. Modern drivers regulate winding current by chopping and support microstepping. Commanding step rates beyond available torque causes missed steps.

Many hobby servos use a periodic pulse command whose pulse width represents target position. Timing ranges are device-specific; the frequently quoted values are not universal and must be verified from the servo documentation.

10. Polling, Interrupts, and Data Transfer

Polling repeatedly checks a status condition. It is simple and deterministic when the loop period is bounded, but wastes CPU time and can miss brief events.

Interrupts notify the processor asynchronously. They provide prompt service but require careful control of latency, shared data, interrupt priorities, and execution time. Interrupt service routines should normally capture essential information and defer lengthy processing.

DMA transfers data between a peripheral and memory with limited CPU involvement. It is particularly effective for ADC sample blocks, DAC waveforms, and high-rate serial streams.

A real-time design must distinguish average response from worst-case response. A polling loop services an event in time only if its maximum interval is shorter than the allowable latency and the event remains observable until read.

11. Integrated Application: Greenhouse Ventilation Controller

This is an illustrative case developed to demonstrate complete peripheral integration.

Background and problem

A small greenhouse requires temperature monitoring, keypad configuration, a four-digit display, variable-speed ventilation, and an emergency overtemperature response. The available controller has a 48 MHz clock, 12-bit ADC, GPIO, timers, PWM, and interrupts. The fan uses a 12 V brushed DC motor with 2 A startup current.

Analysis

The temperature sensor produces 10 mV/°C with a 500 mV offset. Its expected 0.5–1.3 V output lies within the 3.3 V ADC range. An RC low-pass filter suppresses fan-switching noise, while the sensor's source resistance and ADC acquisition requirements are checked from the datasheet.

A 1 ms timer tick uses prescaler register 47, division factor 48, and ARR=999. The tick schedules keypad scanning and nonblocking debouncing. Five stable 1 ms samples provide approximately 4–5 ms clean-transition latency, excluding additional bouncing and scheduler jitter.

The display uses four 250 μs slots per 1 ms frame. Consequently, every digit is refreshed at 1 kHz with 25% duty. Transistor digit drivers keep aggregate LED current outside the GPIO pins.

The fan is driven by a rated MOSFET stage rather than directly from GPIO. The MOSFET, supply, wiring, and suppression network are selected for at least startup and possible stall current, with suitable engineering margin. A timer-generated PWM signal controls speed.

Approach and solution

1. Sample temperature through the ADC at 100 samples/s.
2. Average a short block for noise reduction without hiding dangerous temperature changes.
3. Scan one keypad row per scheduler activation and debounce each key independently.
4. Refresh the display entirely through a timer-driven routine.
5. Map measured temperature to fan duty using bounded control logic.
6. Use an independent comparator or watchdog-supported shutdown path if the risk assessment requires protection against firmware failure.
7. Record sensor-range, motor-driver, and watchdog faults for maintenance.

For ADC voltage V, temperature is calculated from the sensor model:

At V=0.850\ V, the calculated temperature is:

Outcome

The design separates fast periodic services from slower application logic, satisfies display-refresh requirements, protects the controller from motor current, and supports fault reporting. Its dependability follows from coordinated electrical, timing, and software design rather than from any single peripheral.

Learning points

• Peripheral calculations must use actual clock, register, and electrical definitions.
• Display frame rate, digit refresh rate, slot rate, and duty ratio are different quantities.
• Filtering improves noise performance but introduces delay.
• Actuator safety requires startup and fault-current analysis.
• Independent protection may be justified where software failure could damage equipment.

12. Challenges, Governance, and Contemporary Practice

Peripheral systems are vulnerable to electromagnetic interference, ground offsets, connector faults, component tolerance, temperature drift, timer rollover, software races, and undocumented startup states. Good engineering practice includes schematic review, worst-case analysis, boundary testing, fault injection, and measurement with oscilloscopes and logic analyzers.

Products must also satisfy applicable electromagnetic-compatibility, electrical-safety, environmental, and machinery regulations. Interfaces connected to humans or hazardous actuators require fail-safe states, access control, diagnostic coverage, and documented risk assessment. Sensor data may create privacy obligations when it reveals occupancy, health, or behaviour.

Modern microcontrollers increasingly provide event-routing fabrics, programmable I/O engines, high-resolution PWM, hardware oversampling, touch sensing, and intelligent analog peripherals. Machine-learning models may classify sensor patterns, but they do not replace input validation, deterministic safety limits, calibration, or conventional fault protection.

Best practices include using typed hardware-abstraction interfaces, documenting pin ownership, keeping interrupt routines short, separating measurement from control policy, validating every peripheral timeout, and deriving timing values from symbolic clock definitions rather than unexplained constants.

Chapter Summary

Peripheral interfacing connects processor software to physical systems. Reliable designs satisfy logic thresholds, current limits, timing requirements, source impedance, noise, protection, and safe-state constraints. GPIO supports digital inputs and several output structures, while switches require defined idle levels and debouncing. Matrix keyboards reduce pin count but may exhibit ghosting.

Multiplexed displays require correct distinction among frame rate, digit refresh rate, slot frequency, and duty cycle. Sensors often need filtering, amplification, calibration, and protection before ADC conversion. ADC and DAC performance depends on resolution, reference quality, loading, sampling, and nonideal errors. Timers provide deterministic scheduling, counting, capture, compare, and PWM functions. Power drivers isolate low-power GPIO circuitry from inductive actuators and motors. Polling, interrupts, and DMA offer different trade-offs in simplicity, latency, and throughput. Robust products integrate these elements through worst-case analysis, fault handling, measurement, and regulatory awareness.

Key Terms

GPIO: A programmable pin used for digital input, digital output, analog input, or a peripheral function.

Push-pull output: An output stage that actively drives both HIGH and LOW levels.

Open-drain output: An output that actively pulls LOW and requires an external or internal pull-up for HIGH.

Noise margin: The voltage allowance between a guaranteed driver level and the receiver threshold.

Debouncing: Suppression of unwanted transitions produced by mechanical-contact bounce.

Keyboard matrix: An arrangement in which keys connect selected row and column conductors.

Ghosting: Detection of an unpressed matrix key because of unintended current paths through other pressed keys.

Multiplexing: Time-sharing conductors or drivers among multiple devices or display digits.

Duty cycle: The active fraction of a periodic waveform.

Signal conditioning: Electrical processing that adapts a sensor signal for acquisition.

Aliasing: False frequency representation caused by inadequate sampling of signal bandwidth.

ADC: A converter that maps an analog input to a digital code.

Quantization: Representation of a continuous amplitude by one of a finite number of levels.

DAC: A converter that produces an analog output corresponding to a digital code.

Prescaler: A circuit that divides a clock before it reaches a timer or counter.

Input capture: Storage of a timer count in response to an input event.

PWM: Control using a periodic waveform whose active-time fraction is adjustable.

H-bridge: A power circuit that applies either polarity to a load such as a DC motor.

Flyback diode: A diode that provides a current path for an inductive load after switching off.

DMA: Hardware that transfers data between memory and peripherals with little CPU intervention.

Review Questions

Short Answer Questions

1. Why should an unused CMOS input not be left floating?
2. Distinguish a push-pull output from an open-drain output.
3. What causes key ghosting in a keyboard matrix?
4. Why is an anti-alias filter placed before an ADC?
5. What function does a flyback diode perform?

Long Answer Questions

1. Explain the electrical and software considerations involved in interfacing a mechanical switch to a GPIO input.
2. Develop a design procedure for a four-digit multiplexed seven-segment display, including timing and current constraints.
3. Discuss ADC resolution, acquisition time, source impedance, reference error, and calibration.
4. Compare polling, interrupts, and DMA for peripheral data transfer.
5. Explain the operation and protection requirements of a PWM-controlled H-bridge motor driver.

Analytical / Application Questions

1. A 72 MHz timer must generate a 2 kHz update using a prescaler division of 72. Calculate the required value of ARR for an inclusive up-counter.
2. Design a software debouncer sampled every 2 ms that requires four consecutive equal samples. Determine the clean-transition latency range due only to sampling phase.
3. A 10-bit ADC uses a 2.5 V reference to measure a sensor spanning 0.4–2.0 V. Calculate nominal LSB size and endpoint codes using the ideal code model, then identify two nonideal errors that could dominate the quantization error.

Multiple Choice Questions with Answers

Question 1

A GPIO driver guarantees V_OH(min)=2.8\ V, while a receiver requires V_IH(min)=2.0\ V. What is the HIGH-level noise margin?

A. 0.8 V

B. 2.4 V

C. 4.8 V

D. −0.8 V

Correct Answer: A. 0.8 V

Question 2

Five consecutive key samples are taken at 1 ms intervals. What time separates the first and fifth samples?

A. 1 ms

B. 4 ms

C. 5 ms

D. 6 ms

Correct Answer: B. 4 ms

Question 3

A four-digit display has a complete-frame rate of 1 kHz and equal digit slots. How often is each digit selected?

A. 250 Hz with 25% duty

B. 1 kHz with 100% duty

C. 4 kHz with 25% duty

D. 1 kHz with 25% duty

Correct Answer: D. 1 kHz with 25% duty

Question 4

What is the nominal LSB size of an ideal 12-bit ADC with a 3.3 V reference?

A. 0.806 mV

B. 1.61 mV

C. 3.30 mV

D. 8.06 mV

Correct Answer: A. 0.806 mV

Question 5

A 48 MHz timer uses a prescaler division factor of 48. What is its timer tick frequency?

A. 48 kHz

B. 1 MHz

C. 2 MHz

D. 48 MHz

Correct Answer: B. 1 MHz

Question 6

On a timer where the prescaler division equals the prescaler-register value plus one, which register value produces division by 48?

A. 46

B. 47

C. 48

D. 49

Correct Answer: B. 47

Question 7

Which interface method is generally most suitable for transferring continuous high-rate ADC sample blocks to memory with minimal CPU involvement?

A. Busy-wait polling

B. Software debouncing

C. DMA

D. Open-drain GPIO

Correct Answer: C. DMA

Question 8

Why is a flyback diode used with a DC relay coil?

A. To amplify the GPIO voltage

B. To provide a path for inductive current when switching off

C. To increase relay contact current

D. To generate PWM

Correct Answer: B. To provide a path for inductive current when switching off

Question 9

Which condition is required for direct digital-level compatibility at logic HIGH?

A. V_OH(min) ≥ V_IH(min)

B. V_OH(min) < V_IL(max)

C. V_OL(max) ≥ V_IH(min)

D. V_IL(max) < V_OL(max)

Correct Answer: A. V_OH(min) ≥ V_IH(min)

Question 10

What is a principal cause of ghost keys in a keyboard matrix without isolation diodes?

A. ADC quantization

B. Insufficient PWM resolution

C. Unintended current paths through simultaneously closed switches

D. Excessive DAC settling time

Correct Answer: C. Unintended current paths through simultaneously closed switches