Serial Communication and Embedded Networking

Introduction

A microprocessor or microcontroller rarely operates in isolation. It exchanges measurements with sensors, commands with actuators, diagnostic information with computers, and application data with other controllers. Serial communication provides the electrical, logical, and procedural rules that make these exchanges reliable and interpretable.

This chapter examines UART, SPI, I²C, CAN, and USB, then places these interfaces in the broader context of Ethernet, Wi-Fi, and Bluetooth networks. The emphasis is practical: selecting an appropriate protocol, designing frames, addressing devices, controlling errors, and integrating embedded systems safely.

Learning Objectives

By the end of this chapter, the learner should be able to:

1. Explain serial communication, framing, synchronization, addressing, and error control.
2. Configure and use UART, SPI, and I²C interfaces.
3. Describe CAN arbitration, identifiers, and error handling.
4. Explain the host-device model and enumeration process of USB.
5. Compare embedded buses with Ethernet, Wi-Fi, and Bluetooth.
6. Select a communication protocol for a practical embedded application.
7. Diagnose common communication faults using systematic measurements.

1. Serial Communication Fundamentals

In parallel communication, several bits are transferred simultaneously on separate conductors. Serial communication transfers bits sequentially, usually requiring fewer wires and simplifying cabling. Modern serial links can achieve high data rates because transmitters, receivers, signalling methods, and error-control mechanisms are carefully engineered.

A communication system normally contains:

• Transmitter: converts data into electrical or radio signals.
• Receiver: reconstructs data from the signal.
• Medium: wires, printed tracks, optical fibre, or radio spectrum.
• Protocol: rules for timing, framing, addressing, ordering, and error handling.
• Buffer: temporary storage that absorbs differences between producer and consumer speeds.

1.1 Synchronous and asynchronous transfer

In asynchronous communication, the receiver does not share a continuous clock with the transmitter. Each character includes start and stop information. UART is the common example.

In synchronous communication, the receiver obtains timing from a clock line or from the encoded signal. SPI uses a separate clock line, while USB and Ethernet recover timing from the signal stream.

1.2 Bit rate, baud rate, and throughput

The bit rate is the number of data bits transferred per second, measured in bit/s. Baud rate is the number of signalling symbols per second. They are equal only when each symbol represents one bit. In multi-level signalling, one symbol can represent several bits.

For an asynchronous UART frame with one start bit, d data bits, p parity bits, and s stop bits, the character time is:

where R is the baud rate in bit/s and T_character is in seconds, assuming one bit per signalling interval. The maximum character rate is therefore:

For 8-N-1 UART, there is one start bit, eight data bits, no parity bit, and one stop bit. At 9,600 bit/s:

Thus the ideal rate is approximately 960 characters/s, before software delays, buffering, and retransmissions.

1.3 Framing and error control

A frame is a structured unit of communication. It may contain a preamble, address, control field, payload, length, sequence number, error-detection code, and end marker. Error control can detect errors, correct them, or request retransmission.

Common mechanisms include:

• Parity: detects many single-bit errors but cannot reliably detect all multiple-bit errors.
• Checksum: adds data values using a defined arithmetic rule; simple but less powerful than a good CRC.
• Cyclic redundancy check (CRC): treats the bit sequence as a polynomial and divides it by a generator polynomial. The remainder is transmitted as the CRC.
• Acknowledgement and timeout: the receiver confirms successful receipt; lack of confirmation triggers recovery.
• Sequence numbers: identify duplicates and missing frames.

Error detection does not itself repair data. A protocol must specify what happens after detection: discard, request retransmission, substitute a safe value, or enter a fault state.

2. UART and RS-232/RS-485 Applications

2.1 UART operation

A Universal Asynchronous Receiver/Transmitter converts bytes to and from asynchronous serial frames. A typical frame consists of:

1. An idle line state, normally logic high in common UART implementations.
2. A low start bit.
3. Five to nine data bits, commonly eight.
4. An optional parity bit.
5. One or more stop bits.

The receiver detects the start-bit transition and samples near the centre of each bit interval. Both ends must use compatible baud rates, data length, parity, and stop-bit settings. A typical notation is 8-N-1.

UART is generally point-to-point and has no built-in device addressing, arbitration, or acknowledgement. These functions can be implemented by an application-layer packet format.

A practical packet might be:

2.2 Baud-rate generation

A UART peripheral derives its baud clock from the microcontroller clock. The exact divisor depends on the UART architecture and oversampling mode. Therefore, the device reference manual must be used rather than assuming a universal divisor.

Baud mismatch causes sampling to move progressively away from the centre of each bit. Short frames tolerate small mismatch, but long frames and inaccurate oscillators reduce the margin. Crystal oscillators generally provide better accuracy than inexpensive internal RC oscillators.

2.3 Electrical standards

UART describes a data format and peripheral function, not one universal voltage standard. Logic-level UART may use 3.3 V or 5 V signals. RS-232 uses bipolar voltages and inverted signalling and requires a level translator. RS-485 uses differential signalling and is designed for multidrop networks and longer cables.

RS-485 commonly operates in half-duplex mode. Only one transmitter should drive the bus at a time. A termination resistor is normally placed at each physical end of a properly designed bus, while biasing resistors establish a known idle state when no driver is active. Values depend on transceiver characteristics and cable impedance; they should not be selected blindly.

2.4 UART implementation practice

A robust driver normally includes:

• interrupt-driven or DMA-based transmit and receive paths;
• circular buffers;
• timeout detection;
• framing, parity, and overrun error reporting;
• packet resynchronisation after corrupted data;
• independent validation of length and CRC;
• safe handling of buffer overflow.

UART is suitable for console access, GPS receivers, modems, bootloaders, and simple device-to-device links. It is less suitable when many devices must share a bus or when deterministic arbitration is required.

3. SPI: Fast Synchronous Peripheral Communication

Serial Peripheral Interface is a synchronous, usually board-level bus. A controller provides a clock and selects one peripheral. The conventional signals are:

• SCLK: serial clock;
• MOSI: controller-out, peripheral-in;
• MISO: peripheral-out, controller-in;
• CS or SS: active-low peripheral-select signal.

SPI is usually full duplex: one bit can be shifted in while another is shifted out. It has no universal packet format, addressing scheme, acknowledgement, or error detection. Each peripheral defines its own command and register protocol.

3.1 Clock polarity and phase

SPI modes are defined by clock polarity (CPOL) and clock phase (CPHA). CPOL specifies the clock’s idle level. CPHA specifies whether data is sampled on the first or second clock edge. The controller and peripheral must use the same mode.

A mismatch can produce data that appears shifted, constant, or intermittently incorrect. The peripheral data sheet must be consulted for maximum clock frequency, setup time, hold time, bit order, and mode.

3.2 Advantages and limitations

SPI offers high speed, low protocol overhead, and simple hardware. It is widely used for displays, flash memory, analogue-to-digital converters, and sensors. Its disadvantages include more wires, one chip-select per peripheral in many designs, short practical board-level distances, and the absence of standardised interoperability at the command level.

If several peripherals share SCLK, MOSI, and MISO, inactive peripherals must place MISO in a high-impedance state. A faulty or incorrectly configured peripheral that drives MISO continuously can corrupt all transfers.

3.3 SPI design example

Suppose a controller reads a 16-bit sensor register. The sensor protocol specifies an 8-bit read command followed by an 8-bit register address; the returned data appears during the next 16 clock cycles. The controller must:

1. Assert the sensor’s chip select.
2. Send the command and address with the correct bit order.
3. Generate sufficient clock cycles to receive the response.
4. Sample MISO according to the specified SPI mode.
5. Deassert chip select only after the required hold time.

The exact transaction is device-specific; SPI itself does not define the command byte or register address.

4. I²C: Addressed Two-Wire Communication

I²C is a synchronous, multidrop bus using two open-drain or open-collector lines:

• SCL: serial clock;
• SDA: serial data.

Pull-up resistors return both lines high. Devices actively pull a line low but normally do not drive it high. This arrangement permits wired-AND arbitration and allows multiple controllers, subject to the bus specification and implementation.

4.1 Bus conditions and transfers

When the bus is idle, SDA and SCL are high. A START condition occurs when SDA falls while SCL is high. A STOP condition occurs when SDA rises while SCL is high. Data should remain stable while SCL is high; changes during the high period are reserved for START and STOP conditions.

Each byte is followed by an acknowledge clock. The receiver pulls SDA low for ACK; leaving it high indicates NACK. A controller may use NACK to indicate that it does not require more data or that a device did not respond.

A typical transaction is:

START → address plus read/write bit → ACK → register address → ACK → repeated START → address plus read bit → ACK → data bytes → NACK → STOP.

4.2 Addressing and arbitration

I²C devices commonly use a 7-bit address, though extended addressing formats also exist. The transmitted address byte traditionally consists of the 7-bit address followed by a read/write bit; the address is not itself an eight-bit address.

Because lines are wired-AND, a controller that sends a high but observes a low has lost arbitration. It must stop driving and retry according to the system design. Clock stretching allows a device to hold SCL low while it is not ready, although not every controller or host supports it equally well.

4.3 Pull-up resistor considerations

The rising edge of SDA and SCL is produced by the pull-up resistor and bus capacitance. A smaller resistor produces faster rising edges but increases low-level current. A larger resistor reduces current but may make the rise time too slow.

For a simplified RC model:

where t_r is the rise time, R_P is the pull-up resistance, C_B is total bus capacitance, and k depends on the rise-time definition and the assumed waveform model. This is an approximation, not a replacement for the applicable I²C timing limits. Pull-up selection must also satisfy the device’s maximum low-level sink current and the desired bus speed.

4.4 Strengths and weaknesses

I²C uses only two shared signal lines and supports many addressed devices, making it excellent for sensors, real-time clocks, EEPROMs, and power-management ICs. It is slower and more electrically sensitive than SPI, and address conflicts, excessive capacitance, missing pull-ups, and clock stretching can complicate debugging.

5. CAN: Robust Distributed Control

Controller Area Network was designed for reliable communication among distributed controllers, especially in vehicles and industrial systems. CAN uses differential signalling, commonly over a twisted pair, and supports multiple controllers without a central master.

5.1 Message identifiers and arbitration

CAN messages are identified by an identifier rather than by a destination address. The identifier also determines arbitration priority: numerically lower identifiers have higher priority in the conventional dominant-recessive scheme.

A controller begins transmitting an identifier while monitoring the bus. A dominant bit overrides a recessive bit. If a controller transmits recessive but reads dominant, it has lost arbitration and immediately stops transmitting. The winning frame continues without corruption or a separate collision-recovery exchange.

This mechanism is non-destructive arbitration. It provides predictable priority, but excessive high-priority traffic can delay low-priority messages.

5.2 CAN frame and error mechanisms

A classical CAN data frame includes a start bit, arbitration field, control field, data field, CRC field, acknowledgement field, and end-of-frame sequence. CAN implementations also use bit stuffing: after a defined run of equal bits, the transmitter inserts a complementary bit, and the receiver removes it.

CAN detects errors through several mechanisms, including bit monitoring, bit stuffing checks, frame-format checks, acknowledgement checks, and CRC. Nodes signal detected errors using an error frame. Fault confinement uses transmit and receive error counters; a severely faulty node can enter a bus-off state to protect the network.

CAN FD extends the payload capacity and can use a faster data phase, subject to transceiver, wiring, timing, and system compatibility.

5.3 CAN design principles

A CAN network requires compatible bit timing, correct termination at the physical ends, suitable cable impedance, a defined grounding and protection strategy, and carefully selected message priorities. The system designer must calculate worst-case latency rather than relying only on average traffic measurements.

CAN is appropriate for automotive controls, robots, distributed industrial I/O, and safety-related monitoring. It is not a general-purpose replacement for Ethernet or USB.

6. USB: Host-Controlled Device Connectivity

Universal Serial Bus is a standardised connection system for a host and attached devices. Unlike CAN, USB normally uses a host-controlled schedule: the host initiates transactions, while devices respond to requests and transfers.

6.1 Enumeration

When a USB device is attached, the host detects it, resets it, reads descriptors, assigns an address, and selects a configuration. Descriptors identify device class, endpoints, capabilities, and configuration requirements. The host then loads an appropriate driver or uses a class driver.

This process is called enumeration. A device that electrically connects but fails enumeration may have incorrect descriptors, signal-integrity problems, power faults, firmware errors, or an incompatible speed configuration.

6.2 Endpoints and transfer types

USB endpoints are logical data channels. Common transfer types are:

• Control: configuration and management;
• Bulk: reliable large-volume transfers with no guaranteed periodic latency;
• Interrupt: bounded polling service for small, time-sensitive transfers;
• Isochronous: periodic delivery with bandwidth and timing guarantees but limited recovery of corrupted data.

USB uses packet-level error detection and acknowledgements, with retries for applicable transfer types. Bus-powered devices must obey current and power-management rules. Connector wiring, pull-up or pull-down signalling, speed requirements, cable quality, and electromagnetic compatibility are important practical concerns.

USB is attractive when interoperability with computers is required. It is more complex than UART, SPI, or I²C because a compliant device requires descriptors, endpoint management, protocol state machines, and often a substantial software stack.

7. Connecting Embedded Devices to Networks

7.1 Ethernet

Ethernet provides wired local-area networking with standard physical layers, frames, MAC addresses, switches, and commonly Internet Protocol above it. An embedded controller may use an integrated Ethernet MAC with an external physical-layer transceiver, or a network controller connected through SPI or another bus.

An Ethernet-to-UART gateway illustrates layering: UART carries local bytes, gateway firmware interprets them, and an Ethernet interface transports application messages using higher-layer protocols such as TCP or UDP. TCP provides ordered, reliable byte-stream delivery, while UDP provides datagrams with lower protocol overhead but no intrinsic delivery guarantee.

Designers must address IP configuration, time synchronisation, authentication, encryption, firmware updates, and network segmentation—not merely electrical connectivity.

7.2 Wi-Fi

Wi-Fi offers wireless LAN connectivity and commonly carries IP traffic. It enables cloud services, mobile applications, and remote monitoring, but introduces variable latency, radio interference, association and authentication procedures, and higher energy consumption than a short wired bus.

A product should not expose an unprotected debug interface merely because it uses Wi-Fi. Credentials, certificates, secure key storage, encrypted transport, update signing, and least-privilege services are central design requirements.

7.3 Bluetooth

Bluetooth is commonly used for short-range personal-area communication. Bluetooth Low Energy uses advertising, scanning, connections, services, and characteristics. It is well suited to battery-powered sensors and mobile-device interaction. Range, throughput, connection interval, pairing method, privacy, and interoperability must be considered together.

Bluetooth is usually preferable to Wi-Fi when data volumes are modest and low energy use or direct smartphone access is important. Wi-Fi is generally preferable when direct IP connectivity and higher throughput are required.

8. Selecting a Protocol

Protocol selection should begin with requirements rather than familiarity. Important questions include:

• How many devices must communicate?
• Is the link point-to-point or multidrop?
• What distance and cable environment are involved?
• What data rate and worst-case latency are required?
• Is deterministic priority or collision recovery necessary?
• Are addressing, acknowledgement, and error detection built in?
• What power budget is available?
• Must the device interoperate with a computer, vehicle network, or Internet service?
• What are the safety, security, maintenance, and certification requirements?

9. Practical Debugging Method

Communication faults should be investigated from the physical layer upward:

1. Confirm power rails, ground reference, pin multiplexing, and voltage compatibility.
2. Check cable orientation, termination, pull-ups, and connector continuity.
3. Verify clock frequency, baud rate, SPI mode, addresses, and polarity.
4. Capture signals with an oscilloscope or logic analyser.
5. Determine whether the fault is at framing, addressing, payload, or error-checking level.
6. Test one device and one transaction before introducing full application traffic.
7. Add timeouts and recovery rather than allowing firmware to wait forever.
8. Record error counters, reset causes, bus states, and rejected frames.

A logic analyser can show that bits exist, but an oscilloscope may be required to reveal slow edges, ringing, overshoot, ground-bounce, or inadequate differential amplitude. Tools must be configured with the correct voltage thresholds and protocol decoder settings.

10. Illustrative Case: Distributed Environmental Monitoring

Background

A diploma-level engineering team is designing a greenhouse controller. Several temperature and humidity sensors are mounted near a microcontroller, a motor controller is located three metres away, and the system must report data to a supervisory computer.

Problem

The team initially proposes SPI for every device. This would require several chip-select lines, longer wiring than SPI is intended to support, and no inherent message priority or fault containment for the motor controller.

Analysis

The local sensors need modest bandwidth and have short board connections. I²C is appropriate if addresses are unique and bus capacitance remains within limits. The motor controller is electrically remote and may generate noise; CAN provides differential signalling, arbitration, acknowledgements, and error handling. The supervisory computer requires a standard connection, so USB or Ethernet is suitable depending on distance and software architecture.

Approach and solution

The design uses:

• I²C for local sensors and a real-time clock;
• CAN for the motor controller and remote I/O;
• Ethernet for the supervisory connection;
• UART as a protected service port for manufacturing and field diagnostics.

Each CAN message receives a documented identifier and priority. Sensor values include a validity flag and timestamp. Firmware uses watchdog recovery, bus-off reporting, CRC-protected application packets where appropriate, and authenticated firmware updates over the Ethernet service.

Outcome

The design reduces wiring, isolates protocol responsibilities, and makes faults easier to diagnose. It also avoids treating a communication link as automatically secure: the Ethernet interface is segmented, authenticated, and restricted to required services.

Learning points

The best protocol is determined by distance, topology, timing, interoperability, electrical environment, power, and lifecycle requirements. A single product may correctly use several protocols at different layers and locations.

11. Limitations, Safety, and Security

No interface guarantees correct system behaviour by itself. A valid frame may contain an incorrect sensor value, a compromised command, or stale data. Application protocols should therefore define units, ranges, timestamps, validity, freshness limits, and safe defaults.

For safety-related systems, communication failure must lead to a defined safe state. Designers should consider loss of power, stuck-at signals, repeated messages, replay, malformed lengths, buffer exhaustion, denial of service, and compromised firmware.

Security controls include authenticated devices, encrypted links where appropriate, secure boot, signed updates, credential protection, access control, logging, network segmentation, and removal or lockdown of production debug ports. Privacy regulations may apply when devices collect personal or location data. Product compliance may also involve electromagnetic compatibility, radio certification, electrical safety, and USB or network interoperability requirements.

12. Contemporary Developments

Current embedded systems increasingly combine traditional buses with IP networking, edge analytics, time synchronisation, and cloud services. Time-sensitive networking extends Ethernet for applications requiring coordinated delivery. Matter and related ecosystems seek interoperability among smart-home devices. Low-power wide-area technologies support remote sensors, although they are distinct from short-range Bluetooth and local Wi-Fi.

Artificial intelligence can assist in anomaly detection—for example, identifying unusual error counters, bus-off events, or sensor traffic patterns. However, an AI model should not replace deterministic protocol validation, safety interlocks, or cryptographic authentication. The model’s data, false-alarm rate, explainability, and failure behaviour must be evaluated before deployment.

Best Practices

• Begin with a written interface specification.
• Use the electrical standard and protocol specification appropriate to the physical environment.
• Define frame formats, byte order, units, timeouts, and versioning.
• Validate lengths before copying received data into buffers.
• Use CRC or another suitable integrity check when the interface does not provide one.
• Design recovery for missing acknowledgements, reset devices, and bus faults.
• Measure real signals rather than relying only on firmware assumptions.
• Document addresses, priorities, termination, pull-ups, and pin assignments.
• Separate safety-critical traffic from noncritical traffic where necessary.
• Secure network-facing interfaces throughout the product lifecycle.

Chapter Summary

Serial communication transfers information sequentially according to electrical and protocol rules. UART is a simple asynchronous point-to-point interface whose frames require compatible baud and format settings. SPI is a fast synchronous peripheral bus, but its command format, chip selection, and error handling are usually device-specific. I²C provides two-wire addressed multidrop communication using open-drain signalling, START and STOP conditions, acknowledgements, and arbitration.

CAN is a robust distributed bus in which identifiers determine arbitration priority and multiple mechanisms detect errors. USB provides standard host-device connectivity, enumeration, descriptors, endpoints, and several transfer types. Ethernet, Wi-Fi, and Bluetooth connect embedded systems to larger networks, but introduce configuration, security, power, and interoperability concerns.

Protocol selection must consider topology, distance, bandwidth, latency, power, environmental noise, interoperability, safety, security, and maintenance. Reliable embedded networking results from coordinated electrical design, firmware, application framing, diagnostics, and lifecycle governance.

Key Terms

UART: Peripheral that converts parallel data to and from asynchronous serial frames.

Baud rate: Number of signalling symbols transmitted per second.

Framing: Organising bits into identifiable communication units.

Parity: A simple error-detection bit associated with a data unit.

CRC: Cyclic redundancy check used to detect transmission errors.

SPI: Synchronous peripheral interface using clock, data, and chip-select signals.

CPOL: SPI parameter defining the clock’s idle polarity.

CPHA: SPI parameter defining the data sampling phase.

I²C: Two-wire addressed synchronous multidrop bus.

ACK: Acknowledge response indicating acceptance of a byte or operation.

Clock stretching: Holding a shared clock low until a device is ready.

CAN: Distributed controller network with priority-based non-destructive arbitration.

Identifier: CAN field used to identify a message and determine priority.

Bit stuffing: Insertion of complementary bits to maintain CAN synchronisation.

USB enumeration: Host process of detecting, identifying, addressing, and configuring a USB device.

Endpoint: Logical USB communication channel.

Ethernet: Wired local-area networking technology using frames and MAC addressing.

Wi-Fi: Wireless LAN technology commonly carrying IP traffic.

Bluetooth Low Energy: Short-range wireless technology designed for low-power communication.

Bus-off: CAN state in which a severely faulted node disconnects itself from bus communication.

Review Questions

Short Answer Questions

1. What is the difference between synchronous and asynchronous serial communication?
2. What information is represented by the UART notation 8-N-1?
3. Why does SPI require a chip-select signal for many peripherals?
4. What is the function of an I²C pull-up resistor?
5. What is USB enumeration?

Long Answer Questions

1. Explain UART framing, baud-rate compatibility, and practical error handling.
2. Compare SPI and I²C in terms of wiring, speed, addressing, and limitations.
3. Describe CAN arbitration and explain why it is called non-destructive.
4. Explain USB endpoints and the four common transfer types.
5. Discuss the factors that should guide selection among CAN, Ethernet, Wi-Fi, and Bluetooth.

Analytical / Application Questions

1. A controller must connect eight low-speed sensors on one circuit board. Explain whether I²C or SPI is more suitable and identify two design risks that must be checked.
2. A remote motor controller shares a noisy three-metre cable with other equipment. Recommend a communication approach and justify the choice using topology, signalling, arbitration, and error handling.
3. A UART system uses 8-N-1 at 19,200 bit/s. Calculate the ideal maximum character rate using the frame-length relationship, and explain why the practical application rate may be lower.

Multiple Choice Questions with Answers

Question 1

Which UART format contains one start bit, eight data bits, no parity bit, and one stop bit?

A. 7-E-2

B. 8-N-1

C. 8-O-2

D. 9-N-1

Correct Answer: B. 8-N-1

Question 2

Which SPI parameter specifies whether the clock is idle high or idle low?

A. CPOL

B. CPHA

C. CRC

D. ACK

Correct Answer: A. CPOL

Question 3

What electrical feature allows I²C devices to pull a shared line low without actively driving it high?

A. Push-pull outputs

B. Differential termination

C. Open-drain outputs with pull-up resistors

D. Bipolar RS-232 drivers

Correct Answer: C. Open-drain outputs with pull-up resistors

Question 4

In conventional CAN arbitration, which message has the higher priority?

A. The message with the numerically lowest identifier

B. The message with the longest payload

C. The message transmitted by the newest node

D. The message with the numerically highest identifier

Correct Answer: A. The message with the numerically lowest identifier

Question 5

What is the primary purpose of USB enumeration?

A. To select an SPI clock mode

B. To assign CAN priorities

C. To detect, identify, address, and configure a device

D. To calculate an I²C pull-up value

Correct Answer: C. To detect, identify, address, and configure a device

Question 6

A UART uses 8-N-1 framing at 9,600 bit/s. Ignoring software overhead, what is its ideal character rate?

A. 96 characters/s

B. 480 characters/s

C. 960 characters/s

D. 9,600 characters/s

Correct Answer: C. 960 characters/s

Question 7

Which interface normally provides built-in message arbitration and fault confinement?

A. SPI

B. CAN

C. Basic UART

D. I²C EEPROM command protocol

Correct Answer: B. CAN

Question 8

Which USB transfer type is intended for periodic delivery where corrupted data is generally not retransmitted?

A. Control

B. Bulk

C. Interrupt

D. Isochronous

Correct Answer: D. Isochronous

Question 9

Which technology is generally most appropriate for direct low-energy interaction between a battery-powered sensor and a smartphone?

A. Bluetooth Low Energy

B. RS-232

C. Classical parallel bus

D. CAN without a transceiver

Correct Answer: A. Bluetooth Low Energy

Question 10

A communication protocol specification should define units, validity, and timestamps because a valid frame may still contain what problem?

A. An electrically impossible clock frequency only

B. An incorrect, stale, or unsafe application value

C. A guaranteed hardware short circuit

D. A compulsory USB descriptor

Correct Answer: B. An incorrect, stale, or unsafe application value