Memory Systems and Address Decoding

Introduction

Memory is the storage subsystem through which a microprocessor or microcontroller obtains instructions, data, configuration values, and temporary working results. The processor communicates with memory using three logical groups of signals: an address bus, a data bus, and control signals. The address bus selects a storage location, the data bus transfers the stored value, and control signals specify operations such as read, write, chip enable, and output enable.

A sound understanding of memory is essential when designing embedded systems. The designer must select suitable memory technologies, calculate capacity and address ranges, decode addresses without overlap, satisfy timing requirements, and balance cost, speed, power consumption, endurance, and reliability.

Learning Objectives

After studying this chapter, the learner should be able to:

• distinguish ROM, RAM, Flash, EEPROM, and cache memory;
• calculate memory capacity and address ranges;
• construct a memory map;
• explain full and partial address decoding;
• design basic address-decoding logic;
• interface memory devices using address, data, and control signals;
• analyse timing, performance, and practical design limitations.

1. Memory Organisation and Terminology

A memory device consists of individually addressable locations. If a device has 2ⁿ locations, it requires n address inputs because an n-bit binary address can represent 2ⁿ distinct values. If each location stores m bits, the total capacity is:

Here, C is capacity in bits, n is the number of address lines, and m is the number of data bits stored at each address. The formula assumes that every address selects one location and that all locations have equal width.

Capacity is often expressed in bytes. Since 8 bits make one byte:

For a byte-wide memory, m = 8, so the capacity is simply 2ⁿ bytes. In digital systems, prefixes such as KiB and MiB traditionally mean 2¹⁰ bytes and 2²⁰ bytes respectively, whereas kB and MB may be used by manufacturers to mean 10³ and 10⁶ bytes.

Important terms include:

• Address: the binary number identifying a memory location.
• Address bus: the group of lines carrying an address.
• Data bus: the group of lines carrying data to or from memory.
• Read operation: transfer of data from memory to the processor.
• Write operation: transfer of data from the processor to memory.
• Chip select (CS): signal that enables a particular memory device.
• Output enable (OE): signal that permits a memory device to drive the data bus.
• Write enable (WE): signal that permits data to be stored.
• Access time: interval from a valid address or control transition until valid output data is available.
• Byte-wide memory: a memory whose locations contain 8 bits.
• Word-wide memory: a memory whose locations contain the processor’s selected word size, such as 16 or 32 bits.

Many control signals are active-low. They are conventionally written with an overbar, for example CS̅, or with a suffix such as CS_N. An active-low signal is asserted when it is at logic 0.

2. Types of Semiconductor Memory

2.1 ROM

Read-only memory is non-volatile: it retains information when power is removed. Traditional mask ROM is programmed during manufacture. PROM can be programmed once by the user, while EPROM can be erased, usually with ultraviolet light, and reprogrammed. These older forms are less common in new designs but explain the historical development of non-volatile memory.

ROM is suitable for fixed firmware, lookup tables, boot code, and safety-critical constants. Its principal advantages are retention and predictable read behaviour. Its limitation is poor flexibility when the stored program must be updated.

2.2 RAM

Random-access memory allows approximately equal-time access to any location. It is normally volatile, so its contents disappear when power is removed.

Static RAM (SRAM) stores each bit in a latch or bistable circuit. It does not require refresh while powered, has low and predictable access latency, and is commonly used for processor cache and small embedded buffers. It requires more silicon area per bit than DRAM.

Dynamic RAM (DRAM) stores each bit as charge associated with a capacitor and must be periodically refreshed. DRAM offers high density and low cost per bit but requires a memory controller and has more complex timing. It is common in computers and larger embedded systems.

RAM may be asynchronous or synchronous. In asynchronous RAM, address and control changes directly determine the operation. Synchronous RAM uses a clock and captures commands or addresses on clock edges, allowing high-speed pipelined operation.

2.3 Flash Memory

Flash is electrically erasable and programmable non-volatile memory. It is erased in sectors or blocks rather than normally one byte at a time. Flash has high density, low cost per bit, and good retention, making it common for firmware, solid-state storage, and data logging.

Flash has finite program/erase endurance. A controller may therefore use wear levelling, error-correcting codes, bad-block management, and power-loss protection. NOR Flash provides fast random reads and is often used for execute-in-place firmware. NAND Flash provides very high density and is normally accessed through a controller that manages pages and blocks.

2.4 EEPROM

Electrically Erasable Programmable ROM can be electrically rewritten without removing the device. EEPROM commonly supports byte-level or small-page writes, which is useful for calibration constants, serial numbers, configuration data, and counters. It generally has lower density and slower write operations than Flash, but its fine-grained update capability is valuable.

2.5 Cache Memory

Cache is a small, fast memory placed between a processor and a slower main memory. It stores copies of recently or frequently used instructions and data. A cache exploits:

• Temporal locality: recently used data is likely to be used again.
• Spatial locality: data near a recently used address is likely to be used soon.

A cache hit occurs when the requested item is present; a cache miss requires access to a lower memory level. A useful average-access-time model is:

Here, T_avg is average access time, T_hit is cache lookup and hit-service time, h is the hit ratio, and P_miss is the additional miss penalty. The expression assumes that T_hit is paid for every access and that P_miss represents the extra time after a miss. If miss penalty is defined to include hit lookup time, the formula must be adjusted; definitions must not be mixed.

For example, if T_hit = 2 ns, h = 0.90, and P_miss = 40 ns:

T_avg = 2 + (1 − 0.90) × 40 = 6 ns

Cache improves performance but does not increase the fundamental capacity of main memory. In systems with writable caches, designers must also consider consistency between cache contents and external memory.

2.6 Comparison of Memory Technologies

3. Address Space and Memory Maps

A memory map assigns non-overlapping address ranges to memory devices and peripherals. A processor with A address lines can generate at most 2^A distinct byte addresses, giving an address-space size of:

This assumes byte addressing. For a word-addressed processor, the number of addressable words is 2^A, and the physical byte capacity depends on the word size.

For a device beginning at address B and containing L bytes, the final address is:

The subtraction of one is required because the first byte is located at B. The range is valid only when the device is aligned and does not exceed the processor’s address space.

Worked Example 1: Constructing a Memory Map

A microcontroller has a 16-bit byte-address bus. It must accommodate:

• 16 KiB ROM,
• 8 KiB RAM,
• 4 KiB peripheral registers.

The total address space is:

2¹6 = 65,536 bytes = 64 KiB

Assign ROM from 0000H. Since 16 KiB = 4000H bytes, its final address is:

0000H + 4000H − 1 = 3FFFH

Assign RAM from 4000H. Since 8 KiB = 2000H bytes, its final address is:

4000H + 2000H − 1 = 5FFFH

Assign peripherals from 6000H. Since 4 KiB = 1000H bytes, the final address is:

6000H + 1000H − 1 = 6FFFH

The remaining range, 7000H–FFFFH, is unused and may be reserved for expansion.

A good memory map prevents overlap, documents reserved regions, and makes future expansion possible. Memory-mapped I/O places peripheral registers in the same address space as memory. The processor then uses ordinary load and store instructions, but software must respect register side effects and access widths.

4. Address Decoding

Address decoding converts the processor’s address into one or more chip-select signals. A device should be enabled only when its assigned address range is present. Decoding may be implemented with logic gates, a decoder IC, a programmable logic device, or internal microcontroller circuitry.

4.1 Full Decoding

Full decoding uses every address bit needed to distinguish a device from all other locations. For a 16-bit address bus, a 4 KiB device needs 12 internal address bits because 2¹2 = 4096. The upper four bits select the 4 KiB region. A device mapped to 6000H–6FFFH is selected when A15–A12 = 0110.

Full decoding prevents address aliasing, also called mirroring. Every physical location has one logical address in the assigned range. It consumes more logic than partial decoding but provides a clear and reliable map.

4.2 Partial Decoding

Partial decoding tests only some upper address bits. It uses fewer gates, but multiple address ranges may activate the same device. For example, if a 2 KiB RAM uses A0–A10 internally and only A15–A12 are decoded, several lower address combinations may select the device depending on the logic arrangement.

Aliasing is acceptable only when deliberate and documented. It can simplify low-cost designs, but it may cause software errors, make debugging difficult, and prevent later memory expansion.

4.3 Decoder Logic

A 3-to-8 decoder accepts three binary inputs and asserts one of eight outputs. If the inputs are A15, A14, and A13, each output represents one 8 KiB segment in a 64 KiB address space. Additional address bits can be used with gates to subdivide the segment.

For an active-high conceptual decoder, a chip-select condition for a region can be written as a Boolean product. For example, selection of addresses whose upper nibble is 0110 is:

This expression is shown only as a logic example; the device name must match the actual assigned region. Active-low signals require appropriate inversion or NAND-based implementation. In practical circuits, the enable inputs and polarity of the decoder IC must be checked against its datasheet.

Figure: The processor supplies addresses and data; decoding logic generates separate chip-select signals for assigned memory ranges.

5. Memory Interfacing

A memory interface must connect compatible address, data, and control signals. A byte-wide memory with n address inputs connects A0 through A(n−1) to the corresponding processor lines. Its eight data pins connect to D7–D0. The remaining processor address lines feed decoding logic.

During a read cycle, the processor places an address on the address bus, asserts the appropriate chip-select and read controls, and waits for the memory to drive valid data. During a write cycle, the processor places the address and data on their buses and asserts write enable for the required interval.

Data-bus contention occurs when two devices drive the bus simultaneously. Proper chip-select logic and tri-state outputs are therefore essential. Unselected devices must place their outputs in a high-impedance state. Pull-up or pull-down resistors may be required for control inputs so that the circuit remains safe during reset and power-up.

Width and Capacity Expansion

Two common forms of expansion are:

1. Word-width expansion: connect two or more devices to the same addresses, with each device supplying a portion of the data word. For a 16-bit processor using 8-bit chips, one chip may supply D7–D0 and another D15–D8. Their chip-select and timing signals must be coordinated.
2. Address-capacity expansion: connect devices in separate address regions and use higher address bits to select one device at a time.

If a processor requires a 16-bit word but memory is byte-wide, the design must also account for byte order, byte-enable signals, and whether unaligned accesses are supported.

6. Timing and Performance

Memory timing is as important as logical connectivity. A memory may have a correct capacity and address map yet fail because it cannot provide data quickly enough.

For an asynchronous read, the principal constraint is approximately:

Here, t_access is memory access time and t_available is the time from the relevant address or control reference until the processor samples data. A more detailed budget may include address propagation, decoder delay, memory delay, and bus delay:

The terms represent propagation delays through the address path, decoder, memory, and bus; t_cycle is the available cycle interval. This is a simplified worst-case timing budget and must be checked against the processor and memory datasheets, including setup and hold requirements.

For synchronous memory, the designer must verify clock frequency, command setup time, data-out latency, write recovery time, and hold time. Temperature, supply voltage, loading, and manufacturing variation can increase delay. Designs should use worst-case specifications rather than typical values.

Performance can be improved through faster memory, wider transfers, burst operation, interleaving, wait-state control, and cache. Wait states extend the bus cycle when the memory is slower than the processor. They preserve correctness at the cost of throughput.

7. Worked Design Example: Interfacing ROM and RAM

Consider an 8-bit processor with a 16-bit byte-address bus. The system requires a 16 KiB ROM at 0000H and an 8 KiB RAM at 4000H.

The ROM needs 14 address inputs because 2¹4 = 16 KiB. Connect processor lines A0–A13 to ROM address inputs. ROM is selected when A15–A14 = 00. The RAM needs 13 address inputs because 2¹3 = 8 KiB. Connect A0–A12 to RAM address inputs. RAM is selected when A15–A13 = 010.

A read operation should assert the selected chip’s CS and OE while WE remains inactive. During a RAM write, CS and WE are asserted, OE is inactive, and the processor holds address and data stable for the specified setup and hold intervals.

The ranges are:

• ROM: 0000H–3FFFH;
• RAM: 4000H–5FFFH;
• unused: 6000H–FFFFH.

The design must verify that the chosen decoder produces no simultaneous ROM and RAM selects, that both devices tolerate the processor’s voltage levels, and that their access times meet the processor’s cycle requirements. If the ROM access time is too large, wait states or a faster ROM are required.

8. Applied Case: Firmware Logger for an Industrial Sensor

Background

This illustrative case concerns a small industrial sensor node with an 8-bit microcontroller. The node measures temperature and vibration, stores configuration values, and records diagnostic events after power interruptions.

Problem

The design requires fast program execution, non-volatile configuration storage, temporary measurement buffering, and a fault log that must survive power removal. Rewriting the entire firmware device for every configuration update would be inefficient, and storing frequent logs in a small EEPROM could exceed its endurance.

Analysis

The firmware is stored in internal Flash because it is non-volatile and supports in-system updates. SRAM stores sampled data and temporary calculations. EEPROM stores infrequently changed calibration constants and device identity. A larger external serial Flash device stores event logs in pages and sectors.

The designer allocates separate memory regions for program code, SRAM, peripheral registers, and bootloader functions. Chip-select logic ensures that an external memory device is active only during its assigned range. The logging software uses wear levelling and a validity marker so that an interrupted write does not appear to be a complete record.

Approach and Outcome

Configuration values are written to EEPROM only when changed. Measurement buffers remain in SRAM and are periodically compressed before being committed to external Flash. The bootloader verifies firmware integrity before execution using an error-detection mechanism. The memory map reserves an expansion range for a future communication module.

The result is a design with fast normal operation, reduced EEPROM wear, recoverable logs, and a documented address map. The case demonstrates that memory selection is a system-level decision rather than a capacity decision alone.

Learning Points

• Match memory endurance to write frequency.
• Separate volatile working data from non-volatile records.
• Reserve address space for expansion.
• Protect updates against power interruption.
• Treat memory timing and integrity as part of system reliability.

9. Design Challenges, Reliability, and Best Practices

Common design problems include overlapping address ranges, floating chip-select inputs, insufficient timing margins, incorrect active-low assumptions, bus contention, incompatible voltage levels, and writing non-volatile memory too frequently.

Best practices include:

1. document every address range in hexadecimal and decimal units;
2. use full decoding unless aliasing is intentional;
3. read the complete device datasheet, not only the capacity label;
4. calculate worst-case timing over voltage and temperature;
5. confirm reset-state behaviour of all control signals;
6. add error detection or correction where data integrity matters;
7. provide firmware mechanisms for safe update and recovery;
8. test boundary addresses such as the first and last locations;
9. verify that no two devices drive a shared bus simultaneously;
10. reserve unused address space for future hardware.

Memory devices also raise governance and security concerns. Firmware stored in external memory may be copied or modified, so secure boot, authenticated updates, access control, and encryption may be appropriate. Sensitive calibration data should not be left unprotected. Debug interfaces must be controlled in deployed products. In safety-related systems, retention, endurance, diagnostic coverage, and failure modes should be documented and tested according to the relevant industry standard.

Contemporary systems increasingly combine internal Flash and SRAM with external DDR memory, cache hierarchies, non-volatile storage controllers, and memory protection units. Artificial intelligence is relevant mainly when a device performs local inference: model weights may reside in Flash, frequently accessed parameters may be cached in SRAM, and intermediate tensors may require carefully sized buffers. The fundamental principles of capacity, address mapping, timing, and integrity remain unchanged.

Chapter Summary

Memory systems provide the storage hierarchy required by processors and embedded controllers. ROM, Flash, and EEPROM retain information without power; SRAM and DRAM provide volatile working storage; and cache reduces average access time by exploiting temporal and spatial locality. Capacity depends on the number of address lines and the width of each location.

A memory map assigns non-overlapping address ranges to memory and peripherals. The final address of a device is its base address plus its length minus one. Address decoding generates chip-select signals, with full decoding preventing aliasing and partial decoding reducing hardware at the cost of mirrored addresses. Correct interfacing requires compatible address and data widths, proper control-signal polarity, tri-state bus behaviour, and adequate timing margins.

Professional memory design also considers endurance, retention, power failure, security, voltage compatibility, expansion, and worst-case operating conditions. A reliable design is therefore both logically correct and physically validated against device specifications.

Key Terms

Address bus: Group of lines carrying a memory address.

Access time: Delay between a valid access request and valid data.

Aliasing: Multiple processor addresses selecting one physical location.

Cache: Small, fast memory that stores copies of frequently used data or instructions.

Chip select: Signal that enables a particular device.

Data bus: Group of lines transferring data.

Decoder: Logic circuit that converts address bits into select signals.

DRAM: Dense volatile memory requiring periodic refresh.

EEPROM: Electrically erasable non-volatile memory suited to small updates.

Flash: Block-erasable, electrically programmable non-volatile memory.

Memory map: Assignment of address ranges to system resources.

Non-volatile memory: Memory retaining contents without power.

OE: Output-enable control signal.

RAM: Volatile read/write memory.

ROM: Non-volatile memory intended primarily for reading.

SRAM: Fast volatile memory that does not require refresh while powered.

Tri-state output: Output capable of logic 0, logic 1, or high impedance.

Wait state: Additional bus cycle or interval inserted to accommodate slow memory.

Write endurance: Maximum specified number of reliable write or erase cycles.

Review Questions

Short Answer Questions

1. Why does a memory with n address lines have 2ⁿ addressable locations?
2. Distinguish SRAM from DRAM.
3. What is the purpose of a chip-select signal?
4. Define address aliasing.
5. Why are Flash erase operations normally performed by sector or block?

Long Answer Questions

1. Compare ROM, SRAM, DRAM, Flash, EEPROM, and cache in terms of volatility, speed, density, endurance, and application.
2. Explain how a processor performs a typical asynchronous memory-read cycle.
3. Describe full and partial address decoding and discuss the advantages and disadvantages of each.
4. Explain the electrical and timing requirements for interfacing a byte-wide RAM to a processor.
5. Discuss how cache locality improves performance and identify situations in which cache contents may create consistency problems.

Analytical / Application Questions

1. A processor has a 20-bit byte-address bus. Design a memory map containing 64 KiB ROM, 32 KiB RAM, and 8 KiB memory-mapped I/O, beginning with ROM at 00000H. Give the start and end address of each region.
2. A cache has a hit time of 3 ns, a hit ratio of 95%, and a miss penalty of fifty ns beyond the hit lookup. Calculate the average access time and state the assumptions used.
3. A 16-bit processor uses two 8-bit RAM chips to form a 16-bit-wide memory. Explain how the data lines, address lines, chip selects, and byte-enable signals should be connected, and identify one possible bus-contention fault.

Multiple Choice Questions with Answers

Question 1

A memory with 14 address lines and 8-bit locations has what capacity?

A. 4 KiB

B. 8 KiB

C. 16 KiB

D. 32 KiB

Correct Answer: C. 16 KiB

Question 2

What is the main purpose of address-decoding logic?

A. To amplify data-bus voltage

B. To generate device-select signals from addresses

C. To refresh DRAM cells

D. To convert serial data into parallel data

Correct Answer: B. To generate device-select signals from addresses

Question 3

Which memory normally requires periodic refresh?

A. SRAM

B. EEPROM

C. DRAM

D. ROM

Correct Answer: C. DRAM

Question 4

A 4 KiB device begins at 8000H. What is its final address?

A. 8FFFH

B. 80FFH

C. 9FFFH

D. BFFFH

Correct Answer: A. 8FFFH

Question 5

Which technology is most suitable for storing infrequently changed calibration constants?

A. EEPROM

B. Cache SRAM

C. DRAM

D. CPU register

Correct Answer: A. EEPROM

Question 6

What is a disadvantage of partial address decoding?

A. It always requires more gates

B. It prevents all memory access

C. It can produce mirrored address ranges

D. It makes memory non-volatile

Correct Answer: C. It can produce mirrored address ranges

Question 7

If a cache hit time is 2 ns, the hit ratio is 0.90, and the additional miss penalty is 40 ns, what is the average access time?

A. 4 ns

B. 6 ns

C. 40 ns

D. 42 ns

Correct Answer: B. 6 ns

Question 8

During a RAM write cycle, which control signal normally permits storage of the data?

A. WE

B. OE only

C. Refresh enable only

D. Clock disable

Correct Answer: A. WE

Question 9

Why must unselected memory devices place their outputs in a high-impedance state?

A. To increase their storage capacity

B. To avoid simultaneous devices driving the data bus

C. To erase their contents

D. To perform address translation

Correct Answer: B. To avoid simultaneous devices driving the data bus

Question 10

A 16-bit byte-addressed processor has what total address-space size?

A. 16 KiB

B. 32 KiB

C. 64 KiB

D. 128 KiB

Correct Answer: C. 64 KiB