Instruction-Level Parallelism and Advanced Execution

Introduction

Instruction-level parallelism (ILP) is the overlap or simultaneous execution of operations from a single instruction stream. Whereas pipelining overlaps different stages of successive instructions, advanced processors seek additional parallelism by issuing multiple instructions per cycle, executing instructions outside program order, predicting control flow, and speculating before outcomes are known.

These techniques must preserve the instruction set architecture’s observable behavior. In particular, out-of-order processors commonly retire instructions in program order to support precise exceptions: when an exception is reported, all older instructions have completed architecturally and no younger instruction has modified architectural state. This property is distinct from sequential consistency, which is a multiprocessor memory-consistency model requiring the operations of all processors to appear in one total order consistent with each processor’s program order. A processor may provide precise exceptions without implementing sequential consistency.

ILP improves performance but requires larger scheduling windows, more physical registers, more prediction hardware, additional data paths, and greater energy consumption. Its practical limit is therefore determined not only by available parallelism but also by timing, power, verification, memory latency, and prediction accuracy.

Learning Objectives

After studying this chapter, the reader should be able to:

• distinguish pipelined, superpipelined, superscalar, out-of-order, speculative, and VLIW execution;
• identify true, name, control, and memory dependencies;
• explain register renaming, reservation stations, load–store queues, and reorder buffers;
• trace the dispatch, issue, execution, completion, and retirement of instructions;
• evaluate branch predictors, including two-bit saturating-counter predictors;
• calculate IPC, CPI, branch-misprediction cost, and bounded speedup;
• compare dynamically scheduled superscalar processors with statically scheduled VLIW machines;
• assess the performance, energy, security, and complexity limits of ILP.

1. Performance Foundations

Processor execution time is commonly expressed as

where T_CPU is execution time in seconds, IC is the dynamic instruction count, CPI is average cycles per retired instruction, and T_clk is clock period in seconds. Equivalently, T_clk = 1/f_clk, where f_clk is clock frequency in hertz.

Instructions per cycle is

where N_retired is the number of architecturally retired instructions and N_cycles is elapsed processor cycles. For a measured interval in which instructions retire steadily, CPI = 1/IPC. This reciprocal relationship should not be applied to an interval containing no retired instructions.

For an ideal processor able to retire at most W instructions per cycle,

The bound assumes an adequately long instruction stream and ignores startup, dependencies, cache misses, branch recovery, and other bottlenecks. Real IPC is usually substantially lower than issue width.

1.1 Latency and throughput

Latency is the time from the start of an operation until its result becomes available. Throughput is the rate at which operations complete or can be accepted. A fully pipelined multiplier might have a latency of four cycles but accept one independent multiplication every cycle.

For a simple pipeline with k stages executing n independent instructions, with one instruction entering per cycle and no stalls, the cycle count is

This is a special-case pipeline model; it does not describe superscalar issue, variable-latency operations, or pipeline hazards.

2. Forms of Advanced Execution

2.1 Conventional and superpipelined execution

A conventional scalar pipeline initiates at most one instruction per cycle. Superpipelining divides work into a greater number of shorter stages, potentially allowing a shorter clock period. Deeper pipelines incur additional register overhead and increase the number of in-flight instructions. Branch recovery and exception handling may also become more costly in cycles.

Clock frequency does not increase in direct proportion to pipeline depth because latch delay, clock skew, unequal stage delays, wire delay, and power constraints remain. Consequently, greater depth eventually produces diminishing or negative returns.

2.2 Superscalar execution

A superscalar processor can fetch, issue, execute, or retire multiple instructions in one cycle. A processor described as four-wide may have a maximum width of four at one or more of these stages, but widths need not be equal. For example, it may decode four instructions yet possess only two integer arithmetic units and one load unit.

Multiple issue requires the processor to:

1. find independent instructions;
2. provide sufficient execution units and register-file ports;
3. route operands and results;
4. detect hazards;
5. recover from incorrect speculation;
6. commit results in a controlled architectural order.

2.3 Out-of-order execution

In an out-of-order processor, instructions are decoded in program order but may begin execution when their operands and required functional units become available, even if older instructions are still waiting. This allows younger independent operations to bypass a stalled instruction.

Execution order and architectural retirement order are separate. Results may complete out of order while instructions retire in order through a reorder buffer. This combination exposes parallelism while maintaining precise architectural state.

2.4 Speculative execution

A processor executes speculatively when it performs work before confirming that the work is required or safe to make architecturally visible. Common forms include:

• executing beyond a predicted branch;
• issuing a load before all older store addresses are known;
• predicting whether two memory operations conflict;
• predicting operation values or dependencies in experimental designs.

Speculative results remain provisional. If the prediction is wrong, affected instructions are squashed and correct execution restarts. Although squashed instructions do not update architectural state, their microarchitectural effects—such as cache fills—can persist, creating security concerns.

2.5 VLIW execution

A very-long-instruction-word (VLIW) architecture encodes several operations in one instruction bundle. The compiler statically determines which operations can execute together and assigns them to functional-unit slots.

VLIW works well when dependence and latency are predictable, as in some digital signal processing workloads. Challenges include code expansion from unused slots, variable memory latency, exception handling, and maintaining compatibility across implementations.

3. Dependency Analysis

Correct scheduling begins with distinguishing dependencies that carry information from those arising only because architectural storage names are reused.

Consider:

I1: R1 ← R2 + R3
I2: R4 ← R1 × R5
I3: R1 ← R6 − R7
I4: R8 ← R1 + R9

3.1 Register dependencies

• Read after write (RAW): I2 must read the value produced by I1. This is a true data dependency and cannot be removed by renaming.
• Write after read (WAR): I3 must not overwrite architectural R1 before I2 has read I1’s value. This is an anti-dependency caused by name reuse.
• Write after write (WAW): I1 and I3 both write R1, so architectural ordering must identify I3 as the final writer. This is an output dependency caused by name reuse.
• Read after read (RAR): two reads of the same location do not create a hazard because neither changes the value.

Register renaming eliminates WAR and WAW hazards by assigning different physical destinations. It does not eliminate RAW dependencies because consumers still require the producer’s value.

3.2 Control dependencies

An instruction is control-dependent on a branch if its execution depends on the branch outcome. Branch prediction converts the delay of waiting for the outcome into speculative work and a recovery cost when the prediction is incorrect.

3.3 Memory dependencies

Memory dependencies are more difficult because addresses may be calculated at run time. A load must obtain the value of the youngest older store to the same address. If no older matching store exists, it may read the cache hierarchy.

A load–store queue (LSQ) tracks in-flight memory operations. It supports:

• ordering checks between loads and stores;
• store-to-load forwarding when addresses match;
• delaying a load whose safety is uncertain;
• detecting ordering violations after speculative loads;
• enforcing the memory-ordering requirements of the architecture.

Memory disambiguation predictors may allow a load to pass older stores with unresolved addresses. If a later address calculation reveals an alias, the processor replays or squashes dependent work.

4. Register Renaming

Register renaming maps each architectural register name to a physical register holding its current speculative or committed version. A rename map table records the active mapping.

For the previous instruction sequence, one possible mapping is:

Initial: R1 → P1
I1: R1 → P10; computes P10 ← P(R2) + P(R3)
I2: reads P10; writes P11 for R4
I3: R1 → P12; computes P12 ← P(R6) − P(R7)
I4: reads P12; writes P13 for R8

I2 remains dependent on I1 through P10, but I3 can execute without waiting for I2 to read P10. The reuse of architectural R1 no longer creates WAR or WAW hazards.

A physical register cannot be reclaimed merely when a new mapping is created. It must remain available until the processor knows that no older recovery point or instruction can require it. Implementations commonly free an old physical register when the replacing instruction retires, although precise mechanisms differ.

Figure: Renaming gives successive writes to R1 distinct physical destinations while preserving each RAW relationship.

5. Dynamic Scheduling Structures

5.1 Reservation stations and issue queues

A reservation station or issue-queue entry holds an operation until its source operands and a suitable execution unit are available. An entry typically contains:

• operation type;
• source values or producer tags;
• source-ready bits;
• destination physical-register tag;
• age or ordering information;
• control information.

When a producer completes, its destination tag and result are communicated to waiting consumers. Matching consumers mark the corresponding operand ready. The selection logic then chooses ready instructions for available functional units.

This process is often described as wakeup and select. Its delay and energy can grow rapidly with issue-window size, issue width, and the number of result broadcasts. Practical processors therefore use segmented queues, clustered execution, restricted bypass networks, or multiple scheduling domains.

5.2 Reorder buffer

A reorder buffer (ROB) records in-flight instructions in program order. A typical ROB entry stores completion status, exception information, branch information, and data needed for retirement or recovery. Depending on the design, completed values reside in the ROB, the physical register file, or both.

At retirement, the processor examines the oldest entries. An instruction can retire when it has completed without an unresolved exception and all required architectural conditions are satisfied. Retirement updates committed state and releases resources.

If the oldest instruction has an exception, younger instructions are discarded before the exception is reported. The resulting state is precise:

• every older instruction has taken effect;
• the faulting instruction and younger instructions have not taken architectural effect;
• execution can be restarted or transferred to an exception handler consistently.

Again, precise exception state concerns the boundary between retired and unretired instructions. It does not by itself define the ordering of memory operations observed by other processors.

5.3 A representative execution flow

Figure: A representative out-of-order organization. Implementations differ, but renaming, dynamic issue, execution, completion, and in-order retirement are distinct functions.

5.4 Worked scheduling example

Assume one pipelined integer ALU, one non-pipelined three-cycle multiplier, operands initially ready except where dependencies are shown, and one instruction can begin on each unit per cycle.

I1: P10 ← P2 + P3
I2: P11 ← P10 × P5
I3: P12 ← P6 + P7
I4: P13 ← P12 + P8

Suppose an ALU result becomes available at the end of its issue cycle and may be consumed in the next cycle.

I2 completes at the end of cycle 4 because its three multiplier cycles are 2, 3, and 4. Dynamic scheduling overlaps the independent chain I3–I4 with I2. In-order retirement may still require I3 and I4 to wait behind I2, depending on completion and ROB order.

6. Branch Prediction and Recovery

Branches disrupt instruction supply because the next program counter may be unknown. A branch predictor estimates direction and often the target address.

6.1 Prediction mechanisms

• Static prediction: uses a fixed rule, such as always not taken or compiler-provided hints.
• Bimodal predictor: indexes a table of counters using branch-address bits.
• Local-history predictor: uses the recent behavior of the same branch.
• Global-history predictor: uses outcomes of recent branches to capture correlation.
• Tournament predictor: selects among multiple component predictors.
• TAGE-style predictor: combines tagged tables indexed by different history lengths.
• Neural or perceptron predictor: forms a weighted function of branch history, especially useful for long correlations.
• Branch target buffer (BTB): predicts target addresses for control-transfer instructions.
• Return-address stack: predicts procedure-return targets.

6.2 Two-bit saturating counter

A common direction predictor uses four states:

• strongly not taken (SNT);
• weakly not taken (WNT);
• weakly taken (WT);
• strongly taken (ST).

Taken outcomes increment the counter toward ST; not-taken outcomes decrement it toward SNT. The two lower states predict not taken, and the two upper states predict taken.

A two-bit counter provides hysteresis in its strong states: one contrary outcome moves a strong state to a weak state without reversing the prediction. However, the statement that prediction always changes only after repeated contrary evidence is incorrect. From WNT, one taken outcome moves to WT and changes the prediction; from WT, one not-taken outcome moves to WNT and also changes it.

Figure: State transitions of a two-bit saturating counter. A transition across the WNT–WT boundary immediately changes the prediction.

6.3 Branch cost

Under a simplified model with a fixed recovery penalty, the additional CPI caused by branch mispredictions is

where f_b is the fraction of retired instructions that are branches, p_m is the misprediction probability per branch, and P is the average recovery penalty in cycles per misprediction. All three quantities must be measured under compatible workload and processor conditions. The model is approximate because penalties can overlap with other stalls and vary by branch.

Worked example. Suppose branches constitute 20% of instructions, 6% of branches are mispredicted, and each misprediction costs 12 cycles:

If CPI excluding branch mispredictions is 0.80 and no overlap is assumed, total CPI is 0.80 + 0.144 = 0.944, corresponding to approximately IPC = 1/0.944 ≈ 1.059.

6.4 Recovery

A branch checkpoint may preserve the rename map and other recovery information. On a misprediction, the processor:

1. redirects fetch to the correct target;
2. squashes younger instructions;
3. restores the appropriate rename state;
4. reclaims speculative resources;
5. resumes execution from the correct path.

A larger instruction window can exploit more ILP but may increase wasted work and recovery traffic following a misprediction.

7. Limits of Instruction-Level Parallelism

7.1 Program limits

True dependencies impose a critical path that no amount of renaming can remove. Further limits include:

• unpredictable branches;
• pointer-dependent memory accesses;
• cache and translation misses;
• unknown memory aliases;
• insufficient independent instructions within the scheduling window;
• inherently serial algorithms.

7.2 Hardware-resource limits

A wide machine requires proportional support throughout the pipeline. Bottlenecks may arise in fetch bandwidth, instruction-cache access, decoding, rename-map ports, physical-register ports, issue logic, execution units, cache ports, result forwarding, ROB capacity, and retirement bandwidth.

A globally connected bypass network becomes especially expensive as width grows. If every producer must forward to every potential consumer, wire count, capacitance, delay, and energy rise rapidly. Exact growth depends on topology; it should not be reduced to one universal formula.

7.3 Amdahl’s law

If a fraction f of original execution time benefits from an enhancement with speedup S, while the remaining fraction is unaffected, overall speedup is

This form assumes that f and 1-f are fractions of the original execution time and that their times combine additively.

If 70% of execution time can be accelerated fourfold,

The result is much less than four because 30% remains unchanged.

7.4 Power, thermal, and verification limits

Additional speculation and larger scheduling structures consume dynamic and leakage power. Instructions later squashed still use fetch, decode, issue, execution, and cache energy. High temperatures may force frequency reduction, so wider execution can fail to improve sustained performance.

Complex recovery interactions are also difficult to verify. Designers must establish correct behavior under simultaneous cache misses, exceptions, interrupts, branch recovery, memory-order violations, and resource exhaustion.

8. Detailed Applied Case: Communications Signal-Processing Core

Illustrative case. A design team is selecting an execution architecture for a programmable baseband processor used in a wireless receiver.

Background

The workload combines regular finite-impulse-response filtering, vector arithmetic, packet-header parsing, table lookups, and error-control decoding. Filtering loops contain predictable arithmetic parallelism, whereas parsing contains branches and data-dependent memory accesses.

Problem

An eight-operation VLIW prototype performs well on regular kernels but leaves many bundle slots empty during control-intensive code. A four-wide out-of-order prototype achieves steadier utilization but consumes more energy and silicon area. The design must meet a real-time deadline under a constrained power budget.

Analysis

Compiler traces show that filtering kernels often expose six or more independent operations, making static scheduling effective. Header parsing frequently encounters unpredictable branches, while decoding suffers irregular load latency. The VLIW design’s average useful slot occupancy is 82% in filtering but only 31% in parsing. The out-of-order design dynamically fills slots from a larger instruction window, but issue logic and the physical register file account for substantial energy.

Branch profiling also shows that a larger predictor reduces parsing mispredictions, but increasing predictor capacity gives little benefit in regular loops. A load–store queue improves performance in decoding by allowing independent loads to pass unrelated older stores.

Approach

The team adopts a heterogeneous organization:

• a statically scheduled vector/VLIW unit for regular signal-processing kernels;
• a moderately wide out-of-order control core for parsing and irregular tasks;
• compiler-directed kernel placement;
• shared coherent memory with explicitly defined synchronization;
• performance counters for mispredictions, replays, cache misses, and slot utilization.

The out-of-order core is limited to four-wide issue rather than a more power-intensive eight-wide design. Its branch predictor and ROB are sized from workload measurements rather than peak-width assumptions.

Outcome

The combined system meets the deadline with lower energy than running all code on the out-of-order prototype. Regular loops exploit compiler-visible parallelism, while irregular code benefits from dynamic scheduling and branch prediction. The result illustrates that peak issue width is not a sufficient design criterion; workload structure, predictability, memory behavior, and energy matter.

Learning Points

1. VLIW and dynamic superscalar execution are complementary rather than universally competing solutions.
2. Useful IPC depends on available independent work and resource utilization, not nominal width alone.
3. Memory and branch behavior must be measured using representative workloads.
4. Hardware–software co-design can outperform a single uniform execution model.

9. Security, Governance, and Professional Practice

Speculative execution has security implications because wrong-path operations can modify caches, predictors, translation structures, and timing behavior even when their architectural results are discarded. Transient-execution attacks may infer protected data through these side channels.

Mitigations include speculation barriers, predictor isolation, privilege-aware predictor controls, bounds-check hardening, cache partitioning, microcode updates, and constant-time software. Each mitigation may reduce performance and must be evaluated against an explicit threat model.

Professional design practice should include:

• precise documentation of architectural and microarchitectural behavior;
• validation using realistic workloads, not only peak-throughput kernels;
• formal and simulation-based checking of retirement and recovery;
• side-channel testing across privilege and process boundaries;
• transparent reporting of performance, power, and security assumptions;
• compliance with applicable safety and cybersecurity requirements in regulated products.

10. Contemporary Directions

Current high-performance processors increasingly combine heterogeneous cores, specialized matrix units, deeper memory-level parallelism, and sophisticated predictors. Machine-learning methods are researched for branch prediction, prefetching, resource management, and design-space exploration, although latency, storage, determinism, and verification constrain deployment.

Rather than increasing width indefinitely, designers often improve efficiency through instruction fusion, selective scheduling, clustered execution, improved prefetching, better cache hierarchies, simultaneous multithreading, and domain-specific accelerators. The contemporary objective is therefore not maximum ILP at any cost, but useful performance per watt, per area, and per unit of design complexity.

Chapter Summary

Instruction-level parallelism allows a processor to overlap or execute multiple operations from one instruction stream. Superpipelining increases pipeline depth, superscalar execution increases issue width, and out-of-order scheduling permits ready instructions to bypass stalled older instructions. Speculation extends execution beyond unresolved control or memory decisions, while VLIW architectures rely more heavily on compile-time scheduling.

RAW dependencies represent required data flow, whereas WAR and WAW dependencies are name dependencies removable through register renaming. Reservation stations or issue queues perform dynamic wakeup and selection; physical registers hold renamed values; load–store queues manage memory ordering; and reorder buffers support in-order retirement and precise exceptions. Precise architectural state is distinct from sequential consistency, a multiprocessor memory model.

Branch prediction is essential for supplying wide pipelines. Two-bit predictors provide hysteresis, although a weak state changes prediction after one contrary outcome. ILP performance is limited by true dependencies, branch behavior, memory latency, finite windows, hardware bandwidth, power, security, and verification complexity. Effective designs balance dynamic execution, compiler scheduling, workload characteristics, and energy constraints.

Key Terms

Architectural state: Programmer-visible registers, memory effects, and control state defined by the instruction set architecture.

Branch prediction: Estimation of branch direction and target before the branch is resolved.

Control dependency: A relationship in which an instruction’s execution depends on a control-flow decision.

Instruction-level parallelism: Parallel or overlapped execution of operations from a single instruction stream.

Issue queue: Hardware structure that holds instructions and selects ready operations for execution.

Load–store queue: Structure that tracks in-flight memory operations and enforces required ordering.

Memory disambiguation: Determination or prediction of whether memory operations access the same location.

Out-of-order execution: Execution of ready instructions in an order different from program order.

Physical register: Internal storage assigned to a particular version of an architectural register.

Precise exception: Exception state in which all older instructions have taken architectural effect and no younger instruction has done so.

Register renaming: Mapping architectural registers to physical registers to remove name dependencies.

Reorder buffer: Program-ordered structure used to track in-flight instructions, retire them, and support recovery.

Reservation station: Buffer that retains an operation and its operand status until it can execute.

Retirement: Final, architecturally visible commitment of a completed instruction.

Sequential consistency: Memory model in which all processors’ operations appear in one total order consistent with each processor’s program order.

Speculative execution: Execution performed before all conditions authorizing it are known.

Superscalar processor: Processor capable of processing multiple instructions in a cycle at one or more pipeline stages.

Superpipelining: Division of instruction processing into more, shorter pipeline stages.

True dependency: RAW relationship in which a consumer requires a producer’s value.

VLIW: Architecture in which one wide instruction explicitly encodes several statically scheduled operations.

Review Questions

Short Answer Questions

1. Distinguish instruction latency from instruction throughput.
2. Why can register renaming remove WAR and WAW hazards but not RAW dependencies?
3. What role does a reorder buffer play in precise exception handling?
4. How does a load–store queue support store-to-load forwarding?
5. Why can a weak two-bit predictor state change its prediction after one contrary outcome?

Long Answer Questions

1. Explain the complete journey of an instruction through a representative out-of-order superscalar processor.
2. Compare superpipelined, superscalar, speculative, and VLIW execution in terms of performance opportunities and implementation costs.
3. Explain branch prediction and recovery, comparing bimodal, history-based, tournament, and TAGE-style predictors.
4. Discuss the hardware, software, power, security, and verification limits of increasing instruction-level parallelism.
5. Clearly distinguish precise exceptions, in-order retirement, memory ordering, and sequential consistency.

Analytical / Application Questions

1. A processor has a base CPI of 0.65. Branches constitute 18% of retired instructions, the misprediction rate is 5%, and the average penalty is 14 cycles. Under the additive fixed-penalty model, calculate total CPI and IPC.
2. Rename the registers in the sequence R2 ← R1 + R3; R4 ← R2 × R5; R2 ← R6 − R7; R8 ← R2 + R9, identify all RAW, WAR, and WAW relationships, and explain which are removed by renaming.
3. For a communications workload containing regular vector kernels and irregular control code, propose an execution architecture and justify the issue width, scheduling method, branch prediction, and memory-disambiguation support.

Multiple Choice Questions with Answers

Question 1

Which dependency cannot be eliminated by register renaming?

A. Read after write

B. Write after read

C. Write after write

D. Register-name reuse without data flow

Correct Answer: A. Read after write

Question 2

What is the principal function of a reorder buffer in a typical out-of-order processor?

A. To encode several operations into a VLIW bundle

B. To track instructions in program order for retirement and recovery

C. To replace all cache-coherence mechanisms

D. To predict the target of procedure returns

Correct Answer: B. To track instructions in program order for retirement and recovery

Question 3

Which statement correctly distinguishes precise exceptions from sequential consistency?

A. They are two names for the same uniprocessor property

B. Precise exceptions define cache coherence, while sequential consistency defines register renaming

C. Precise exceptions concern the architectural boundary at an exception; sequential consistency is a multiprocessor memory-ordering model

D. Sequential consistency is required before a reorder buffer can hold speculative instructions

Correct Answer: C. Precise exceptions concern the architectural boundary at an exception; sequential consistency is a multiprocessor memory-ordering model

Question 4

A processor has a branch frequency of 0.25, a misprediction probability of 0.04 per branch, and a fixed penalty of 10 cycles. Under the additive model, what is the branch contribution to CPI?

A. 0.04

B. 0.10

C. 0.25

D. 1.00

Correct Answer: B. 0.10

Question 5

A two-bit predictor is currently in the weakly taken state. What occurs after one not-taken outcome?

A. It moves to strongly taken and still predicts taken

B. It remains weakly taken and predicts taken

C. It moves to weakly not taken and changes its prediction

D. It moves directly to strongly not taken

Correct Answer: C. It moves to weakly not taken and changes its prediction

Question 6

Which structure primarily checks ordering and address relationships among in-flight loads and stores?

A. Branch target buffer

B. Load–store queue

C. Return-address stack

D. Instruction decoder

Correct Answer: B. Load–store queue

Question 7

A program spends 60% of its original execution time in a component accelerated by a factor of 3. According to Amdahl’s law, what is the overall speedup?

A. 1.25

B. 1.50

C. 1.67

D. 3.00

Correct Answer: C. 1.67

Question 8

Which feature most directly distinguishes VLIW from a dynamically scheduled superscalar processor?

A. VLIW relies primarily on compiler-scheduled operation bundles

B. VLIW cannot contain arithmetic operations

C. VLIW always executes only one operation per cycle

D. VLIW requires all memory accesses to hit in cache

Correct Answer: A. VLIW relies primarily on compiler-scheduled operation bundles

Question 9

Why may an instruction complete execution but remain unable to retire?

A. Retirement ordinarily waits for older instructions to satisfy in-order commit conditions

B. Completion permanently removes the instruction from the reorder buffer

C. Every completed instruction must be executed a second time

D. Register renaming prohibits retirement of destination registers

Correct Answer: A. Retirement ordinarily waits for older instructions to satisfy in-order commit conditions

Question 10

Which statement about speculative execution is correct?

A. Squashed instructions cannot leave any microarchitectural timing effects

B. Speculation guarantees that every fetched instruction retires

C. Speculative results remain provisional until architectural retirement

D. Speculation removes all true data dependencies

Correct Answer: C. Speculative results remain provisional until architectural retirement