Serial Communication and Industrial Protocols

Introduction

Microcontrollers rarely operate as isolated devices. A control system may contain sensors, drives, displays, supervisory computers, safety controllers, and cloud gateways. Serial communication provides the mechanisms through which these devices exchange measurements, commands, status information, and diagnostic data. In contrast with parallel communication, serial interfaces transmit information sequentially over one or more conductors. This reduces wiring, connector size, electromagnetic coupling, and cost, although it introduces requirements for timing, framing, addressing, arbitration, and error management.

This chapter develops the principles and implementation practices of UART, SPI, I²C, CAN, LIN, USB, RS-485, Modbus, and related industrial protocols. The emphasis is not merely on memorizing signal names, but on selecting an appropriate interface, calculating timing and throughput, diagnosing faults, and designing robust systems.

Learning Objectives

By the end of this chapter, the reader should be able to:

1. Explain serial framing, synchronization, addressing, arbitration, and error detection.
2. Configure and troubleshoot UART, SPI, and I²C interfaces.
3. Distinguish physical-layer standards from communication protocols.
4. Analyze CAN, LIN, USB, and RS-485 architectures and applications.
5. Calculate approximate transmission time, throughput, and bus loading.
6. Implement and diagnose Modbus RTU communication over an RS-485 network.
7. Apply grounding, termination, shielding, isolation, and software design practices suitable for industrial environments.

1. Communication Layers and Design Vocabulary

A communication system is most clearly understood by separating its layers:

• Physical layer: voltage levels, connectors, cables, electrical loading, signaling, and transmission speed.
• Data-link layer: framing, medium access, arbitration, error detection, and acknowledgements.
• Network or addressing layer: identification of nodes and routing, where applicable.
• Application layer: meaning of data, commands, registers, object identifiers, and diagnostic conventions.

RS-485, for example, is primarily an electrical physical-layer standard. It does not define registers, message meaning, or a complete master–slave protocol. Modbus RTU is a protocol commonly carried over RS-485. USB, by contrast, specifies electrical, link, transport, and application-related mechanisms through a large family of specifications.

Important terms include:

• Baud rate: number of signaling symbols per second. In simple binary UART signaling, one symbol commonly represents one bit, so baud rate and bit rate have the same numerical value; this is not universally true for multilevel modulation.
• Bit rate: number of transmitted bits per second.
• Frame: a structured unit containing fields such as synchronization, address, data, and error check.
• Simplex: communication in one direction only.
• Half-duplex: communication in either direction, but not simultaneously.
• Full-duplex: simultaneous transmission in both directions.
• Master–slave or client–server: a controlled exchange in which one device initiates transactions and another responds. Modern documentation often prefers controller–peripheral or client–server terminology.
• Node: a device connected to a communication network.
• Latency: time between an event and the corresponding communication or response.
• Jitter: variation in timing from one event or transmission to another.
• Throughput: useful data delivered per unit time, excluding overhead.

For a message containing L useful data bits and H overhead bits, transmitted at bit rate R, the ideal transmission time is:

Here, t_tx is in seconds and R is in bits per second. The expression assumes a continuously transmitted frame and excludes software delays, propagation delay, arbitration delay, retransmissions, and inter-frame gaps. Useful throughput is approximately:

where η is dimensionless efficiency. Real throughput is lower when bus access delays, acknowledgement time, idle intervals, or retries are significant.

2. UART: Asynchronous Point-to-Point Communication

2.1 Principle and frame structure

UART means Universal Asynchronous Receiver/Transmitter. It is usually a peripheral inside a microcontroller rather than a complete electrical standard. A UART converts parallel bytes into a serial stream and reconstructs received bits. Because no clock line is transmitted, both endpoints must be configured with compatible baud rate, data length, parity, and stop-bit settings.

A common UART frame consists of:

1. An idle line state, usually logic 1.
2. One start bit, usually logic 0.
3. Five to nine data bits, commonly eight, often least significant bit first.
4. An optional parity bit.
5. One or more stop bits, usually logic 1.

A notation such as 8-N-1 means eight data bits, no parity, and one stop bit. With one start bit and one stop bit, each eight-bit payload byte occupies ten transmitted bits. Therefore, neglecting higher-level packet overhead:

where N_d is the number of data bits, N_p is 0 or 1 parity bit, N_s is the number of stop bits, and R_b is the baud rate. For 8-N-1 at 9,600 baud, T_byte = 10/9600 ≈ 1.042 ms. The maximum raw payload rate is approximately 960 bytes per second, not 9,600 bytes per second.

Parity provides limited error detection. For even parity, the parity bit is selected so that the total number of 1 bits in the data plus parity is even. A one-bit error is detected, but some multiple-bit errors can pass undetected. Parity is not a substitute for a message-level CRC.

2.2 Electrical implementations

UART logic signals are typically single-ended CMOS or TTL levels, such as 0 V and 3.3 V. A UART logic interface must not be connected directly to an RS-232 cable. RS-232 uses different voltage polarities and levels, generally supports point-to-point communication, and requires a line driver/receiver such as a transceiver IC. USB-to-UART adapters also contain active conversion electronics; a USB connector is not electrically equivalent to UART pins.

2.3 Configuration and troubleshooting

Both devices must agree on baud rate, frame format, and signal reference. Common failures include:

• incorrect baud rate or clock calibration;
• TX connected to TX instead of TX to RX;
• missing common ground;
• incompatible voltage levels;
• incorrect inversion or parity;
• receiver overrun because software does not service the receive buffer;
• noise causing framing or parity errors.

A disciplined test begins with a known-good loopback. An oscilloscope or logic analyzer can verify start-bit duration, bit order, idle polarity, and frame timing. A protocol analyzer is useful only after the electrical waveform is known to be valid.

3. SPI: Synchronous Local Peripheral Communication

SPI is a synchronous interface commonly used between a microcontroller and displays, ADCs, DACs, memory devices, and sensors. A conventional connection uses:

• SCLK: serial clock;
• MOSI: controller-out/peripheral-in data;
• MISO: peripheral-out/controller-in data;
• CS or SS: chip-select line, usually one per peripheral.

SPI is normally full-duplex. Data is shifted out and in on each clock cycle, so an eight-bit transfer takes eight clock periods. Unlike I²C, standard SPI does not define a universal addressing scheme, acknowledgement bit, or maximum packet format. The controller selects a peripheral using CS and must know that device’s command and register format.

3.1 Clock polarity and phase

SPI modes are defined by clock polarity (CPOL) and clock phase (CPHA). CPOL specifies the idle level of SCLK. CPHA specifies whether data is sampled on the first or second clock edge. The four combinations are conventionally called modes 0–3. The controller and peripheral must use the same mode. A mode mismatch often produces data that appears shifted, duplicated, or consistently incorrect.

Chip-select timing is also device-specific. Some peripherals require CS to remain low for an entire command, while others interpret a rising edge as the end of a transaction. If several peripherals share SCLK, MOSI, and MISO, an inactive device must place MISO in a high-impedance state. Otherwise, two outputs may contend electrically.

3.2 Throughput and design limitations

For an SPI clock frequency f_s and one data bit transferred per clock edge, the raw one-direction bit rate is approximately f_s. If eight useful data bits are transferred in an eight-clock transaction, the byte rate is reduced by command, address, dummy, and chip-select overhead. SPI is fast and simple over short PCB traces, but it is not normally intended for long multidrop wiring. Signal integrity, ground bounce, simultaneous switching, and clock skew limit practical speed.

4. I²C: Addressed Two-Wire Bus

I²C, originally developed for integrated circuits, uses two open-drain or open-collector lines:

• SDA: serial data;
• SCL: serial clock.

Both lines require pull-up resistors. Devices actively pull a line low but normally do not drive it high. This enables wired-AND behavior and permits multiple controllers, although many embedded systems use one controller.

A typical transaction begins with a START condition, followed by a seven-bit address and a read/write bit. The receiving device returns an ACK or NACK during the ninth clock cycle. Data bytes are then transferred, each followed by an acknowledgement bit. The transaction ends with a STOP condition. Ten-bit addressing is also defined, but seven-bit addressing is most common in microcontroller work.

A frequent source of confusion is that the address shown in a data sheet may be a seven-bit address, whereas software libraries may expect the address shifted left by one position with the read/write bit in bit 0. The engineer must verify the convention rather than blindly shifting values.

4.1 Timing and electrical constraints

Because pull-up resistors charge the bus capacitance, rising edges are not instantaneous. A smaller resistance produces faster rising edges but increases low-level current. A larger resistance reduces current but may violate rise-time limits. The approximate RC rise behavior is:

where V_CC is the pull-up voltage, R is the effective pull-up resistance, C is total bus capacitance, and t is time after release. This is a first-order approximation assuming a lumped capacitance and linear resistor. The actual I²C specification defines rise-time limits for each speed mode; resistor selection must satisfy those limits and the devices’ sink-current ratings.

I²C supports acknowledgement, clock stretching, and, in many systems, multi-controller arbitration. Clock stretching allows a peripheral to hold SCL low while it is not ready. Not every controller handles stretching equally well, so compatibility must be checked.

4.2 Typical faults

An SDA or SCL line permanently low may indicate a damaged device, a device reset during a transaction, incorrect pin configuration, or a short circuit. Recovery may involve temporarily configuring SCL as a GPIO and generating clock pulses to allow a stuck peripheral to release SDA, followed by a STOP condition. This should be implemented only with an understanding of the hardware and safety implications.

5. CAN: Distributed, Robust Control Networking

Controller Area Network (CAN) was designed for reliable distributed control, especially in vehicles and industrial equipment. CAN uses differential signaling, message identifiers, non-destructive arbitration, acknowledgement, and strong error detection. A node does not send a destination address in the usual sense; the identifier describes the message’s meaning and priority. All nodes receive the frame and decide whether to accept it.

5.1 Arbitration

CAN uses dominant and recessive bus states. A dominant bit overwrites a recessive bit. During arbitration, nodes transmit the identifier while monitoring the bus. If a node transmits recessive but observes dominant, it withdraws. The frame with the numerically highest priority—normally the lowest numerical identifier—continues without corruption or retransmission. This is non-destructive arbitration.

Consequently, identifiers must be assigned carefully. A high-priority periodic safety message can delay lower-priority traffic. Worst-case response analysis should consider the interference of all higher-priority frames, not merely average utilization.

5.2 Error mechanisms

CAN includes bit monitoring, bit stuffing, frame checks, acknowledgement, and a CRC. A transmitting node inserts a complementary bit after five consecutive equal bits in specified regions. Receivers detect violations and signal an error frame. Error-active and error-passive states, together with a bus-off state, help prevent a faulty node from continuously disrupting the network.

Classical CAN carries up to 8 data bytes per frame. CAN FD permits larger payloads and can use a faster data phase, subject to transceiver, controller, cabling, and network constraints. CAN is not inherently a complete application protocol. CANopen, J1939, and DeviceNet are examples of higher-level systems that define object dictionaries, parameter groups, or device behavior.

5.3 Termination and topology

A conventional high-speed CAN bus uses approximately one termination resistor at each physical end of the main trunk, commonly 120 Ω, with no termination at intermediate nodes. The two resistors appear in parallel to a meter and should measure approximately 60 Ω when the network is powered down and isolated from other circuitry. Long stubs and star wiring cause reflections and should be avoided or carefully engineered.

6. LIN: Cost-Optimized Local Networking

Local Interconnect Network (LIN) is a lower-cost, lower-speed network often used for noncritical vehicle functions such as switches, mirrors, seats, and climate controls. It normally uses a single master and multiple slaves over a single wire plus ground. The master initiates a frame by transmitting a break, synchronization field, and identifier. A designated slave supplies the response.

LIN is simpler and less expensive than CAN but has lower bandwidth, less flexible scheduling, and weaker fault tolerance. It is appropriate when deterministic low-cost communication is needed and the application does not justify CAN. LIN should not be selected for safety-critical or high-bandwidth control merely because it reduces component count.

7. USB: Host-Centered Peripheral Communication

Universal Serial Bus is a standardized, high-speed connection for computers and embedded hosts. Unlike CAN and I²C, USB uses a host-centered architecture. The host detects a device, supplies bus management, assigns an address, and reads descriptors to learn the device’s capabilities. Devices are organized through endpoints and interfaces, and transfers are scheduled by the host.

USB transfer types include control, bulk, interrupt, and isochronous transfers. Control transfers support enumeration and configuration. Bulk transfers emphasize reliable delivery and are suitable for storage or data acquisition without strict timing. Interrupt transfers provide bounded service opportunities for small, time-sensitive reports; despite the name, they are scheduled transactions rather than hardware interrupts. Isochronous transfers reserve bandwidth for time-dependent streams but do not provide the same retransmission guarantee as bulk transfers.

USB complexity is often underestimated. A microcontroller design may require a USB device stack, descriptors, endpoint management, power negotiation, and compliance with electrical and protocol requirements. USB is excellent for connecting a product to a host computer, but it is not usually the simplest choice for a small deterministic sensor bus inside a machine.

8. RS-485 and Industrial Physical Design

RS-485 specifies balanced differential signaling suitable for multipoint networks. A receiver responds primarily to the voltage difference between two conductors, so common-mode noise coupled similarly onto both wires is rejected within the transceiver’s allowed range. A two-wire RS-485 network is half-duplex; a four-wire arrangement can support separate transmit and receive pairs.

RS-485 does not define message framing, addressing, or error checking. Modbus RTU is one widely used protocol over it, but proprietary protocols and other standards are also common.

8.1 Wiring practices

Use a daisy-chain or bus topology with short stubs. Place termination at the two physical ends, not at every node. Biasing resistors may define a known idle differential state when all drivers are disabled, but bias values must be selected with regard to termination and transceiver current. A shield, protective earth, and signal reference should be designed as a complete grounding system rather than connected casually at multiple points.

Industrial installations may require galvanic isolation to prevent ground loops and protect low-voltage electronics from high transient voltages. Isolated transceivers, isolated power supplies, surge protection, fuses, and appropriate creepage and clearance can be necessary. The exact design must follow applicable electrical-safety and EMC standards.

9. Modbus RTU and Industrial Transactions

Modbus RTU commonly uses a client–server model over a serial physical layer. A client sends a request containing a server address, function code, data, and a 16-bit CRC. The server responds with the requested data or an exception response. A typical RTU frame is:

The CRC is calculated over the address, function, and data fields, excluding the CRC itself. The transmitted CRC byte order follows Modbus convention and must be implemented exactly; a mathematically correct CRC with reversed byte order is still an invalid frame.

A Modbus RTU frame is separated from the next frame by a silent interval of at least 3.5 character times. At a given baud rate, the character time depends on the configured UART format. For 8-E-1, a character commonly occupies 11 bits: one start bit, eight data bits, one parity bit, and one stop bit. Thus, at 19,200 baud:

and the nominal minimum silent interval is approximately 3.5 × 0.573 ≈ 2.0 ms. Exact implementation must account for the selected format and the applicable Modbus specification.

Worked Example: Modbus timing

Suppose a request and response together contain twenty 11-bit characters at 9,600 baud. The character transmission time is:

The serial transmission portion is approximately:

Adding two mandatory inter-frame gaps of approximately 3.5 character times gives:

The minimum communication time is therefore about 30.9 ms, before processing delay, turnaround time, retries, or other bus traffic. A control loop requiring a guaranteed 10 ms response cannot use this transaction schedule without redesigning the message, baud rate, protocol, or control architecture.

Register maps require particular care. A manual may label a holding register as 40001, while the protocol address field may require zero-based address 0. Engineers must consult the device-specific register convention, data type, word order, scaling, signedness, and exception behavior.

10. Selecting an Interface

The correct interface depends on distance, number of devices, bandwidth, determinism, cost, noise, and software complexity.

The choice should be made from system requirements rather than habit. A display on the same PCB may be ideal for SPI; a remote inverter in a factory may require isolated RS-485 or CAN; a computer-connected data logger may benefit from USB.

11. Implementation and Troubleshooting Method

A reliable implementation proceeds from the physical layer upward:

1. Define requirements: distance, payload, update rate, latency, node count, safety level, and environmental conditions.
2. Confirm electrical compatibility: voltage, differential range, termination, grounding, isolation, connector pinout, and maximum cable length.
3. Configure clocks and peripherals: baud divider, sampling point, SPI mode, I²C timing, CAN bit timing, DMA, and interrupt priorities.
4. Implement a clear frame state machine: detect start, validate length, check address, verify CRC, and handle timeouts.
5. Instrument the system: expose counters for CRC errors, framing errors, overruns, bus-off events, retries, timeouts, and rejected addresses.
6. Test abnormal conditions: unplugged cable, shorted line, incorrect CRC, delayed response, bus contention, power cycling, and noise.
7. Verify under load: measure worst-case latency and bus utilization rather than relying on an idle bench test.

A useful diagnostic order is: power and ground, connector continuity, physical waveform, protocol frame, application interpretation. Swapping software libraries before checking the waveform often wastes time.

For a bus with periodic messages, a first approximation of utilization is:

where f_i is the frequency of message i in frames per second, B_i is the number of transmitted bits including protocol overhead, and R_b is the bus bit rate. The equation assumes no retransmissions or arbitration delays. It is a planning estimate, not a proof of schedulability. Real-time systems must also analyze priority, blocking, worst-case frame length, and error recovery.

12. Applied Case: Remote Pump-Control Panel

Background

Consider an illustrative industrial pump station containing a microcontroller panel, a variable-frequency drive, pressure and temperature sensors, a local display, and a supervisory PLC. The motor environment produces electromagnetic noise, and the sensors are located 35 m from the panel.

Problem

The original prototype used UART-level signals over an unshielded cable. Intermittent framing errors occurred whenever the motor drive accelerated. The display also required rapid updates, while the PLC needed reliable status and command exchange.

Analysis

The UART wiring was single-ended and lacked a controlled return path. Cable length and motor transients increased susceptibility to common-mode and radiated interference. The prototype also had no message CRC and no timeout strategy. The display and remote instrumentation had different communication requirements, so one interface was unlikely to be optimal for all devices.

Approach and solution

The design was divided into three networks:

• SPI connected the local display and a short-distance ADC on the panel PCB.
• An isolated RS-485 transceiver connected the remote sensor module using a shielded twisted pair and a documented grounding strategy.
• Modbus RTU over a separate isolated RS-485 channel connected the PLC and drive, because both devices already supported the protocol.

The panel software used a nonblocking state machine. Each request had a deadline. CRC failures, timeouts, exception responses, and transceiver-direction faults were counted and reported. Termination was installed only at the two ends of each bus, and the cable topology was changed from a star to a trunk with short stubs. Oscilloscope measurements were taken during motor acceleration.

Outcome

The framing errors disappeared during normal acceleration, and the diagnostic counters made occasional cable faults distinguishable from drive-related interference. The display remained responsive because its local SPI traffic did not compete with the industrial bus. The PLC interface became easier to commission because register definitions, scaling, and exception behavior were documented.

Learning points

The case demonstrates that protocol selection cannot compensate for poor physical wiring. It also shows why a system may legitimately use several interfaces: SPI for local speed, RS-485 for robust distance, and Modbus for interoperability. Isolation, termination, monitoring, and explicit timeout behavior are part of communication design, not optional afterthoughts.

13. Limitations, Safety, and Contemporary Practice

Serial protocols are not automatically safe merely because they include a CRC. A CRC detects many random transmission errors but does not prove that a command is authorized, fresh, correctly scaled, or intended for the current machine. Safety-related functions may require redundant channels, watchdogs, safe states, sequence counters, authentication, and certification under relevant functional-safety standards.

Industrial networks are also cybersecurity boundaries. Modbus RTU, UART, and many fieldbus protocols commonly lack encryption and authentication. A physically accessible port can allow commands to be injected or operational data to be read. Protective measures include network segmentation, authenticated gateways, least-privilege access, secure boot, signed firmware, logging, port control, and threat-informed maintenance procedures. Encryption added without considering latency, key management, and fail-safe behavior may create new engineering problems.

Contemporary systems increasingly combine traditional fieldbuses with Ethernet-based protocols, time-sensitive networking, edge gateways, and wireless links. Artificial intelligence may assist predictive maintenance by analyzing error counters, latency, and sensor trends, but an AI model should not replace deterministic interlocks or safety logic. Data quality, explainability, model drift, and cybersecurity remain engineering responsibilities.

Best-Practice Checklist

• Separate physical-layer, data-link, and application-layer decisions.
• Confirm voltage levels and transceiver compatibility before connecting equipment.
• Use differential signaling, correct termination, shielding, and isolation where the environment requires them.
• Document bit order, byte order, register offsets, scaling, signedness, and timing.
• Use CRC or another appropriate message-integrity mechanism in addition to UART parity.
• Design explicit timeouts, retries, safe defaults, and bus-recovery behavior.
• Measure worst-case latency and bus utilization under realistic load.
• Never assume a register label is the same as the on-wire address.
• Test power cycling, disconnected nodes, invalid frames, noise, and simultaneous access.
• Treat exposed serial ports as cybersecurity and safety concerns.

Chapter Summary

Serial communication links microcontrollers to sensors, actuators, computers, and industrial controllers. UART provides simple asynchronous point-to-point transfer but requires compatible framing and usually a separate electrical standard. SPI offers fast synchronous local communication but generally requires explicit chip-select wiring and device-specific protocols. I²C provides addressed two-wire communication, with pull-up resistor and bus-capacitance constraints.

CAN supports distributed control through message identifiers, non-destructive arbitration, differential signaling, and strong error handling. LIN provides a lower-cost scheduled network for simple local functions. USB is a host-managed architecture suited to computer and peripheral connectivity. RS-485 is a robust differential physical layer that must be paired with a higher-level protocol such as Modbus RTU.

Correct engineering requires more than configuring a peripheral. Designers must account for framing overhead, throughput, latency, arbitration, termination, grounding, isolation, CRCs, timeouts, and fault recovery. A reliable industrial network is the result of coordinated electrical, protocol, software, diagnostic, safety, and cybersecurity design.

Key Terms

UART: Asynchronous serial peripheral that converts bytes to serial frames.

Baud rate: Number of signaling symbols transmitted per second.

Frame: Structured sequence of synchronization, control, data, and checking fields.

Parity: Simple error-detection bit associated with a serial character.

SPI: Synchronous local peripheral interface using clock and data signals.

CPOL: SPI clock-polarity setting defining the idle clock level.

CPHA: SPI clock-phase setting defining the sampling edge.

I²C: Addressed two-wire bus using open-drain signaling and pull-up resistors.

ACK: Acknowledgement bit indicating that a byte was accepted.

CAN: Distributed control network with identifier-based arbitration and error handling.

Dominant bit: CAN bus state that overrides a recessive state.

LIN: Low-cost, master-scheduled local serial network.

USB: Host-managed universal serial bus for standardized peripheral connectivity.

RS-485: Differential multipoint physical-layer standard for robust serial links.

Modbus RTU: Client–server serial protocol commonly carried over RS-485.

CRC: Cyclic redundancy check used to detect transmission errors.

Termination: Resistors used to reduce reflections at the ends of a transmission line.

Bus utilization: Fraction of available transmission capacity occupied by traffic.

Galvanic isolation: Electrical separation that prevents direct conductive current between circuits.

Review Questions

Short Answer Questions

1. What information is specified by the UART notation 8-E-1?
2. Why does an I²C bus require pull-up resistors?
3. What is the purpose of CAN arbitration?
4. Why is RS-485 not, by itself, a complete communication protocol?
5. What role does the CRC play in a Modbus RTU frame?

Long Answer Questions

1. Compare UART, SPI, and I²C in terms of wiring, synchronization, addressing, duplex operation, and typical applications.
2. Explain CAN arbitration and describe how identifier assignment affects message latency.
3. Describe the electrical and installation practices required for a reliable RS-485 network.
4. Explain USB enumeration and compare control, bulk, interrupt, and isochronous transfers.
5. Develop a troubleshooting procedure for an industrial serial link that exhibits intermittent communication failures.

Analytical / Application Questions

1. A UART uses 8-N-1 framing at 19,200 baud. Estimate the minimum time required to transmit 40 payload bytes, ignoring inter-message delays. State your assumptions.
2. A Modbus RTU request–response exchange contains 24 characters, each occupying 11 bits, at 9,600 baud. Estimate the serial transmission time and explain why the actual response time will be longer.
3. Select an interface for a 30 m, electrically noisy connection between a microcontroller and a remote actuator. Justify the physical layer, topology, termination, error handling, isolation, and application protocol you would use.

Multiple Choice Questions with Answers

Question 1

In a UART frame using 8-N-1 format, how many transmitted bits are required for one eight-bit payload byte?

A. 8 bits

B. 9 bits

C. 10 bits

D. 11 bits

Correct Answer: C. 10 bits

Question 2

Which SPI setting determines the idle level of the serial clock?

A. CPOL

B. CPHA

C. CS

D. MISO

Correct Answer: A. CPOL

Question 3

Why are I²C SDA and SCL lines normally connected to pull-up resistors?

A. To provide differential signaling

B. Because devices actively pull the lines low but release them high

C. To generate the SPI chip-select signal

D. To terminate a CAN transmission line

Correct Answer: B. Because devices actively pull the lines low but release them high

Question 4

In CAN arbitration, what normally happens to a node that transmits recessive but observes a dominant bus bit?

A. It increases its baud rate

B. It changes its identifier

C. It withdraws from arbitration

D. It resets the entire bus

Correct Answer: C. It withdraws from arbitration

Question 5

Where should termination resistors normally be placed on a conventional high-speed CAN bus?

A. At every node

B. Only at the controller

C. At the two physical ends of the main bus

D. Only on each cable stub

Correct Answer: C. At the two physical ends of the main bus

Question 6

Which statement about RS-485 is correct?

A. It defines a complete register-level application protocol

B. It is primarily a differential physical-layer standard

C. It requires USB enumeration

D. It is always full-duplex

Correct Answer: B. It is primarily a differential physical-layer standard

Question 7

At 19,200 baud, assuming an 11-bit character, what is the approximate transmission time of one character?

A. 0.057 ms

B. 0.573 ms

C. 5.73 ms

D. 57.3 ms

Correct Answer: B. 0.573 ms

Question 8

Which USB transfer type is primarily intended for reliable high-volume data without strict periodic timing?

A. Bulk

B. Isochronous

C. Control only

D. Clock stretching

Correct Answer: A. Bulk

Question 9

What separates Modbus RTU frames?

A. A CAN dominant bit

B. A mandatory silent interval of at least 3.5 character times

C. An SPI chip-select pulse for every bit

D. A USB descriptor

Correct Answer: B. A mandatory silent interval of at least 3.5 character times

Question 10

A communication system sends 800 useful bits and 200 overhead bits in a frame. What is the ideal protocol efficiency?

A. 20%

B. 50%

C. 80%

D. 125%

Correct Answer: C. 80%