2. Processor Architecture and Operation

Introduction and Context

A microprocessor or microcontroller is not merely an arithmetic device. It is an organized digital system that fetches instructions, interprets them, obtains or generates data, performs operations, and communicates results with memory and peripheral devices. Processor architecture describes the programmer-visible and internally implemented organization that enables these activities. Processor operation describes the sequence of events by which an instruction is executed.

Understanding architecture is foundational for studying instruction sets, embedded-system design, real-time control, compiler behavior, operating systems, and performance optimization. At postgraduate level, the objective is not only to identify registers or buses, but also to analyze how architectural choices influence throughput, latency, power consumption, determinism, programmability, and system reliability.

The discussion in this chapter applies broadly to classical microprocessors and modern microcontrollers. Examples are expressed generically because different processor families use different register names, bus widths, instruction formats, and timing conventions. The underlying principles, however, remain consistent.

Learning Objectives

After completing this chapter, the learner should be able to:

1. Explain the roles and interactions of the ALU, registers, control unit, buses, memory, and input/output interfaces.

2. Describe clocking, instruction cycles, machine cycles, and the fetch–decode–execute process.

3. Analyze addressing modes and their effects on instruction flexibility and execution time.

4. Explain pipelining, hazards, interrupts, and interrupt-service mechanisms.

5. Compare von Neumann and Harvard architectures in terms of performance, flexibility, cost, and security.

6. Apply architectural concepts to embedded control and processor-selection decisions.

7. Evaluate common design errors and trade-offs in processor-based systems.

The Processor as a Coordinated System

A processor can be viewed through three complementary perspectives. The instruction-set architecture (ISA) defines the instructions, data types, registers visible to programmers, addressing modes, and rules governing program execution. The microarchitecture describes how the ISA is implemented internally using datapaths, pipelines, buffers, control logic, and execution units. The system architecture includes memory, buses, peripherals, interrupt controllers, timers, and external interfaces.

Two processors may implement the same ISA while using different microarchitectures. One may execute instructions sequentially, whereas another may use multiple pipeline stages, caches, and speculative mechanisms. Conversely, two processors may have similar internal hardware but expose different instruction sets. This distinction is important when assessing compatibility, performance, and software portability.

At the center of most processors is a datapath. The datapath contains registers, multiplexers, shifters, arithmetic circuits, logical circuits, and connections through which data moves. The control unit generates signals that select datapath operations and coordinate communication with memory and peripherals. The processor therefore operates as a controlled sequence of data transfers and transformations.

The Arithmetic and Logic Unit

The arithmetic and logic unit (ALU) performs operations such as addition, subtraction, incrementing, decrementing, comparison, AND, OR, exclusive OR, complement, and shifting. In many processors, the ALU also produces status information. A typical status register contains flags such as:

• Zero flag (Z): indicates that the result is zero.
• Carry flag (C): indicates a carry from addition or a borrow-related condition in subtraction, depending on the architecture.
• Negative or sign flag (N/S): reflects the most significant bit of a signed result.
• Overflow flag (V/O): indicates that a signed arithmetic result cannot be represented in the available word size.
• Parity flag (P): indicates the parity of selected result bits in architectures that implement it.

Flags must be interpreted according to the processor’s specification. A carry is not equivalent to signed overflow. For example, adding two positive signed values may generate overflow without producing an unsigned carry, while an unsigned addition may generate carry even when signed overflow has not occurred.

The ALU commonly receives one operand from a working register and another from a source register, memory interface, or immediate field. Its output may be written into a register, stored in memory, or used only to update flags. In a microcontroller, the ALU may also support bit manipulation, saturation arithmetic, multiply–accumulate operations, or specialized control-oriented functions.

Register Organization

Registers are high-speed storage locations inside the processor. They reduce the need to access slower memory and provide the temporary state required for instruction execution. Registers can be classified as follows:

• General-purpose registers store operands, addresses, and intermediate values.
• Accumulator registers are closely associated with ALU operations in some architectures.
• Program counter (PC) holds the address of the next instruction to be fetched.
• Instruction register (IR) holds the currently decoded instruction or its active portion.
• Stack pointer (SP) identifies the top of the run-time stack.
• Status or flag register records arithmetic and control conditions.
• Index and base registers support address calculation.
• Control registers configure processor modes, interrupt behavior, memory protection, and system functions.

Register width influences the amount of data that can be processed directly and the range of addresses that can be represented. It should not, however, be confused with the width of every internal or external bus. A processor may have 32-bit registers but use narrower peripheral interfaces or wider internal data paths.

The program counter normally advances after instruction fetch, but branches, calls, returns, exceptions, and interrupts modify it. The stack pointer is especially important in embedded systems because subroutine calls and interrupt servicing often save registers and return addresses on the stack. An incorrectly initialized or insufficiently sized stack can cause failures that appear unrelated to the original software error.

The Control Unit

The control unit interprets the instruction and produces timing and control signals. In a simple processor, it may be implemented as hardwired combinational and sequential logic. In another design, instruction execution may be controlled partly by microcode, in which complex instructions are translated into internal micro-operations.

The control unit performs several related functions. It selects the source and destination of data, activates ALU operations, controls register loading, requests memory reads or writes, updates the program counter, and coordinates access to shared buses. It also responds to reset, wait states, faults, and interrupts.

Control signals are synchronized with the processor clock, although some events may be asynchronous at the external boundary. Correct synchronization is essential because a control signal arriving too early or too late can cause incorrect data capture, bus contention, or loss of an interrupt request.

Buses and Data Movement

A bus is a shared electrical or logical pathway used to transfer information. The traditional processor bus structure includes:

• Address bus: carries the location of a memory or peripheral access. It is usually unidirectional from the processor, although special systems may support multiple masters.
• Data bus: carries instructions and data. It is generally bidirectional.
• Control bus: carries signals such as read, write, interrupt request, acknowledgment, reset, bus request, and clock-related control.

The width of the address bus determines the directly addressable space. With an n-bit address, up to 2^n distinct address locations can be represented, subject to memory mapping and architectural restrictions. The data-bus width influences how many bits can be transferred in one bus transaction, but actual performance also depends on wait states, memory technology, alignment, caching, and bus arbitration.

In a memory-mapped I/O system, peripheral registers occupy addresses within the processor’s normal address space. The same load and store mechanisms can therefore access both memory and peripherals. This simplifies programming but consumes address space and requires careful control of side effects. A read from a status register may clear a flag, and a write to a control register may start an actuator or alter an interrupt configuration.

Modern systems often contain several buses rather than one shared bus. A high-speed system bus may connect the processor to memory, while peripheral buses connect timers, serial interfaces, and analog subsystems. Bridges or interconnect fabrics translate protocols and manage arbitration. These arrangements improve scalability but introduce latency and configuration complexity.

Clocking and the Timing Framework

The clock provides a reference for sequencing synchronous operations. A clock period is the interval between successive active clock edges, and clock frequency is its reciprocal. A processor cycle is not necessarily identical to one instruction cycle. Some instructions complete in a single cycle, while others require several cycles because they involve memory accesses, multiplication, division, or control transfer.

A useful timing hierarchy is:

1. Clock period: one basic timing interval.

2. Machine or bus cycle: a group of clock periods used for an operation such as instruction fetch or memory write.

3. Instruction cycle: the complete interval required to fetch and execute one instruction.

4. Program execution time: the accumulated time for all instructions, including stalls, wait states, and interrupt servicing.

Increasing clock frequency does not automatically produce proportional performance improvement. Memory latency, pipeline stalls, branch penalties, bus contention, power limits, and instruction count may dominate. In control applications, deterministic timing may be more valuable than maximum average throughput.

A processor may insert wait states when a memory or peripheral device cannot respond within the nominal bus timing. Clock-domain crossings require special synchronization techniques because signals generated in one clock domain may violate setup or hold requirements in another. Designers must also account for clock jitter, duty-cycle variation, reset timing, and low-power clock gating.

The Instruction Cycle

Instruction execution is often explained as a fetch–decode–execute sequence, although practical processors overlap and subdivide these stages.

Fetch

The program counter supplies the address of the next instruction. The control unit initiates a memory read, and the instruction is transferred into an instruction register or instruction queue. The program counter is advanced by the instruction length unless a later operation changes it.

Decode

The opcode is interpreted. The processor identifies the operation, source and destination operands, addressing mode, required functional unit, and any privilege or protection requirements. For a variable-length instruction set, additional bytes may be fetched during this stage.

Operand Access

Operands may come from registers, memory, the instruction itself, or an implicit architectural location. Address calculation may be required. If the operand is in memory, the processor performs one or more bus transactions and may encounter wait states.

Execute

The ALU or another execution unit performs the requested operation. A branch determines a new program-counter value; a load or store transfers data; and a control instruction changes processor state. Flags and other architectural state may be updated.

Write-Back and Completion

The result is written to its destination, status flags are updated, and any pending exception or interrupt is recognized according to the processor’s rules. Some architectures combine write-back with execution, while others use explicit pipeline stages.

The distinction between instruction cycle and bus cycle is important. A single instruction may require multiple bus cycles, and a pipeline may complete one instruction per cycle only after an initial filling period. Performance analysis must therefore consider both instruction count and timing behavior.

Addressing Modes as an Interface Between Instructions and Data

An addressing mode specifies how an instruction identifies its operand. It affects code size, flexibility, execution time, and compiler strategy. Common modes include:

• Immediate addressing: the operand value is embedded in the instruction, as in loading a constant.
• Register addressing: the operand is held in a specified register.
• Direct or absolute addressing: the instruction contains the memory address or a substantial part of it.
• Register-indirect addressing: a register contains the operand address.
• Indexed addressing: an index register is added to a base address, useful for arrays and tables.
• Base-plus-offset addressing: a fixed displacement is combined with a base register, common in structured data and stack frames.
• Auto-increment or auto-decrement addressing: the register is adjusted automatically after or before access, useful for streams and stacks.
• Relative addressing: a signed displacement is added to the program counter, supporting position-independent branches.
• Implied addressing: the operand is implicit, such as an instruction that operates on an accumulator or flags.

Addressing modes are not merely syntactic conveniences. They influence relocation, code density, memory traffic, and security. Relative branches, for example, support relocatable code but have limited range. Register-indirect modes support dynamic data structures but require correct pointer initialization. Post-increment addressing can make buffer processing efficient, but a boundary error may lead to memory corruption.

Pipelining and Instruction Throughput

Pipelining divides instruction processing into stages so that different instructions occupy different stages simultaneously. A simple pipeline may contain fetch, decode, execute, memory access, and write-back stages. Once filled, it may complete approximately one instruction per cycle even though each individual instruction takes several stage intervals to pass through the pipeline.

The main benefit is increased throughput, not necessarily reduced latency for a single instruction. Pipeline performance is reduced by hazards:

• Structural hazards occur when two stages require the same hardware resource.
• Data hazards occur when an instruction depends on a result that a preceding instruction has not yet made available.
• Control hazards occur when a branch changes the instruction stream.

Processors address these hazards using stalling, forwarding, instruction scheduling, branch prediction, speculative execution, or separate resources. In small microcontrollers, the pipeline is often shallow and predictable, which is advantageous for real-time analysis. In high-performance processors, deeper pipelines and prediction can improve average performance but make timing less deterministic.

Interrupts and exceptions also interact with pipelines. On recognition, the processor must preserve a precise architectural state or apply a defined mechanism for discarding partially executed instructions. Real-time designers should consult the processor manual for interrupt latency, stacking time, pipeline flush behavior, and priority rules rather than assuming that an interrupt is serviced immediately.

Interrupts and Exceptional Control Flow

An interrupt is a request that causes the processor to suspend normal program execution and transfer control to a handler. Interrupts may be generated by external pins, timers, communication peripherals, analog converters, watchdogs, or software instructions. Exceptions may arise from conditions such as invalid instructions, protection violations, arithmetic faults, or memory errors.

A typical interrupt sequence is:

1. The processor completes or precisely preserves the current instruction according to its architecture.

2. It recognizes an enabled request and determines its priority and vector.

3. The current program state, including the return address and relevant status information, is saved automatically or by software.

4. The processor obtains the handler address from a vector table or fixed entry point.

5. The interrupt-service routine saves any additional registers it will modify.

6. The routine services the event, clears or acknowledges its source, and may communicate with the main program.

7. A return-from-interrupt operation restores the previous state and resumes execution.

Interrupt design requires attention to latency, jitter, nesting, masking, priority inversion, reentrancy, and shared data. A handler should normally be short and deterministic. Lengthy processing is often deferred to a task or main-loop context after the handler records the event. Shared variables should be protected using appropriate atomic operations, critical sections, or synchronization mechanisms. Declaring a variable as volatile may prevent inappropriate compiler optimization, but it does not by itself guarantee atomicity or mutual exclusion.

Von Neumann and Harvard Architectures

In a von Neumann architecture, instructions and data share a common memory and usually a common path to the processor. A unified address space simplifies program development, supports treating code and data through common mechanisms, and permits flexible memory allocation. Its principal limitation is the potential bottleneck created when instruction fetches and data transfers compete for the same path.

In a Harvard architecture, instructions and data are stored in separate memories and accessed through separate paths. This permits an instruction fetch and a data access to occur concurrently. It can improve throughput and allows instruction and data memories to have different widths, technologies, or protection properties. The trade-offs include greater hardware complexity, more complicated memory models, and possible restrictions on treating code as ordinary data.

Many contemporary processors use a modified Harvard architecture. At the processor core, instruction and data paths may be separate, while a unified external memory or address space is provided for software convenience. Separate instruction and data caches are common, with mechanisms for maintaining consistency when code is generated, modified, or transferred.

The choice is not simply a matter of speed. Harvard separation can help protect program memory from accidental data writes, while unified memory can simplify dynamic loading and software tools. In safety-critical or security-sensitive systems, memory protection, execute permissions, bus isolation, and secure boot may matter more than the nominal architectural label.

Applied Scenario: Selecting an Architecture for a Motor-Control Unit

Background

Consider an illustrative industrial motor-control unit that measures current and position, executes a control algorithm at a fixed sampling interval, communicates diagnostic information over a digital network, and drives a power inverter. The system must respond predictably to sensor events and must prevent unsafe outputs if a fault occurs.

Situation and Analysis

A design team initially proposes a processor with a high clock frequency and a unified memory system. Benchmark results show excellent average performance, but control-loop timing varies when communication software performs long memory transfers. Interrupt latency also changes because instruction and data accesses compete for the same path. These variations produce unacceptable control jitter.

The engineering analysis identifies several requirements: deterministic interrupt response, fast access to control variables, efficient multiply–accumulate operations, protected program memory, and independent peripheral operation. The relevant decision is therefore not based solely on clock rate. Pipeline depth, bus organization, interrupt controller behavior, memory wait states, DMA interaction, and timer facilities must all be evaluated.

Approach and Solution

The team selects a microcontroller using separate instruction and data paths, a shallow predictable pipeline, hardware timers, prioritized interrupts, and a memory-protection mechanism. The current and position samples are transferred by a peripheral or DMA mechanism into controlled buffers. The interrupt handler records the sampling event and performs the time-critical portion of the control calculation. Diagnostic communication is assigned a lower priority and is processed outside the most time-sensitive path.

The software team measures worst-case execution time rather than relying on average benchmarks. Shared buffers are designed with clear ownership rules, and fault handlers place the inverter into a safe state. Program memory is configured as non-writable during normal operation, while update procedures use authenticated and controlled reprogramming modes.

Outcome

The resulting architecture provides more predictable control timing, reduces interference between communication and sampling, and improves fault containment. It may not deliver the highest general-purpose benchmark score, but it better satisfies the actual engineering objectives.

Learning Points

The scenario illustrates that processor selection is a systems decision. Architecture affects timing determinism, safety, memory protection, software complexity, and verification effort. Average throughput is only one performance measure; worst-case latency and reproducibility are often more important in embedded control.

Challenges, Risks, and Common Design Errors

Several errors repeatedly occur in processor-based designs. Treating clock frequency as a complete measure of performance ignores memory and pipeline behavior. Confusing carry with signed overflow produces incorrect arithmetic decisions. Assuming that a memory-mapped peripheral behaves like ordinary RAM overlooks read and write side effects. Failing to initialize the stack or interrupt vector table can cause apparently random failures.

Other risks include unbounded work inside interrupt handlers, incorrect clearing of interrupt sources, data races between handlers and foreground code, unaligned accesses where the architecture does not support them, and failure to account for cache or buffer coherency. In Harvard or modified Harvard systems, self-modifying code and dynamically loaded instructions require explicit synchronization and cache-management procedures.

Reset behavior deserves particular attention. A processor may begin execution before all peripherals are configured, so startup code must establish stack, clocks, memory regions, exception vectors, and safety-related outputs in a controlled sequence. Brownout, watchdog, illegal instruction, and memory faults should be treated as engineering conditions requiring defined recovery behavior rather than ignored anomalies.

Professional and Ethical Considerations

Processor architecture decisions can affect human safety, privacy, equipment reliability, and regulatory compliance. Engineers should document timing assumptions, interrupt priorities, memory maps, safety mechanisms, and hardware–software interfaces. Claims about real-time behavior should be supported by measurement and worst-case analysis, not by nominal clock speed.

Where processors control machinery, transportation systems, medical devices, or energy infrastructure, traceability and verification are essential. Secure boot, authenticated firmware, privilege separation, protected debug interfaces, and controlled software updates may be required to prevent unauthorized changes. Ethical engineering also requires communicating limitations honestly, particularly when a processor has not been validated for the required temperature, electromagnetic, functional-safety, or security environment.

Contemporary Developments

Modern microcontrollers increasingly combine conventional processor cores with digital-signal-processing extensions, floating-point units, cryptographic accelerators, real-time operating-system support, and hardware security modules. Heterogeneous systems may combine general-purpose cores with real-time cores, graphics units, or machine-learning accelerators. These developments increase capability but also make memory coherency, scheduling, isolation, and verification more complex.

RISC-style instruction sets emphasize regular encoding and efficient implementation, while complex instruction sets may provide dense code and specialized operations. The distinction is less important than the actual implementation, compiler quality, memory system, and workload. Open instruction-set ecosystems have also encouraged customized extensions, but such extensions must be balanced against toolchain support, portability, verification effort, and long-term maintenance.

Energy-aware architecture is another major development. Dynamic voltage and frequency scaling, clock gating, sleep states, event-driven peripherals, and near-memory processing reduce energy consumption. In battery-powered systems, the best architecture may be the one that completes work quickly and returns to a low-power state, rather than the one with the lowest active power alone.

Best Practices for Architectural Analysis

A sound analysis begins by separating requirements into functional, timing, memory, power, safety, security, and maintainability categories. The engineer should then identify the instruction-set features, register organization, bus structure, interrupt behavior, memory architecture, and peripheral capabilities relevant to each requirement.

For practical evaluation:

• Use instruction-level and system-level timing measurements.
• Determine worst-case interrupt latency and execution time.
• Document memory maps and all peripheral side effects.
• Keep interrupt handlers short, bounded, and reentrant where required.
• Define ownership and synchronization rules for shared data.
• Verify reset, exception, watchdog, and fault behavior.
• Consider compiler output, alignment, cache behavior, and toolchain support.
• Evaluate security and update mechanisms as part of architecture, not as late additions.

These practices connect architectural knowledge with reliable engineering decisions.

Chapter Summary

Processor architecture defines how computation, storage, control, and communication are organized, while processor operation describes how instructions move through that organization. The ALU performs arithmetic and logical operations and generates status flags; registers hold operands, addresses, results, and control state; and the control unit coordinates data movement and timing. Address, data, and control buses provide the communication paths among processor, memory, and peripherals.

Instruction execution commonly involves fetch, decode, operand access, execution, and completion. Addressing modes determine how operands are located and influence code density, flexibility, and timing. Pipelining improves throughput by overlapping instruction stages but introduces structural, data, and control hazards. Interrupts provide event-driven control transfer and must be designed with attention to latency, priority, state preservation, and shared data.

Von Neumann systems use shared instruction and data storage, whereas Harvard systems separate them; modified Harvard designs combine aspects of both. Architectural selection should be based on workload, determinism, memory behavior, safety, security, power, and verification requirements rather than clock frequency alone.

Key Terms

ALU: Hardware unit that performs arithmetic, logical, comparison, and shift operations.

Address bus: Path carrying the address of a memory or peripheral location.

Addressing mode: Rule that specifies how an instruction identifies or calculates its operand.

Control unit: Processor component that interprets instructions and generates coordination signals.

Data bus: Path used to transfer instruction and data values.

Exception: A processor-generated control transfer caused by a fault or special execution condition.

Flag register: Register containing status bits such as zero, carry, negative, and overflow.

Harvard architecture: Architecture with separate instruction and data memories or access paths.

Instruction cycle: Complete sequence required to fetch and execute an instruction.

Interrupt: Event-driven request that temporarily transfers execution to a service routine.

Instruction-set architecture: Programmer-visible specification of instructions, registers, data types, and execution rules.

Microarchitecture: Internal implementation of an instruction-set architecture.

Pipeline: Overlapped sequence of instruction-processing stages.

Program counter: Register containing the address of the next instruction to be fetched.

Register: High-speed storage element located within the processor.

Stack pointer: Register identifying the current top of the run-time stack.

von Neumann architecture: Architecture in which instructions and data share memory and commonly share access paths.

Wait state: Additional clock interval inserted because a memory or peripheral is not ready.

Review Questions

Short Answer Questions

1. Distinguish between the program counter, instruction register, and stack pointer.

2. Why is signed overflow different from an unsigned carry?

3. What is the purpose of an address bus, data bus, and control bus?

4. Define a pipeline hazard and identify its three main types.

5. What information is typically saved when an interrupt is accepted?

Long Answer Questions

1. Explain the fetch–decode–execute process and relate each stage to the roles of the datapath and control unit.

2. Discuss common addressing modes and analyze their effects on code size, flexibility, and execution time.

3. Explain pipelining in detail, including its benefits, hazards, and methods of hazard handling.

4. Compare von Neumann, Harvard, and modified Harvard architectures with respect to memory organization, performance, flexibility, and security.

5. Describe the complete interrupt-service sequence and discuss interrupt latency, priority, nesting, and shared-data issues.

Analytical / Application Questions

1. A processor has a high clock frequency but experiences long and variable memory wait states. Explain why its real-time performance may be inferior to that of a slower processor with predictable memory access.

2. Design an interrupt strategy for a motor-control system that receives periodic sensor samples and lower-priority diagnostic messages. Justify your choices of priority, handler length, buffering, and deferred processing.

3. A system must execute code from protected memory while permitting data buffers to be modified during operation. Recommend an appropriate memory organization and explain the architectural and security considerations.

22. Multiple Choice Questions with Answers

Question 1

Which processor component primarily generates control signals for register transfers, ALU selection, and memory operations?

A. Control unit

B. Data bus

C. Stack pointer

D. Address decoder

Correct Answer: A. Control unit

Question 2

A signed addition produces a result whose sign is incorrect even though no unsigned carry is produced. Which condition has most likely occurred?

A. Zero

B. Signed overflow

C. Parity

D. Address wraparound

Correct Answer: B. Signed overflow

Question 3

What is the principal performance advantage of a Harvard architecture?

A. It eliminates the need for registers

B. It allows instruction and data accesses to use separate paths

C. It guarantees that every instruction takes one clock cycle

D. It prevents all software faults

Correct Answer: B. It allows instruction and data accesses to use separate paths

Question 4

An instruction uses a register containing the address of an operand. Which addressing mode is being used?

A. Immediate

B. Implied

C. Register-indirect

D. Relative

Correct Answer: C. Register-indirect

Question 5

Which situation is a control hazard in a pipeline?

A. Two stages require the same multiplier

B. An instruction depends on an unfinished arithmetic result

C. A branch changes the sequence of instructions being fetched

D. A peripheral inserts a wait state during a write

Correct Answer: C. A branch changes the sequence of instructions being fetched

Question 6

Why may increasing processor clock frequency fail to produce proportional performance improvement?

A. Registers stop operating at higher frequencies

B. Memory latency, stalls, and bus contention may dominate execution time

C. The ALU performs fewer logical operations at higher frequencies

D. Addressing modes are disabled at higher frequencies

Correct Answer: B. Memory latency, stalls, and bus contention may dominate execution time

Question 7

Which practice is generally most appropriate for a time-critical interrupt-service routine?

A. Perform extensive diagnostic formatting inside the handler

B. Leave the interrupt source uncleared

C. Record the event, perform bounded urgent work, and defer lengthy processing

D. Disable all interrupts permanently

Correct Answer: C. Record the event, perform bounded urgent work, and defer lengthy processing

Question 8

In a memory-mapped I/O system, a peripheral status register differs from ordinary RAM because

A. it cannot have an address

B. a read or write may produce hardware side effects

C. it is always located outside the processor address space

D. it can only be accessed by the ALU

Correct Answer: B. a read or write may produce hardware side effects

Question 9

Which design choice best supports deterministic motor-control timing?

A. Using only average benchmark performance for selection

B. Allowing unbounded work in high-priority handlers

C. Analyzing worst-case latency, pipeline behavior, memory waits, and interrupt priorities

D. Maximizing diagnostic traffic during the control interval

Correct Answer: C. Analyzing worst-case latency, pipeline behavior, memory waits, and interrupt priorities

Question 10

What is a defining feature of a modified Harvard architecture?

A. It has no separate instruction-processing stage

B. It combines separate internal instruction and data paths with some unified memory or external access

C. It stores all data only in registers

D. It prohibits instruction fetching from memory

Correct Answer: B. It combines separate internal instruction and data paths with some unified memory or external access