5. Memory Systems and Bus Architecture

Introduction and Context

A microprocessor can perform arithmetic and logical operations only when instructions and data are supplied to it. Memory systems provide the storage hierarchy through which programs, operands, intermediate results, and peripheral data are accessed. The bus architecture, in turn, provides the electrical and logical pathways connecting the processor, memory, and input/output devices. Together, memory organization and bus design strongly influence system capacity, performance, cost, reliability, and security.

At a basic level, a processor issues an address, specifies an operation such as read or write, and exchanges data with a selected device. In an actual embedded or computing system, however, this apparently simple transaction involves address decoding, timing control, arbitration, buffering, synchronization, protection, and sometimes direct memory access. A sound understanding of these mechanisms is essential for designing microcontroller systems, high-performance processors, industrial controllers, automotive electronics, and embedded computing platforms.

Memory design is not merely a matter of selecting a RAM or ROM device. The designer must determine the address space, map devices into that space, meet timing requirements, account for volatility and endurance, and ensure that illegal or malicious accesses are controlled. Similarly, a bus is not simply a group of wires; it is a protocol that defines ownership, timing, signaling, data transfer, and error handling.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the organization and characteristics of semiconductor memory technologies.

2. Design an address map and an address-decoding scheme for a processor-based system.

3. Distinguish between SRAM, DRAM, ROM, EEPROM, Flash, cache, and virtual memory.

4. Explain memory-mapped I/O and compare it with isolated I/O.

5. Analyze bus structure, synchronous and asynchronous transfers, arbitration, and DMA.

6. Explain memory protection and the role of memory-management hardware.

7. Select suitable memory and bus arrangements for practical embedded applications.

8. Identify common design errors, performance bottlenecks, and security risks.

The Memory Hierarchy and Its Design Logic

No single memory technology simultaneously provides maximum speed, capacity, low cost, non-volatility, and unlimited endurance. Computer systems therefore use a hierarchy. Registers are closest to the execution unit and are extremely fast but small. Cache memory stores recently or frequently used instructions and data. Main memory provides working storage, while secondary or non-volatile storage retains programs and data when power is removed.

The hierarchy operates on the principle of locality. Temporal locality means that a recently used item is likely to be used again. Spatial locality means that an address near a recently used address is likely to be accessed soon. Caches exploit both properties by transferring blocks, called cache lines, rather than isolated bytes. The effectiveness of a cache is often expressed through its hit ratio. If the cache hit time is t_c, the main-memory access time is t_m, and the hit ratio is h, the approximate average access time is:

Average access time = h t_c + (1 − h)(t_c + t_m)

This expression shows why even a relatively small cache can improve performance substantially when the hit ratio is high. It also shows that a cache miss carries the cost of checking the cache in addition to fetching data from the next level.

Semiconductor Memory Technologies

RAM

Random-access memory permits approximately uniform access to locations. Static RAM (SRAM) stores each bit in a bistable circuit, commonly a flip-flop. It does not require refresh while powered, has low access latency, and is easy to interface, but it occupies more silicon area and is more expensive per bit than dynamic RAM. SRAM is therefore common in processor caches, microcontroller data memory, and high-speed buffers.

Dynamic RAM (DRAM) stores a bit as charge in a capacitor controlled by a transistor. Charge leakage requires periodic refresh. DRAM offers high density and lower cost per bit, making it suitable for main memory. Its controller must manage row activation, column access, refresh, timing constraints, and sometimes error correction. Modern synchronous DRAM transfers data in relation to a clock and may support burst operation.

Read-Only and Non-Volatile Memory

Mask ROM is programmed during manufacture and is economical in very high-volume products, but its contents cannot be changed. Programmable ROM can be programmed after manufacture. Electrically erasable programmable ROM (EEPROM) permits electrical erasure and rewriting, often at byte or word granularity, although writing is slower and endurance is finite.

Flash memory is electrically erasable and programmable, normally in blocks or sectors. It provides non-volatile storage with high density and is widely used for firmware, solid-state storage, and memory cards. NAND Flash is optimized for high-density data storage, whereas NOR Flash provides relatively fast random read access and is commonly used for execute-in-place firmware. Flash memory has limited program/erase endurance, so controllers use wear leveling, bad-block management, and error-correcting codes.

Comparative Selection

Memory selection should be based on access pattern rather than capacity alone. SRAM is suitable for deterministic, high-speed temporary storage. DRAM is appropriate where large working memory is required and a memory controller is acceptable. NOR Flash is useful for firmware execution and random reads; NAND Flash is preferable for large storage volumes. EEPROM is useful for configuration data that changes relatively infrequently. Non-volatile memory should not be treated as unlimited-write storage.

Address Spaces, Address Maps, and Decoding

An n-bit address bus can theoretically identify 2^n distinct address locations. If each location holds one byte, the address space is 2^n bytes. A processor with a 32-bit address bus therefore has a theoretical 4 GiB byte-addressable space, although the actual implemented range may be smaller.

An address map assigns non-overlapping address intervals to memory and peripherals. A representative map might place boot Flash at the lower address range, SRAM immediately above it, and peripheral registers in a separate region. The precise arrangement depends on processor conventions, boot requirements, linker configuration, interrupt-vector placement, and hardware constraints.

A memory map should specify:

• start and end address of each device;
• size and data width of each region;
• read, write, and execute permissions;
• reset and boot behavior;
• reserved or unmapped areas;
• alignment and access restrictions; and
• aliasing, if more than one address refers to the same physical storage.

Address Decoding

Address decoding generates a chip-select signal when the processor address falls within a device's assigned range. Full decoding examines all relevant address lines and produces a unique selection for each device. It prevents address aliasing but requires more logic. Partial decoding examines only some address bits. It reduces hardware but allows multiple addresses to select the same device.

For example, suppose a 16-bit processor addresses 64 KiB and a 16 KiB ROM is assigned from 0000H to 3FFFH. The ROM requires fourteen internal address lines, A0 through A13. The upper two processor address lines, A14 and A15, must both be zero for the ROM to be selected. A two-input NOR-based or equivalent logic arrangement can generate the chip-select condition. If A14 is ignored, the ROM may also appear at 4000H–7FFFH, producing an alias.

Address decoding can be implemented using gates, decoders, programmable logic, or integrated memory controllers. A practical design must also consider active-low signals, propagation delay, bus contention, setup and hold times, and whether address lines remain stable for the complete transfer.

Memory Timing and Interface Signals

A memory read normally proceeds through several events. The processor places an address on the address bus, asserts a read control signal, and waits for the selected memory to provide valid data. The memory decodes the address, drives the data bus, and may assert a ready or acknowledge signal. The processor samples the data and terminates the cycle.

Important timing parameters include address-access time, read-cycle time, write-recovery time, setup time, and hold time. If a memory device is slower than the processor's default cycle, wait states must be inserted. A wait state extends the transfer until the device asserts readiness. Failure to provide sufficient delay can lead to intermittent and difficult-to-reproduce errors.

In a write cycle, the processor drives both address and data and asserts write enable. The receiving device must capture the data within the required setup and hold intervals. Tri-state outputs are essential on shared data buses: only the selected device should drive the bus during a read, while other devices remain electrically disconnected.

Cache Organization and Coherence

A cache is a small, fast memory between a processor and a slower memory level. Its organization is described by line size, number of lines, associativity, replacement policy, and write policy. In a direct-mapped cache, each memory block has one possible cache location. In a fully associative cache, a block may occupy any line. Set-associative caches provide an intermediate arrangement.

Write-through caching updates the lower memory level whenever the processor writes the cache. It simplifies consistency but generates more traffic. Write-back caching updates only the cache initially and writes the modified line to lower memory when it is evicted. It reduces traffic but requires dirty-bit management.

In systems containing DMA engines, multiple processors, or peripheral masters, cache coherence becomes important. A DMA controller may write new data into main memory while the processor still holds an old copy in its cache. The software or hardware must use cache clean, invalidate, or coherent-interconnect mechanisms. Incorrect cache maintenance can produce data corruption even when the bus transactions themselves are electrically correct.

Virtual Memory and Protection

Virtual memory separates the addresses generated by a program from physical memory addresses. A memory-management unit translates virtual pages into physical frames using page tables. A translation lookaside buffer caches recent translations to avoid repeated page-table walks.

Virtual memory supports process isolation, controlled sharing, relocation, and use of storage beyond available physical RAM. A page may be marked readable, writable, executable, or inaccessible. A page fault occurs when a translation is absent or an access violates its permissions. In a general-purpose operating system, the fault may cause a page to be loaded from secondary storage; in an embedded real-time system, protection may be used without relying on paging.

Microcontrollers often employ a memory protection unit rather than full virtual memory. An MPU divides the address space into regions and assigns permissions and attributes such as read-only, executable, device, or non-cacheable. This arrangement is valuable for isolating safety-critical tasks, preventing stack overflow from damaging control registers, and restricting untrusted software.

Bus Architecture and Transfer Protocols

A system bus traditionally contains address, data, and control signals. Modern systems may use separate instruction and data paths, split transactions, packetized interconnects, or point-to-point links. The essential function remains the same: establish a source, a destination, a transfer type, timing, and ownership.

A synchronous bus uses a shared clock. Transfers occur at defined clock edges, making timing predictable and simplifying design at moderate distances. Its limitation is that the clock must accommodate the slowest relevant path and must be distributed with controlled skew.

An asynchronous bus uses handshaking signals such as request and acknowledge. The source initiates a transaction, and the destination responds when ready. This permits devices with different speeds to communicate without a common timing assumption, although the protocol and control logic are more complex.

A bus may be single-master or multi-master. In a single-master arrangement, the processor controls all transfers. In a multi-master system, processors, DMA controllers, or intelligent peripherals may request ownership. Arbitration determines which master receives access. Fixed-priority arbitration is simple but may starve low-priority devices. Round-robin arbitration improves fairness, while weighted schemes can provide controlled service for real-time traffic.

Modern interconnects often support burst transfers, separate read and write channels, outstanding transactions, and quality-of-service controls. These features increase throughput but also complicate ordering, buffering, and verification.

DMA and Memory-Mapped I/O

Direct memory access allows a peripheral or DMA controller to transfer data between a device and memory without requiring the processor to move every word. The processor initializes the source address, destination address, transfer count, direction, and control attributes. The DMA controller then requests bus access, performs transfers, updates its address and count, and typically interrupts the processor on completion or error.

DMA is effective for high-volume transfers such as network packets, audio streams, disk blocks, and sensor data. It reduces processor overhead but introduces bus contention, cache-coherence issues, buffer ownership problems, and security concerns. Descriptors and addresses supplied to a DMA engine must be validated; otherwise, a faulty or compromised peripheral could overwrite protected memory.

In memory-mapped I/O, peripheral registers occupy ordinary processor addresses. The processor uses load and store instructions to access control, status, and data registers. Registers must be declared volatile in software because their values may change independently of program flow. Some registers have side effects: reading may clear a status bit, and writing a one may acknowledge an interrupt. Hardware and software specifications must therefore define access width, alignment, reset value, and permissible operations.

Memory-mapped I/O simplifies the instruction set and permits uniform address decoding. However, peripheral regions must generally be marked non-cacheable and strongly ordered, since caching a status register or reordering control writes can produce incorrect behavior. Isolated I/O, used in some processor families, employs separate instructions and a distinct I/O address space.

Applied Design Example: Controller for an Industrial Sensor Node

Background

Consider an illustrative sensor node based on a 32-bit microcontroller. The node samples vibration and temperature, performs local filtering, stores calibration data, and transmits records to a supervisory controller. The design must boot reliably, protect the control firmware, and move sampled data with minimal CPU overhead.

Situation and Requirements

The proposed system requires 512 KiB of non-volatile firmware storage, 128 KiB of SRAM, a DMA-capable analog-to-digital converter, and memory-mapped control registers. Firmware updates must not destroy the currently executing image. Sensor acquisition must remain deterministic even while communication traffic is present.

Analysis and Architecture

The designer assigns two Flash banks to separate firmware images, a protected boot region, SRAM for stacks and control variables, and a circular DMA buffer for samples. Peripheral registers are mapped into a non-cacheable device region. The DMA buffer is aligned to cache-line boundaries, and the software explicitly cleans or invalidates cache lines when required by the processor architecture.

Full decoding is used for the principal memory regions to avoid accidental aliases. The boot code validates an image before transferring control to it. The MPU marks boot code as read-only and executable, calibration constants as read-only, peripheral registers as device memory, and the DMA buffer as non-executable. A watchdog and bus-error handler provide recovery for abnormal conditions.

Approach and Outcome

The ADC generates requests at a fixed sampling rate. DMA writes samples into alternating buffers while the processor filters the completed buffer. A transfer-complete interrupt changes buffer ownership. Communication uses a lower-priority DMA channel, while the acquisition channel receives sufficient arbitration priority to meet its timing requirement. Flash wear is reduced by storing calibration updates in a managed region rather than rewriting the firmware bank.

This architecture separates program storage, working data, peripheral access, and DMA ownership. It improves determinism and makes faults easier to diagnose. It also demonstrates that memory mapping, bus arbitration, protection, and software design must be considered together rather than as isolated hardware decisions.

Learning Points

The case illustrates five important principles: address maps should reflect protection and boot requirements; DMA improves throughput but requires explicit buffer ownership; cache attributes must match device behavior; arbitration affects real-time performance; and non-volatile endurance must influence data-placement decisions.

Design Risks and Common Errors

Several failures recur in memory and bus designs. Incomplete decoding may cause aliases that hide software defects. Overlapping chip-select ranges can make two devices drive the data bus simultaneously. Incorrect wait-state configuration can produce temperature-dependent failures. Ignoring alignment and access width can trigger bus faults or unintended peripheral behavior.

Other common mistakes include caching device registers, failing to clean or invalidate buffers used by DMA, assuming that a write has reached a peripheral before an ordering barrier, and permitting unvalidated DMA descriptors. Firmware that stores frequently changing data directly in Flash may exhaust its endurance. A memory map that does not reserve future expansion space can make later product revisions unnecessarily difficult.

Security and safety require particular attention. Code should not execute from writable data regions unless explicitly intended. Boot memory should be authenticated where the threat model demands it. Protection boundaries should be tested under fault conditions, not only during normal operation. In safety-related systems, memory tests, ECC or parity, watchdog supervision, and documented fault responses may be required by the applicable engineering standard.

Contemporary Directions

Recent processor platforms increasingly use coherent system interconnects, multiple independent bus masters, and memory controllers with error correction. Non-volatile memories are being developed with lower latency and greater endurance, although their programming and retention characteristics remain technology-dependent. Hardware virtualization and trusted execution mechanisms extend memory protection to multiple operating environments.

Design automation also plays a growing role. Electronic-design-automation tools can generate interconnect fabrics, verify address maps, and detect overlapping regions. Software development kits may generate peripheral headers and linker scripts from machine-readable hardware descriptions. Formal checks and transaction-level simulation can identify protocol violations before hardware is manufactured. These tools improve reliability, but they do not replace engineering judgment about timing, privilege, failure modes, or system-level behavior.

Best Practices for Engineering Practice

A robust design normally follows these principles:

• Define the complete address map before selecting final decoding logic.
• Document reset addresses, permissions, widths, alignment, and reserved regions.
• Use full decoding where uniqueness and safety are more important than minimal logic.
• Verify timing with worst-case device specifications, clock tolerance, and temperature.
• Treat peripheral registers as device memory and specify side effects explicitly.
• Design DMA buffers, cache maintenance, and ownership rules together.
• Use protection regions to separate code, data, stacks, peripherals, and untrusted inputs.
• Include error detection, diagnostic access, and recovery paths.
• Test boundary addresses, illegal accesses, simultaneous masters, and reset transitions.
• Plan for firmware updates, Flash endurance, expansion, and long-term maintainability.

Chapter Summary

Memory systems provide the storage hierarchy required by processors, while bus architecture defines how processors, memories, and peripherals exchange information. SRAM offers speed, DRAM density, Flash non-volatility, and EEPROM convenient small-scale rewriting. Address maps assign devices to ranges, and decoding converts address conditions into chip-select signals; incomplete decoding can create aliases. Timing design must account for access delays, wait states, setup, hold, and bus turnaround.

Caches improve average performance by exploiting locality, but write policies and coherence become important when DMA or multiple masters are present. Virtual memory and MPUs provide translation, isolation, and access permissions. Bus protocols may be synchronous or asynchronous and may require arbitration among several masters. DMA increases transfer efficiency but introduces ownership, coherence, and security issues. Memory-mapped I/O provides uniform access to peripherals, provided that device attributes and register side effects are correctly handled. Effective engineering integrates memory technology, address decoding, protection, timing, bus protocol, software, and verification into one system design.

Key Terms

Address bus: Signal lines carrying the address of a memory location or peripheral register.

Address decoding: Logic that selects a device according to an address range.

Address map: Assignment of address intervals to memories, peripherals, and reserved regions.

SRAM: Volatile semiconductor memory using bistable storage cells without refresh.

DRAM: Volatile, high-density memory that stores charge and requires refresh.

Flash memory: Non-volatile electrically programmable memory erased in sectors or blocks.

Cache: Small, fast memory that stores recently or frequently accessed data and instructions.

Cache line: Unit of data transferred between a cache and a lower memory level.

Memory-mapped I/O: Accessing peripheral registers through the processor's memory address space.

DMA: Direct memory access performed by a controller without processor movement of every data item.

Bus arbitration: Procedure for granting shared bus ownership to one of several masters.

Wait state: Additional bus cycle inserted to accommodate a slower device.

Memory protection unit: Hardware that assigns access permissions to physical address regions.

Virtual memory: Address-translation system that presents processes with protected virtual address spaces.

Chip select: Control signal enabling a particular memory or peripheral device.

Bus contention: Electrical conflict caused by multiple devices driving a shared bus simultaneously.

Write-through: Cache policy that updates lower memory on each cache write.

Write-back: Cache policy that delays lower-memory updates until a modified line is evicted.

Cache coherence: Consistency of data copies held by caches and other bus masters.

Review Questions

Short Answer Questions

1. Why is address decoding required in a processor-based system?

2. Distinguish between SRAM and DRAM in terms of storage mechanism and use.

3. What is the purpose of a wait state?

4. Define memory-mapped I/O and state one design precaution.

5. What problem does DMA solve, and what new problem can it introduce?

Long Answer Questions

1. Explain how a complete memory map is developed and discuss the consequences of incomplete decoding.

2. Compare SRAM, DRAM, EEPROM, NOR Flash, and NAND Flash for embedded-system applications.

3. Describe cache organization, write-through and write-back policies, and cache coherence.

4. Explain synchronous and asynchronous buses, including arbitration in a multi-master system.

5. Discuss virtual memory, an MPU, and their roles in isolation, safety, and security.

Analytical / Application Questions

1. A 16-bit processor uses a 64 KiB address space. Design the address allocation and decoding conditions for a 16 KiB ROM at 0000H and an 8 KiB RAM at 8000H. Identify any unused regions.

2. A DMA peripheral writes sensor samples into memory while the processor analyzes the previous buffer. Explain the cache, ownership, arbitration, and interrupt issues that must be addressed.

3. An industrial controller experiences occasional failures when reading a peripheral status register. Analyze how caching, access width, wait states, register side effects, and bus timing could cause the problem, and propose a verification plan.

22. Multiple Choice Questions with Answers

Question 1

A 16-bit byte-addressable processor assigns a 16 KiB ROM from 0000H to 3FFFH. Which address condition selects the ROM under full decoding?

A. A15 = 0 and A14 = 0

B. A15 = 1 and A14 = 0

C. A15 = 0 and A14 = 1

D. A15 = 1 and A14 = 1

Correct Answer: A. A15 = 0 and A14 = 0

Question 2

Which memory technology normally requires periodic refresh because it stores information as charge?

A. SRAM

B. DRAM

C. NOR Flash

D. EEPROM

Correct Answer: B. DRAM

Question 3

What is the principal danger of using incomplete address decoding?

A. The memory becomes non-volatile

B. The processor loses its clock

C. A device may appear at multiple address ranges

D. The data bus becomes wider

Correct Answer: C. A device may appear at multiple address ranges

Question 4

Which cache policy generally reduces write traffic to lower memory but requires dirty-bit management?

A. Write-through

B. Write-back

C. Read-around

D. No-write-allocate

Correct Answer: B. Write-back

Question 5

A DMA controller writes new data into main memory, but the processor reads an old cached copy. What issue is illustrated?

A. Bus arbitration failure

B. Cache incoherence

C. Address aliasing only

D. Flash endurance loss

Correct Answer: B. Cache incoherence

Question 6

Which mechanism is most appropriate for preventing an application from writing to firmware and peripheral-control regions in a microcontroller?

A. A memory protection unit

B. A larger data bus

C. A write-through cache

D. A parity generator alone

Correct Answer: A. A memory protection unit

Question 7

In an asynchronous bus, the receiving device commonly indicates completion using which mechanism?

A. A fixed clock edge only

B. A request-acknowledge handshake

C. A cache-line tag

D. A Flash erase pulse

Correct Answer: B. A request-acknowledge handshake

Question 8

Why should memory-mapped peripheral registers generally be marked non-cacheable?

A. They contain no binary data

B. Caching can return stale values or delay control writes

C. They require periodic refresh

D. They can only be accessed by DMA

Correct Answer: B. Caching can return stale values or delay control writes

Question 9

A low-priority bus master never receives access under fixed-priority arbitration. Which change most directly improves fairness?

A. Use round-robin arbitration

B. Reduce the address width

C. Disable chip select

D. Replace SRAM with ROM

Correct Answer: A. Use round-robin arbitration

Question 10

Which design practice best protects a DMA-based sensor buffer?

A. Allow every peripheral to write to it

B. Ignore cache-line alignment

C. Define buffer ownership and perform required cache maintenance

D. Map it as executable Flash

Correct Answer: C. Define buffer ownership and perform required cache maintenance