Embedded Hardware and Processor Architectures

Introduction

Embedded systems are computing systems designed for a dedicated function within a larger product. Unlike general-purpose computers, they are usually constrained by cost, physical size, energy consumption, response time, reliability, and environmental conditions. A smart thermostat, industrial motor controller, fitness tracker, automobile braking controller, and connected door lock are all embedded systems. The Internet of Things (IoT) extends embedded systems by connecting sensors, actuators, gateways, and cloud services through communication networks.

Hardware architecture is therefore a foundational design decision. The selected processor, memory arrangement, buses, input/output circuitry, power supply, and timing mechanisms determine what the system can sense, compute, communicate, and control. A technically powerful processor may be unsuitable if it consumes excessive energy or requires an expensive circuit board. Conversely, an inexpensive microcontroller may fail when the application requires high computational performance, large memory, or a sophisticated operating system.

This chapter examines the principal embedded hardware choices and the mechanisms that allow processors to interact reliably with the physical world.

Learning Objectives

By the end of this chapter, a student should be able to:

1. Distinguish microcontrollers, microprocessors, systems-on-chip, and programmable logic devices.
2. Explain CPU architecture, instruction execution, memory organization, and buses.
3. Describe GPIO, timers, interrupts, DMA, and watchdog timers.
4. Analyze embedded power-supply requirements and energy consumption.
5. Select hardware using cost, performance, reliability, security, and energy criteria.
6. Apply these concepts to an IoT product design.

1. Embedded Computing Platforms

1.1 Microcontrollers

A microcontroller unit (MCU) integrates a processor core, program memory, data memory, timers, communication peripherals, and general-purpose input/output (GPIO) on one integrated circuit. Many MCUs also include analog-to-digital converters, digital-to-analog converters, pulse-width-modulation units, cryptographic accelerators, and low-power operating modes.

An MCU is appropriate when the application performs control-oriented tasks such as reading sensors, executing a finite-state machine, driving actuators, or communicating through a modest protocol. It normally executes firmware from on-chip flash memory and uses static random-access memory (SRAM) for variables and the stack.

Advantages include low cost, low power consumption, predictable timing, rapid startup, and a small external component count. Limitations include restricted memory, lower processing performance, and less support for complex operating systems.

1.2 Microprocessors

A microprocessor unit (MPU) generally contains a CPU but depends on external memory and, often, external peripheral controllers. Modern MPUs frequently include memory-management units (MMUs), caches, floating-point units, and multicore processors. They can run Linux or another feature-rich operating system and support networking, graphical interfaces, databases, and high-level applications.

The advantages of an MPU are computational capability, large memory support, and software flexibility. The disadvantages are higher power consumption, longer boot time, greater board complexity, and less deterministic timing. An MPU-based design is often justified for an IoT gateway, industrial human-machine interface, or vision system rather than a simple sensor node.

1.3 Systems-on-Chip

A system-on-chip (SoC) integrates several major subsystems on one chip. Depending on the product, an SoC may combine CPU cores, memory controllers, wireless radios, graphics processors, security hardware, timers, and peripheral interfaces. A wireless IoT SoC may include a microcontroller core and Bluetooth Low Energy or Wi-Fi radio. A mobile or edge-computing SoC may contain heterogeneous CPU cores, a graphics processor, and artificial-intelligence acceleration.

The word SoC describes integration, not a single performance level. Some SoCs are simple low-power controllers; others are powerful application processors. Integration reduces board area and can improve energy efficiency, but it can increase design dependence on one vendor and complicate thermal or software migration.

1.4 Other architectural choices

Digital signal processors (DSPs) are optimized for repetitive numerical operations such as filtering and spectral analysis. Field-programmable gate arrays (FPGAs) implement hardware logic that can be configured after manufacture. They offer high parallelism and precise timing but require specialized design skills and generally have greater development cost. Application-specific integrated circuits (ASICs) provide excellent performance, energy efficiency, and volume economics, but their nonrecurring engineering cost is high and changes after fabrication are difficult.

2. CPU Architecture and Instruction Execution

2.1 Instruction-set architecture and microarchitecture

The instruction-set architecture (ISA) is the programmer-visible specification of a processor. It defines instructions, registers, data types, addressing modes, privilege levels, and memory behavior. Examples include ARM, RISC-V, and x86 families. Microarchitecture is the internal implementation used to execute that ISA, including pipelines, caches, branch prediction, and execution units.

Reduced instruction set computer (RISC) designs generally use a relatively regular instruction set, many registers, and load/store memory access. Complex instruction set computer (CISC) designs may provide more elaborate instructions and addressing modes. The distinction is useful historically, but modern processors often combine features from both approaches.

2.2 Registers, datapath, and control

Registers are small, fast storage locations inside the CPU. A typical processor includes general-purpose registers, a program counter (PC), a stack pointer (SP), and a status or condition register. The datapath contains arithmetic-logic units (ALUs), shifters, multipliers, and register connections. The control unit decodes instructions and generates signals that coordinate execution.

A simplified instruction cycle is:

1. Fetch the instruction from memory using the PC.
2. Decode the operation and identify operands.
3. Read registers or access memory.
4. Execute the arithmetic, logical, or control operation.
5. Write the result and update status flags.
6. Advance or modify the PC.

Pipelining overlaps these stages to increase instruction throughput. However, branches, data dependencies, interrupts, and memory delays can prevent ideal performance. Thus, clock frequency alone is not a sufficient measure of system performance.

2.3 Performance measures

A useful first-order relationship for CPU execution time is:

where T_CPU is CPU execution time in seconds, N_I is the number of executed instructions, CPI is the average number of clock cycles per instruction, and T_cycle is the clock period in seconds. The relationship assumes that the measured instruction count and average CPI represent the workload and that other delays are included appropriately.

Since T_cycle = 1/f_clk, the equation can also be written as:

where f_clk is clock frequency in hertz. Increasing frequency may reduce execution time, but it commonly increases dynamic power and may create thermal or electromagnetic-interference problems. Memory latency, cache behavior, compiler quality, and peripheral waiting can dominate actual performance.

2.4 Determinism and real-time behavior

A real-time system must produce a correct result within a required time limit. A hard real-time deadline must not be missed; a soft real-time system tolerates occasional delay with degraded quality. MCUs are attractive for hard real-time control because their interrupt latency and peripheral behavior can be relatively predictable. Caches, speculative execution, virtual memory, and complex operating systems improve average performance but may increase timing variability.

3. Memory Organization

3.1 Memory types

Embedded systems commonly use the following memory technologies:

• ROM or mask ROM: Nonvolatile memory programmed during manufacture.
• Flash: Nonvolatile, electrically erasable memory used for firmware; writes are slower and have finite endurance.
• SRAM: Fast volatile memory used for variables, stacks, buffers, and caches; it requires more silicon area per bit than DRAM.
• DRAM: Dense volatile memory requiring refresh; common in application processors.
• EEPROM: Electrically erasable nonvolatile memory useful for relatively small configuration data.
• Cache: Small, fast memory that stores recently used instructions or data.

The memory hierarchy balances speed, capacity, cost, and energy. Registers are fastest and smallest; external nonvolatile storage is usually larger but slower. A cache miss may cause the CPU to wait while data is fetched from a lower level of the hierarchy.

3.2 Address space and memory map

The address space is the set of addresses a processor can generate. In an n-bit address system, the theoretical number of distinct byte addresses is:

This assumes byte-addressable memory and no architectural reservation. For example, a 32-bit address space contains 2³2 addressable byte locations, equal to 4 GiB of address space, although not all addresses need correspond to installed RAM.

An MCU commonly uses memory-mapped I/O. Peripheral registers occupy addresses within the same address space as RAM and flash. Writing to a register may start an ADC conversion, set a GPIO output, or clear an interrupt flag. Such registers are declared volatile in software because their values can change through hardware and must not be optimized away by the compiler.

3.3 Stack, heap, and nonvolatile data

The stack stores function return information, local variables, and saved registers. It grows and shrinks according to program execution. Stack overflow can corrupt memory and cause unpredictable behavior. The heap supports dynamic allocation, but fragmentation and nondeterministic allocation time make it undesirable in many safety-critical or deeply embedded systems.

Firmware images, calibration constants, device identity, and persistent settings require nonvolatile storage. Designers must consider flash erase-block size, write endurance, power loss during updates, and secure boot requirements. A robust system uses versioned data, integrity checks, and an atomic update strategy.

4. Buses and Peripheral Interconnection

A bus provides a shared or point-to-point path for transferring information. Its principal elements are address, data, and control signals. A bus transaction may involve an initiator, such as a CPU or DMA controller, and a target, such as memory or a peripheral.

Common embedded interfaces include:

• AMBA-based internal buses: Widely used within ARM-based SoCs.
• APB: A simple, low-power peripheral bus for registers with modest bandwidth.
• AHB or AXI: Higher-performance buses supporting memory and high-speed peripherals.
• I²C: Two-wire, addressed serial bus supporting multiple devices; useful for sensors and configuration devices.
• SPI: Synchronous serial interface with separate clock, data, and chip-select signals; typically faster than I²C but uses more wires.
• UART: Asynchronous serial communication using transmit and receive lines; common for debugging and point-to-point links.
• CAN: Robust, message-oriented bus widely used in vehicles and industrial systems.
• USB and Ethernet: Higher-level interfaces for host connectivity and networking.

Bus selection depends on bandwidth, distance, number of nodes, wiring, electrical environment, software support, and fault tolerance. Signal integrity becomes important as edge rates and cable lengths increase. Proper grounding, termination, shielding, level translation, and protection against electrostatic discharge are part of interface design.

5. GPIO and Mixed-Signal Peripherals

General-purpose input/output pins connect digital logic to external circuits. A GPIO may be configured as an input, push-pull output, open-drain output, or alternate-function pin. Pull-up and pull-down resistors establish a defined logic state when a switch or open-drain device is inactive.

An input pin must satisfy voltage thresholds and input-current limits. An output pin must not be required to source or sink more current than its data sheet allows. Driving an LED directly requires a current-limiting resistor. For a supply voltage V_S, LED forward voltage V_F, and desired current I_LED, an approximate resistor is:

The formula assumes a simple DC circuit and neglects output-driver resistance. For V_S = 3.3 V, V_F = 2.0 V, and I_LED = 10 mA, R = 130 Ω. A standard 150 Ω resistor would reduce current and provide a practical margin.

Analog-to-digital converters (ADCs) represent an analog voltage using a finite number of codes. For an ideal ADC with resolution N bits and reference voltage V_ref, the approximate voltage represented by one least significant bit is:

This is an ideal quantization step; actual accuracy is affected by noise, reference tolerance, nonlinearity, input impedance, and layout. Anti-alias filtering is required when sampling signals whose frequency content may exceed half the sampling frequency.

6. Timers, PWM, and Real-Time Scheduling

Timers count clock events and provide delays, periodic interrupts, event capture, output comparison, and pulse-width modulation (PWM). If a timer receives a clock frequency f_timer, has prescaler P, and must generate an overflow period T, an approximate required count is:

The result must fit the timer’s counter width. For a 1 MHz timer clock, prescaler 1, and a 1 ms interval, the count is 1000 ticks. Clock tolerance and interrupt latency determine the actual timing accuracy.

PWM controls average power by varying the duty cycle. For an ideal switching signal with high level V_H, low level zero, and duty ratio D between 0 and 1, the average voltage is:

This relationship applies to loads that respond to average power, often with filtering or mechanical inertia. It does not mean that the instantaneous voltage is reduced; the load receives a switching waveform.

7. Interrupts and Direct Memory Access

An interrupt is a hardware-generated request that temporarily transfers CPU execution to an interrupt service routine (ISR). Interrupts allow a processor to respond to external events without continuously polling a status register. Typical sources include timer expiration, received serial data, ADC completion, GPIO transitions, and fault conditions.

A sound ISR should be short, deterministic, and safe. It should acknowledge the source, capture essential data, and defer lengthy processing to a foreground task or operating-system thread. Shared data between an ISR and normal code requires appropriate atomic operations, volatile declarations where appropriate, and synchronization. Priority inversion, nested interrupts, missed flags, and race conditions are common hazards.

Direct memory access (DMA) transfers data between peripherals and memory with limited CPU involvement. DMA is valuable for continuous ADC sampling, audio, networking, and high-speed serial transfers. A DMA design must specify buffer ownership, alignment, transfer size, completion signaling, and cache coherency on processors with data caches. DMA improves CPU availability but does not eliminate memory-bandwidth limits or software synchronization requirements.

8. Watchdogs, Reset, and Reliability

A watchdog timer resets the system if software fails to service it within a permitted interval. It can recover from deadlock, runaway execution, stack corruption, or unexpected peripheral states. A watchdog should not be refreshed unconditionally in an interrupt that continues operating while the main application is stalled. Instead, independent health conditions should be checked before servicing it.

Reliable systems also use brownout detection, power-on reset, clock monitoring, error-correcting or parity protection where available, and safe-state outputs. Reliability is influenced by component quality, temperature, vibration, moisture, electrical transients, software defects, and manufacturing variation. Failure-mode analysis and fault injection are more valuable than assuming that nominal operation is sufficient.

9. Power Supplies and Energy Constraints

An embedded product requires a power tree: battery or external input, protection, regulation, filtering, and separate voltage rails where necessary. Linear regulators are simple and quiet but dissipate excess voltage as heat. For a linear regulator, approximate dissipation is:

where voltages are in volts, current is in amperes, and power is in watts. A switching regulator transfers energy through inductors and capacitors and can achieve higher efficiency, although it introduces switching noise and layout complexity.

If a regulator supplies output power P_out with efficiency η, its input power is approximately:

For a battery-powered system, average energy consumption is determined by operating modes. If a device draws currents I_i for durations t_i during a repeating period T, the average current is:

This assumes approximately constant current in each mode. Battery life in hours is approximately Q_battery / I_avg, where Q_battery is the usable battery capacity in ampere-hours. Temperature, discharge rate, aging, regulator losses, and cutoff voltage make this an estimate rather than a guarantee.

Low-power design includes clock gating, peripheral shutdown, sleep modes, wake-on-interrupt operation, efficient radio protocols, batching of sensor measurements, and reduction of unnecessary transmissions. A radio that transmits briefly at high current may consume less energy than one that remains continuously connected at moderate current.

10. Hardware Selection Framework

Hardware selection should begin with requirements rather than a preferred processor. Important requirements include:

• computational workload and worst-case timing;
• flash, RAM, nonvolatile storage, and peripheral needs;
• analog resolution and sampling rate;
• communication interfaces and protocol security;
• voltage, temperature, mechanical, and environmental conditions;
• energy budget and battery life;
• unit cost, tooling, certification, and supply continuity;
• software ecosystem, development tools, and engineering expertise;
• product lifetime, vendor support, and security-update policy.

A useful selection process first eliminates devices that fail mandatory requirements. Remaining candidates can be scored using weighted criteria. Cost should include the bill of materials, printed circuit board complexity, licensing, development time, certification, manufacturing test, field support, and expected failure costs. A low unit price does not necessarily indicate a low total cost of ownership.

Reliability and security must be considered at the architecture stage. Secure boot, authenticated firmware updates, hardware key storage, debug-port control, unique device identity, and least-privilege software reduce IoT attack exposure. Designers must also consider privacy, responsible vulnerability disclosure, regional radio regulations, electromagnetic compatibility, and applicable product-safety standards.

11. Illustrative Case: Battery-Powered Environmental Sensor

Background

A fictional company plans a wireless sensor that measures temperature, humidity, and air quality in commercial buildings. It must operate for two years from a battery, transmit data every five minutes, cost less than a gateway-class computer, and remain serviceable in a moderately noisy electrical environment.

Problem analysis

The workload is periodic and control-oriented. The device does not require a graphical interface, large databases, or a general-purpose operating system. It does require ADC or digital sensor interfaces, a secure wireless connection, nonvolatile configuration storage, timer wake-up, watchdog recovery, and very low sleep current.

An MPU would provide unnecessary computing capacity and consume more energy. A basic MCU without integrated radio would require an additional radio chip, increasing board area and software integration effort. A low-power wireless SoC with an MCU core is therefore a strong candidate.

Approach and solution

The firmware keeps the processor in deep sleep between measurements. A low-frequency timer wakes the system, powers or enables the sensors, waits for stabilization, acquires readings, performs calibration and plausibility checks, and transmits a compact authenticated packet. DMA moves sensor or radio data into RAM while the CPU performs other work. A watchdog is serviced only after sensor, memory, and communication tasks report healthy status.

Suppose an illustrative operating cycle lasts 300 seconds. The device draws 8 mA for 0.2 s during measurement and transmission and 8 µA for the remaining 299.8 s. The average current is:

Thus, I_avg ≈ 0.0133 mA, or approximately 13.3 µA, before regulator and battery-aging allowances. A practical design would add margin for retransmissions, cold temperature, sensor warm-up, battery self-discharge, and peak-current capability.

Outcome and learning points

The MCU-based wireless SoC meets the functional requirement with lower complexity than an MPU. The case demonstrates that average energy, not only active current, determines battery life; that communication behavior can dominate energy use; and that watchdogs, authenticated updates, and power integrity are essential product features rather than optional additions.

12. Challenges and Contemporary Developments

Embedded designers increasingly use heterogeneous architectures, in which a low-power real-time core works with a high-performance application core or an AI accelerator. Tiny machine-learning models can classify sensor data locally, reducing latency and cloud communication, but introduce model-update, memory, validation, and security challenges.

RISC-V is expanding the range of configurable processor implementations. Chiplet-based integration and advanced packaging may allow specialized computing blocks to be combined, although thermal management, testing, and supply-chain complexity remain concerns. Hardware security modules, confidential computing, and post-quantum cryptographic research are also influencing future IoT platforms.

The central engineering challenge remains balance. More integration can reduce cost and energy, but may increase software complexity and vendor lock-in. More performance can support sophisticated algorithms, but may reduce determinism and battery life. Good design makes these trade-offs explicit and verifies them with measurements, worst-case analysis, prototypes, and environmental testing.

Chapter Summary

Embedded hardware combines computation, memory, timing, communication, sensing, actuation, and power management within strict physical and economic constraints. MCUs are well suited to low-cost, deterministic control; MPUs support complex operating systems and applications; SoCs integrate processor, memory, radio, security, and specialized functions; DSPs, FPGAs, and ASICs serve specialized performance or volume requirements.

CPU performance depends on instruction count, cycles per instruction, and clock period, but memory behavior and real-time determinism are equally important. Memory hierarchy, memory mapping, stacks, nonvolatile storage, and cache behavior directly affect reliability. Buses and interfaces provide structured communication between processing units and peripherals. GPIO, ADCs, timers, PWM, interrupts, DMA, and watchdogs connect software to physical events and improve responsiveness and robustness.

Power supplies must be designed for efficiency, noise control, transient behavior, and safe voltage regulation. Hardware selection should evaluate mandatory technical requirements, total cost, energy, reliability, security, lifecycle support, and regulatory obligations. The best architecture is not the most powerful one; it is the one that satisfies verified system requirements with appropriate margin.

Key Terms

Microcontroller (MCU): An integrated processor, memory, and peripheral controller for dedicated embedded functions.

Microprocessor (MPU): A processor-oriented integrated circuit that commonly requires external memory and peripherals.

System-on-chip (SoC): An integrated circuit containing multiple major computing and peripheral subsystems.

Instruction-set architecture (ISA): The programmer-visible definition of instructions, registers, and memory behavior.

Microarchitecture: The internal implementation used to execute an ISA.

Pipeline: An execution structure that overlaps instruction-processing stages.

Memory map: The assignment of addresses to memory and peripheral registers.

Cache: Fast storage holding recently used instructions or data.

GPIO: A configurable digital input/output connection.

ADC: A circuit that converts an analog signal into a digital representation.

Timer: A counter used for delays, periodic events, capture, comparison, or PWM.

Interrupt: A hardware or software event that requests processor attention.

DMA: Direct memory access that transfers data with limited CPU involvement.

Watchdog timer: A timer that resets the system when software fails to respond correctly.

PWM: Pulse-width modulation used to control average power or represent timing information.

Real-time system: A system whose correctness includes meeting specified timing constraints.

Power tree: The set of input protection, regulation, filtering, and voltage rails in a product.

Secure boot: A mechanism that permits execution only of authenticated firmware.

Review Questions

Short Answer Questions

1. What are the principal differences between an MCU and an MPU?
2. Why is memory-mapped I/O useful in embedded systems?
3. What is the purpose of a watchdog timer?
4. State two advantages of DMA.
5. Why does clock frequency alone not fully determine CPU performance?

Long Answer Questions

1. Explain the memory hierarchy of an embedded processor and discuss the functions of flash, SRAM, cache, stack, and heap.
2. Compare I²C, SPI, UART, and CAN with respect to wiring, addressing, speed, and application suitability.
3. Explain interrupt operation, ISR design principles, priority concerns, and synchronization hazards.
4. Discuss linear and switching regulators and explain how power budgeting affects battery-powered IoT design.
5. Develop a systematic framework for selecting hardware using performance, cost, reliability, security, and lifecycle criteria.

Analytical / Application Questions

1. An MCU executes 12 million instructions with an average CPI of 1.5 at 48 MHz. Calculate the approximate CPU execution time, state the assumptions, and identify two factors that could make the measured time different.
2. Design a timer configuration for a 2 ms periodic event using a 2 MHz timer clock. Discuss counter width, prescaling, clock tolerance, and interrupt latency.
3. Choose between a low-power wireless SoC and an MPU for a battery-powered environmental sensor. Justify the decision using workload, memory, operating system, energy, security, cost, and maintainability.

Multiple Choice Questions with Answers

Question 1

Which platform normally integrates a processor core, memory, timers, and GPIO on one chip for low-power control?

A. Microcontroller

B. Standalone arithmetic unit

C. External hard disk

D. Power transformer

Correct Answer: A. Microcontroller

Question 2

If a processor executes N instructions with average CPI and clock frequency f, which expression gives CPU execution time?

A. N × f × CPI

B. N × CPI ÷ f

C. f ÷ (N × CPI)

D. N ÷ (CPI × f²)

Correct Answer: B. N × CPI ÷ f

Question 3

What is the main purpose of memory-mapped I/O?

A. To replace all RAM with flash

B. To assign peripheral registers addresses in the processor address space

C. To increase battery voltage

D. To eliminate interrupts

Correct Answer: B. To assign peripheral registers addresses in the processor address space

Question 4

Which peripheral is most directly intended for periodic events and pulse-width modulation?

A. Timer

B. UART receiver only

C. Watchdog fuse

D. Flash programmer

Correct Answer: A. Timer

Question 5

What is a principal advantage of DMA?

A. It permanently increases clock frequency

B. It transfers data while reducing repeated CPU copying work

C. It eliminates the need for memory

D. It converts analog signals automatically in every system

Correct Answer: B. It transfers data while reducing repeated CPU copying work

Question 6

For a 3.3 V supply, a 2.0 V LED, and 10 mA desired current, the approximate series resistance is:

A. 13 Ω

B. 130 Ω

C. 330 Ω

D. 530 Ω

Correct Answer: B. 130 Ω

Question 7

Which statement best describes a hard real-time system?

A. It must always use an MPU

B. It must meet specified deadlines for correctness

C. It cannot use interrupts

D. It has unlimited memory

Correct Answer: B. It must meet specified deadlines for correctness

Question 8

What is the principal role of a watchdog timer?

A. To increase ADC resolution

B. To reset or signal a system whose software has failed to respond properly

C. To store firmware permanently

D. To regulate analog voltage

Correct Answer: B. To reset or signal a system whose software has failed to respond properly

Question 9

Which choice generally provides the greatest flexibility for running a feature-rich operating system?

A. MPU with external memory support

B. Single GPIO pin

C. Passive resistor network

D. Basic timer peripheral

Correct Answer: A. MPU with external memory support

Question 10

If a device draws 8 mA for 0.2 s and 0.008 mA for 299.8 s in a 300 s cycle, its approximate average current is:

A. 0.0013 mA

B. 0.0133 mA

C. 0.133 mA

D. 1.33 mA

Correct Answer: B. 0.0133 mA