Sequential Logic Foundations

Introduction and Context

Combinational logic produces outputs determined only by present inputs. A sequential circuit, by contrast, can retain information about its previous condition. Its output therefore depends on both current inputs and an internal state. This capacity for memory is the foundation of registers, counters, finite-state machines, processors, communication interfaces, and digital control systems.

A useful abstract model is:

Here, State(t) is the stored condition at time t, Input(t) is the external input, F is the next-state function, and G is the output function. In a Moore-style machine, output depends only on state; in a Mealy-style machine, output may depend on both state and input. The equations describe idealized behavior; physical circuits also have propagation delay, timing restrictions, power limitations, and possible uncertainty.

Sequential logic is therefore not simply “combinational logic plus memory.” It is a discipline concerned with how information is stored, when it is allowed to change, and how different timing domains interact safely.

Learning Objectives

After studying this chapter, you should be able to:

• explain state, feedback, and the role of a clock;
• distinguish latches from edge-triggered flip-flops;
• use characteristic and excitation tables for common flip-flops;
• compare synchronous and asynchronous control;
• explain setup time, hold time, propagation delay, and metastability;
• analyze clock-domain crossing risks and identify appropriate synchronizing techniques;
• apply these ideas to a practical sequential-system design.

1. State and Feedback

1.1 What is state?

State is the information about a system’s past that is relevant to predicting its future behavior. A single binary storage element has two states, 0 and 1. A group of n independent binary storage elements can represent up to:

possible states, assuming all combinations are permitted. Some systems reserve or prohibit particular combinations, so the number of usable states may be smaller.

For example, a two-bit counter may have states 00, 01, 10, and 11. Its next state is determined by the present state and an enable or reset input. The physical state is stored in latches or flip-flops, while combinational logic computes the next state.

1.2 Feedback

Feedback occurs when a circuit’s output, directly or indirectly, influences its input. In a storage element, feedback allows a previously established logic value to reinforce itself. A simple conceptual memory loop consists of two inverters connected so that each inverter drives the other. In practice, controlled gates are added so that the loop can be written or isolated.

Feedback is powerful but potentially dangerous. Uncontrolled feedback can create oscillation, races, or multiple possible stable conditions. A well-designed sequential circuit controls feedback through an enable signal or clock and satisfies timing constraints.

1.3 Stable and unstable behavior

A stable state is one in which the circuit remains in the same logical condition after internal propagation has completed. An unstable condition causes the circuit to move toward another state, oscillate, or enter an indeterminate analog condition. Digital abstraction treats signals as 0 or 1, but the underlying transistors have continuous voltages and finite response times. This explains why timing analysis is essential.

2. Clocks and Sequential Operation

A clock is a periodic timing signal used to coordinate state changes. Its period is the time between corresponding edges, and its frequency is:

where f_clk is clock frequency in hertz and T_clk is clock period in seconds. This relationship assumes a stable periodic clock.

A rising-edge-triggered circuit responds primarily at a low-to-high transition; a falling-edge-triggered circuit responds at a high-to-low transition. The active transition is called the sampling edge. Between active edges, a properly designed edge-triggered storage element normally holds its state.

Clocked systems divide operation into conceptual phases:

1. Combinational logic uses the current state and inputs to calculate a next-state value.
2. The storage elements sample that value at the active clock edge.
3. The updated state propagates to the outputs and to the next combinational calculation.

This organization makes large digital systems predictable, provided that signal delays and timing requirements are satisfied.

The duty cycle is the fraction of each period for which the clock is at its active level:

Duty cycle matters especially in level-sensitive systems and circuits that use both clock levels. For a simple positive-edge-triggered design, the edge timing is often more important than the exact duty cycle, although clock distribution and minimum pulse-width specifications still apply.

3. Latches and Flip-Flops

3.1 The latch

A latch is level-sensitive. It may be transparent while an enable or gate signal is active and hold its previous value when the enable is inactive. For an active-high D latch, the ideal behavior is:

• when Enable = 1, Q follows D;
• when Enable = 0, Q retains its previous value.

A latch can be useful for time borrowing in high-performance designs, but its transparency creates a window during which changes can pass through. Designers must carefully control the duration and relationship of enable signals.

3.2 The flip-flop

A flip-flop is generally treated as edge-triggered. A D flip-flop samples D at the active edge and retains that sampled value until the next active edge. Conceptually, an edge-triggered flip-flop can be built from two latches arranged as master and slave, with opposite transparency phases.

The distinction is important:

3.3 The D storage element

The D flip-flop is the most common general-purpose storage element. Its characteristic equation is:

This equation states ideal next-state behavior at the active clock edge. It does not mean that Q changes instantaneously; real devices have clock-to-Q delay.

3.4 The SR latch

An SR latch has Set and Reset inputs. In an active-high NOR implementation, Set = 1 drives Q to 1, and Reset = 1 drives Q to 0. The condition Set = Reset = 0 holds the previous state. Set = Reset = 1 is prohibited because it attempts to assert both complementary outputs and may produce an unpredictable result when both controls are released.

Different implementations use active-low inputs, often written S̅ and R̅. The logic interpretation must always be stated; labels alone are not sufficient.

3.5 The JK flip-flop

The JK flip-flop improves on the SR device by defining the condition in which both inputs are active. Its characteristic behavior is:

Its characteristic equation is:

The equation assumes ideal Boolean operation and correctly represents hold, reset, set, and toggle cases. Modern designs more commonly use D flip-flops because their input behavior is simpler and synthesis tools map them efficiently.

3.6 The T flip-flop

A T flip-flop toggles when T = 1 and holds when T = 0:

where ⊕ denotes exclusive OR. T flip-flops are useful in counters and frequency-dividing circuits. If T is permanently 1, the output changes state on every active clock edge and, under ideal conditions, has half the clock frequency.

4. Characteristic and Excitation Tables

A characteristic table describes what next state results from each input and present-state combination. It answers: “Given the present state and inputs, what will the device do?”

An excitation table answers the reverse design question: “Given a desired present-to-next-state transition, what input is required?”

Characteristic tables

The columns are grouped by device type. For the JK table, the complete behavior is more clearly represented by the four-row input table given earlier; the condensed rows above illustrate one selected combination for each present state and should not be interpreted as a full JK characteristic table.

Excitation tables

X means “don’t care”: either 0 or 1 can produce the required transition. Excitation tables are especially useful when implementing a specified state transition using a selected flip-flop type. For a D flip-flop, the required input is simply the desired next state. For a T flip-flop, T is 1 exactly when a transition is needed.

5. Synchronous and Asynchronous Control

5.1 Synchronous control

A synchronous control signal is sampled in relation to a clock edge. A synchronous reset, for example, changes the stored state only at the designated clock edge. Synchronous controls are easier to integrate into timing analysis because state changes occur within the clocked framework.

5.2 Asynchronous control

An asynchronous control can affect a storage element independently of the clock. An asynchronous reset may force Q to 0 immediately, subject to device delay. This is valuable for power-up initialization, emergency shutdown, fault recovery, and safety functions.

However, asynchronous assertion and deassertion have different design implications. Assertion is often deliberately asynchronous so that reset acts quickly. Deassertion should commonly be synchronized to the relevant clock, because releasing reset close to an active edge can violate recovery and removal requirements and leave different flip-flops in different states.

Asynchronous inputs should not be treated as automatically safer merely because they act quickly. They require explicit design rules and verification.

6. Timing Requirements

6.1 Propagation delay

After an input or clock transition, a real circuit requires time before its output becomes valid. For a flip-flop, clock-to-Q delay is the interval between the active clock edge and a valid output transition. Combinational paths also have propagation delay.

6.2 Setup and hold time

Setup time, t_setup, is the minimum interval that data must be stable before the active clock edge. Hold time, t_hold, is the minimum interval that data must remain stable after that edge. Violating either requirement can cause an incorrect result or metastability.

For a simple single-clock path from a launching flip-flop to a receiving flip-flop, a common setup constraint is:

where T_clk is the clock period, t_cq(max) is maximum clock-to-Q delay of the launching element, t_comb(max) is maximum combinational delay, t_setup is receiving-flip-flop setup time, and t_skew represents the relevant clock-skew margin using the adopted sign convention. This expression assumes one active edge per cycle, a common clock, no intentional time borrowing, and nonnegative additional uncertainty represented conservatively.

The corresponding hold condition is commonly expressed as:

Here, minimum delays are used because the concern is data arriving too soon after the receiving edge. The exact skew sign depends on whether the receiving clock arrives earlier or later; professional static-timing tools use a defined convention. Adding arbitrary “safety time” without defining skew and uncertainty can produce an incorrect analysis.

Worked timing example

Suppose a path has t_cq(max) = 0.80 ns, t_comb(max) = 2.40 ns, and t_setup = 0.50 ns. Assume the required clock-skew margin is 0.20 ns.

Therefore, the clock period must be at least 3.90 ns under the stated assumptions. The corresponding maximum ideal frequency is:

This is an ideal timing limit, not a guarantee of system operation. Clock jitter, voltage and temperature variation, routing variation, library characterization, and design margin may require a lower operating frequency.

7. Metastability

Metastability occurs when a storage element is asked to resolve a signal near its sampling boundary, often because setup or hold time is violated or because an asynchronous input changes near a clock edge. The output may temporarily remain between valid logic levels and resolve unpredictably to 0 or 1 after an unbounded physical interval, although the probability of a long resolution time decreases rapidly.

Metastability is not eliminated by Boolean simplification. It is an analog behavior of physical storage elements. Designers reduce its system-level probability by:

• using synchronizer chains for single-bit control signals;
• allowing sufficient resolution time between synchronizer stages;
• avoiding direct use of an asynchronous signal in multiple logic paths;
• using handshake or asynchronous FIFO protocols for data transfer;
• constraining and verifying clock-domain crossings.

A two-flip-flop synchronizer is a common solution for a slowly changing single-bit signal entering a new clock domain. The first flip-flop may become metastable; the second samples it after an additional clock period. This reduces, but never mathematically makes zero, the probability that metastability propagates. A synchronizer must be placed and analyzed appropriately, and it is not a substitute for a protocol when multiple related bits are transferred.

8. Clock-Domain Considerations

A clock domain is the set of sequential logic elements driven by a particular clock, or by clocks treated as timing-related under defined constraints. A signal crossing between unrelated or phase-uncertain domains is asynchronous from the receiving domain’s perspective.

Single-bit crossings

For a level signal, a two-flop synchronizer is often appropriate. For a narrow pulse, direct synchronization may miss the pulse if the destination clock does not sample while it is asserted. Safer techniques include pulse stretching, toggle synchronizers, request-acknowledge handshakes, or event counters.

Multi-bit crossings

Synchronizing each bit independently can produce a word that never existed, because the bits may be captured on different cycles. Multi-bit transfers should use a handshake, a Gray-coded counter where appropriate, or an asynchronous FIFO. An asynchronous FIFO uses separate read and write clocks and carefully synchronized status information.

Clock gating and derived clocks

Improperly gating a clock with ordinary combinational logic can create short pulses and false edges. Dedicated clock-enable inputs or approved clock-gating cells are preferred. A clock divider or derived clock should be treated as a new timing domain unless the design flow explicitly models its relationship to the source clock.

Reset-domain crossing

Reset signals also cross domains. A robust approach is often asynchronous assertion followed by synchronous deassertion separately in each clock domain. Reset sequencing must account for clock availability, power state, and dependencies among subsystems.

9. Designing a Synchronous Counter: An Applied Example

Consider a two-bit synchronous up-counter with an enable input E. When E = 1, the counter advances through 00 → 01 → 10 → 11 → 00. When E = 0, it holds its current state. Let the state bits be Q1 and Q0.

The least significant bit toggles on every enabled count:

The most significant bit toggles when the counter is enabled and Q0 is already 1:

Here × denotes Boolean AND in this context, not arithmetic multiplication of physical quantities. These equations are suitable for a two-bit counter implemented with D flip-flops, because each D input is the desired next-state value.

For example, with current state 01 and E = 1:

At the next active edge, the state becomes 10. With E = 0 and current state 10, D0 = 0 and D1 = 1, so the counter holds 10.

A practical design would also specify reset behavior, maximum clock frequency, output timing, whether unused states exist, and how the counter interacts with other clock domains.

10. Illustrative Case: Sensor Controller with Two Clock Domains

Background

Consider an illustrative embedded controller in which a sensor interface operates at 12 MHz while the main processor operates at 100 MHz. The sensor asserts a data_ready signal when a measurement is available and places the measurement in a register.

Problem

The processor originally sampled data_ready directly. Occasionally it detected a false event, missed an event, or read a mixture of old and new data. These failures were rare in laboratory testing but became more frequent across temperature and voltage changes.

Analysis

The clocks are unrelated, so data_ready is asynchronous to the processor. Direct sampling can violate setup or hold time. Further, synchronizing each data bit independently does not guarantee that all bits represent the same measurement.

Approach and solution

The design was changed to a request-acknowledge handshake. The sensor latches the measurement and toggles a request bit. The request passes through a two-flip-flop synchronizer into the processor domain. When the processor observes a new request, it reads the latched data under the protocol’s stability guarantee and toggles an acknowledge bit. The acknowledge returns through another synchronizer, allowing the sensor to prepare the next measurement.

The data bus is not treated as a collection of unrelated asynchronous bits; its validity is controlled by the handshake. Timing constraints identify the synchronizer registers as intentional clock-domain-crossing elements, while verification checks that the source holds data until acknowledgment.

Outcome

The probability of metastability propagation was greatly reduced, and the protocol prevented the processor from reading a partially updated measurement. The design sacrificed some latency compared with direct sampling, but gained correctness and predictable behavior.

Learning points

1. A rare digital failure may be a timing and analog-interface problem rather than a Boolean-function error.
2. Single-bit synchronization and multi-bit data transfer require different solutions.
3. Protocols should state when data becomes valid, how long it remains stable, and how completion is acknowledged.
4. Clock-domain crossings require architecture, implementation constraints, and verification—not merely additional flip-flops.

11. Design Practices, Limitations, and Contemporary Relevance

Good sequential design begins with an explicit state model and a stated clocking strategy. Use one clear active edge when possible, register critical control signals, define reset behavior, and avoid relying on unspecified power-up values. Use nonblocking assignments for clocked processes in hardware-description languages so that all registers conceptually update together. Separate combinational next-state logic from state registers where this improves readability and verification.

Simulation alone cannot prove absence of metastability because ordinary digital simulation models do not reproduce the full analog resolution process. Static timing analysis, clock-domain-crossing analysis, formal properties, gate-level checks where appropriate, and hardware measurements provide complementary evidence.

Modern systems may contain many clock domains, dynamically scaled frequencies, power-gated regions, and high-speed serial interfaces. Automated tools can identify synchronizer patterns and timing violations, but they cannot replace architectural decisions about data integrity, reset sequencing, or protocol correctness. AI-assisted design tools may help generate or review RTL, yet engineers remain responsible for checking inferred hardware, timing assumptions, security implications, and verification coverage.

Sequential logic also has security relevance. Fault injection, clock manipulation, reset abuse, and metastability-based attacks can target state elements and control paths. Safety-critical and security-sensitive systems should define fail-safe states, monitor clock and reset health, and document assumptions about invalid states and fault recovery.

Chapter Summary

Sequential logic extends combinational logic with state, allowing digital systems to remember past events and coordinate complex operations. Feedback creates storage, while clocks organize when state may change. Latches are level-sensitive; flip-flops are generally edge-triggered. D, SR, JK, and T devices have distinct characteristic behaviors, and excitation tables help determine the inputs required for desired state transitions.

Synchronous controls operate with clocked state updates, whereas asynchronous controls act independently and require special recovery and removal analysis. Setup and hold times constrain data around the sampling edge, and propagation delays determine the maximum usable clock frequency. Violations can lead to metastability, which must be managed rather than assumed away.

Clock-domain crossings are a major practical concern. Single-bit levels may use synchronizers, while pulses, counters, and multi-bit data generally require protocols such as handshakes, toggle schemes, Gray coding, or asynchronous FIFOs. Reliable sequential design combines Boolean reasoning with timing analysis, physical implementation awareness, verification, and disciplined communication between system components.

Key Terms

State: Stored information that influences future circuit behavior.

Feedback: Return of a circuit output to an input path.

Sequential circuit: A circuit whose behavior depends on present inputs and stored state.

Clock: Periodic timing signal used to coordinate state changes.

Latch: Level-sensitive storage element.

Flip-flop: Edge-triggered storage element.

D flip-flop: Storage element whose next state follows the sampled D input.

SR latch: Set-reset storage element with a potentially prohibited input condition.

JK flip-flop: Storage element offering hold, set, reset, and toggle operations.

T flip-flop: Storage element that toggles when T is asserted.

Characteristic table: Table mapping present state and inputs to next state.

Excitation table: Table specifying inputs needed for a desired state transition.

Synchronous control: Control sampled according to a clock.

Asynchronous control: Control that can act independently of the clock.

Setup time: Required data stability interval before a sampling edge.

Hold time: Required data stability interval after a sampling edge.

Metastability: Temporary indeterminate analog condition of a storage element.

Clock domain: Group of sequential elements associated with a timing clock.

Synchronizer: Circuit that reduces the chance of metastability propagation.

Handshake: Coordinated request-and-acknowledge transfer protocol.

Review Questions

Short Answer Questions

1. What distinguishes a sequential circuit from a combinational circuit?
2. Explain the difference between a latch and an edge-triggered flip-flop.
3. What information is provided by an excitation table?
4. Define setup time and hold time.
5. Why is a two-flip-flop synchronizer used for a single-bit clock-domain crossing?

Long Answer Questions

1. Explain how feedback enables binary storage, and discuss why uncontrolled feedback can be problematic.
2. Compare synchronous and asynchronous reset, including their advantages and timing risks.
3. Describe the characteristic and excitation behavior of D, JK, and T flip-flops.
4. Derive the setup-time constraint for a single-clock path and explain each delay term.
5. Explain why synchronizing the individual bits of a multi-bit bus is generally unsafe.

Analytical / Application Questions

1. A path has maximum clock-to-Q delay 1.0 ns, maximum combinational delay 3.2 ns, setup time 0.6 ns, and a 0.2 ns timing margin. Determine the minimum clock period and ideal maximum frequency under the stated assumptions.
2. Design a safe transfer method for a one-cycle pulse generated in a 50 MHz domain and consumed in an unrelated 80 MHz domain. Justify why direct sampling is insufficient.
3. A four-state controller occasionally enters an invalid state after reset release. Analyze how asynchronous deassertion could cause this behavior and propose a reset strategy.

Multiple Choice Questions with Answers

Question 1

Which statement best describes state in a sequential circuit?

A. The current value of only the external input

B. Stored information relevant to future behavior

C. The propagation delay of a logic gate

D. The clock frequency of the system

Correct Answer: B. Stored information relevant to future behavior

Question 2

What is the defining timing characteristic of a latch?

A. It responds only at a rising edge

B. It responds only at a falling edge

C. It is sensitive during an active logic level

D. It never changes after initialization

Correct Answer: C. It is sensitive during an active logic level

Question 3

For a D flip-flop, what is the ideal next-state relationship?

A. Q(t + 1) = D(t)

B. Q(t + 1) = Q̅(t)

C. Q(t + 1) = D̅(t)

D. Q(t + 1) = 0 always

Correct Answer: A. Q(t + 1) = D(t)

Question 4

What does a JK flip-flop do when J = 1 and K = 1?

A. Holds its state

B. Resets to 0

C. Sets to 1

D. Toggles its state

Correct Answer: D. Toggles its state

Question 5

Which table specifies the inputs required to produce a desired state transition?

A. Truth table

B. Excitation table

C. Timing diagram

D. Karnaugh map

Correct Answer: B. Excitation table

Question 6

Why can setup or hold violations be dangerous?

A. They guarantee a transition to logic 1

B. They can cause metastability or incorrect sampling

C. They reduce the number of clock domains

D. They eliminate propagation delay

Correct Answer: B. They can cause metastability or incorrect sampling

Question 7

A path has delays of 0.8 ns, 2.4 ns, and 0.5 ns for clock-to-Q, combinational logic, and setup time, plus a 0.2 ns margin. What is the minimum clock period?

A. 2.9 ns

B. 3.2 ns

C. 3.9 ns

D. 4.8 ns

Correct Answer: C. 3.9 ns

Question 8

What is generally appropriate for transferring a slowly changing single-bit level into an unrelated clock domain?

A. Direct combinational connection

B. Two-flip-flop synchronizer

C. Independent synchronization of every data-bus bit

D. Removal of the receiving clock

Correct Answer: B. Two-flip-flop synchronizer

Question 9

Why is independently synchronizing each bit of a multi-bit bus unsafe?

A. The bus can never contain binary values

B. Different bits may be captured on different cycles

C. Synchronizers work only with analog signals

D. It forces the source clock to stop permanently

Correct Answer: B. Different bits may be captured on different cycles

Question 10

Which reset practice commonly reduces problems during reset release?

A. Asynchronous assertion and synchronized deassertion

B. Synchronous assertion and random deassertion

C. Leaving reset inputs floating

D. Changing reset at every clock edge without analysis

Correct Answer: A. Asynchronous assertion and synchronized deassertion