Registers, Shift Registers, and Counters

Introduction

Digital systems must do more than compute Boolean functions. They must store intermediate results, move data between subsystems, produce timing signals, and follow controlled sequences of states. Registers and counters provide these sequential capabilities. Whereas combinational circuits respond only to present inputs, sequential circuits also depend on stored history. Their memory is normally implemented with flip-flops controlled by a clock.

A register is a group of flip-flops used to store a multi-bit word. A shift register adds controlled movement of bits from one flip-flop to another. A counter is a sequential circuit that advances through a prescribed sequence of binary states. These structures appear in processors, communication interfaces, timers, memory controllers, digital instruments, and embedded systems.

This chapter develops the operation and design of parallel registers, serial and universal shift registers, ripple and synchronous counters, ring and Johnson counters, frequency dividers, and sequence generators.

Learning Objectives

By the end of this chapter, a student should be able to:

• distinguish storage, transfer, shifting, counting, and sequencing functions;
• explain the operation of clocked registers and common shift-register modes;
• design and analyze ripple and synchronous binary counters;
• determine modulus, frequency division, and unused states;
• compare ring, Johnson, and binary counters;
• construct state tables and next-state equations for sequence generators;
• identify timing limitations, startup hazards, and practical implementation issues.

1. Sequential Storage and Register Fundamentals

A flip-flop stores one bit. An n-bit register therefore requires n flip-flops, generally sharing a common clock and reset. If the register contents at time t are represented by Q(t), its next contents are Q(t+1). A parallel-load register transfers all input bits simultaneously:

Here, D(t) is the n-bit input word sampled at the active clock edge. This relationship applies when load is enabled, setup and hold-time requirements are satisfied, and no reset or higher-priority control overrides loading.

A register may have:

• parallel inputs and parallel outputs (PIPO): stores a word and presents all bits together;
• parallel-in, serial-out (PISO): loads a word in parallel and transmits one bit per clock;
• serial-in, parallel-out (SIPO): receives one bit per clock and produces a complete word after n clocks;
• serial-in, serial-out (SISO): delays a serial stream by a selected number of clock periods.

A register with an enable input preserves its old value when disabled. For a D flip-flop register, the next-state relation can be written as:

where E is the enable signal. If E=1, the register loads D; if E=0, feedback preserves Q(t). This equation assumes active-high enable and no separately dominant reset.

Reset may be synchronous, affecting the state only at a clock edge, or asynchronous, affecting the state independently of the clock. Asynchronous reset is useful for rapid initialization, but deassertion must be synchronized in reliable systems to avoid metastability.

2. Shift Registers

A shift register connects flip-flops so that, at each active clock edge, the content of one stage moves to an adjacent stage. Consider a four-stage right-shifting register with stages Q₃, Q₂, Q₁, and Q₀. With serial input S_I and serial output S_O=Q₀, the next-state equations are:

The equations assume a common edge-triggered clock and a right-shift convention. Other texts may number stages in the opposite direction, so the stated convention must always be made explicit.

Serial Transfer Example

Suppose a four-bit register initially contains 0000 and receives the serial sequence 1, 0, 1, 1, with the first bit entering the leftmost stage. After each clock, the contents are:

The sequence appears in parallel as 1101 under this input and stage-order convention. In a communication link, the receiver must use the same bit order and clock interpretation as the transmitter.

Universal Shift Registers

A universal shift register supports four fundamental operations:

1. hold the present word;
2. shift right;
3. shift left;
4. parallel load.

A common implementation places a 4-to-1 multiplexer before each D flip-flop. The multiplexer selects one of four sources according to control inputs S₁,S₀. A representative control table is:

For a four-bit register, the selected source for each stage differs during left and right shifts. Serial inputs must be provided at the two ends. A universal register can therefore convert between serial and parallel data formats and can implement controlled delays.

A crucial design principle is that all stages change on the same clock edge. The circuit must not be built as a chain of level-sensitive storage elements that permits unwanted ripple-through while the clock is active.

3. Counters and Modulus

A counter is a sequential circuit whose state follows a specified progression. A binary up-counter with n flip-flops has up to:

states, where M is the modulus, or number of distinct states in the repeating cycle. The number of flip-flops required for a desired modulus M is:

This determines the minimum number of binary storage elements. If M is not a power of two, some states are unused and additional logic is needed to control or recover from them.

For a binary counter driven by clock frequency f_CLK, the complete counter sequence repeats at:

This equation applies to a signal representing one complete state cycle. Individual output bits may divide the clock by different powers of two in a binary counter.

4. Ripple (Asynchronous) Counters

In a ripple counter, the external clock drives the first flip-flop, and each subsequent flip-flop is clocked by a transition from the preceding stage. With toggle operation, every stage changes state when its clock transition occurs. A four-bit binary ripple counter progresses through 0000, 0001, 0010, and so forth through 1111.

The principal advantage is simplicity: few additional gates are required. Its principal limitation is cumulative propagation delay. If the propagation delay of each stage is t_pd, the worst-case settling delay is approximately:

This is an approximation for equal, independent stage delays and does not include clock distribution, loading, or output buffering. During a transition such as 0111 to 1000, several bits do not change simultaneously. Temporary states such as 0110 or 0100 may appear. These transient states can cause false decoding if combinational logic observes the counter before settling.

Ripple counters are suitable for low-speed frequency division and simple timing tasks. They are less suitable for high-speed address generation or circuits requiring glitch-free decoded outputs.

5. Synchronous Counters

In a synchronous counter, every flip-flop receives the same clock. Combinational logic determines which flip-flops toggle at the active edge. Because clock-to-output changes occur in parallel, synchronous counters are faster and easier to integrate into systems with strict timing requirements.

For a synchronous binary up-counter using T flip-flops, the least significant bit toggles on every clock:

Bit i toggles when all lower-order bits are 1:

for i≥1. Thus, for a four-bit counter:

For T flip-flops, the next state is:

where ⊕ denotes exclusive OR. For JK flip-flops, setting J_i=K_i=T_i produces equivalent toggle behavior. With D flip-flops, the required input is simply D_i=Q_i(t+1).

Worked Design: Modulo-10 Synchronous Counter

A decade counter requires ten states, 0000 through 1001. Four flip-flops are required because 2³=8<10 and 2⁴=16≥10. The desired transition is:

0000 → 0001 → … → 1001 → 0000.

States 1010 through 1111 are unused. A robust design should define their next state, commonly as 0000, so that the counter self-corrects if noise or startup conditions place it in an unused state. The next-state logic can be derived from the state table using excitation tables and Boolean minimization. In practical ICs, dedicated decade-counter logic performs this decoding internally.

A reset-oriented implementation may detect state 1010 and clear the counter. However, asynchronous decoding can generate narrow reset pulses because the state bits do not change at exactly the same time. Synchronous invalid-state recovery is generally easier to analyze and less vulnerable to glitches.

6. Ring and Johnson Counters

A ring counter is a shift register in which the final output is fed back to the first input. With n stages and a one-hot initial state, the sequence contains n states. For a four-stage ring counter:

1000 → 0100 → 0010 → 0001 → 1000.

A ring counter therefore has modulus n, not 2ⁿ. It is easy to decode because exactly one output is high in the intended sequence. Its disadvantages are inefficient state use and the need for initialization. Starting at 0000 produces 0000 forever, so a preset or recovery circuit is essential.

A Johnson counter, also called a twisted-ring counter, feeds the complement of the last stage back to the first. For four stages, one possible sequence is:

0000 → 1000 → 1100 → 1110 → 1111 → 0111 → 0011 → 0001 → 0000.

An n-stage Johnson counter has 2n valid states. It uses more states than a ring counter while retaining simple decoding. The remaining 2ⁿ−2n states are invalid and require consideration during initialization and fault recovery.

7. Frequency Division and Timing

A toggle flip-flop changes state once for each active clock edge. Its output completes one full cycle after two input edges, so it divides frequency by two:

Cascading n ideal binary divide-by-two stages produces division by 2ⁿ. For example, a 12 MHz clock applied to a four-stage binary divider produces a final output of:

The result assumes ideal flip-flops, a stable input clock, and measurement at the final stage. A non-power-of-two divider, such as a decade counter, divides by its modulus. A 10 MHz clock applied to a modulo-10 counter produces 1 MHz at the complete-cycle output.

Frequency division is useful in clock prescalers, baud-rate generation, real-time clocks, event timers, and pulse sequencing. A divided signal should not automatically be treated as a safe clock for every subsystem. In modern synchronous design, it is often preferable to retain one system clock and use a clock-enable pulse, avoiding multiple unrelated clock domains.

8. Sequence Generators and State Design

A sequence generator produces a prescribed repeating pattern of states or output symbols. The design process is:

1. specify the required sequence and output timing;
2. choose a state encoding;
3. draw the state diagram;
4. construct the present-state/next-state table;
5. select flip-flop types;
6. derive and simplify input equations;
7. analyze unused states and reset behavior;
8. verify timing and implement the circuit.

A sequence generator need not count in natural binary order. For example, a controller may cycle through IDLE → LOAD → EXECUTE → STORE → IDLE. The states may be encoded in binary, one-hot form, or another assignment chosen to simplify logic and improve timing.

With D flip-flops, each D input equals the desired next-state bit. With JK or T flip-flops, excitation equations must be obtained from the appropriate excitation table. Outputs may be Moore-type, depending only on the registered state, or Mealy-type, depending on state and external input. Moore outputs are generally easier to make glitch-free; Mealy outputs can respond more quickly but may change when inputs change.

State Assignment and Unused States

Binary encoding uses approximately ⌈log₂ N⌉ flip-flops for N states. One-hot encoding uses N flip-flops but often produces simpler next-state logic and is common in programmable logic devices. A design must specify what happens after reset and what happens if a transient fault enters an unused state. Recovery to a known state is an important reliability practice.

9. Timing, Reliability, and Implementation Constraints

Registers and counters are governed by setup time, hold time, propagation delay, clock skew, and maximum clock frequency. A receiving flip-flop must see stable data for a setup interval before the clock edge and a hold interval after it. If an asynchronous input changes near the edge, the flip-flop may enter metastability. Synchronizer flip-flops reduce, but do not absolutely eliminate, the probability that metastability propagates.

A simplified synchronous timing condition is:

where t_CQ is clock-to-Q delay, t_logic is combinational delay, t_setup is setup time, T_CLK is clock period, t_skew represents clock skew with its sign determined by the timing convention, and t_margin is design margin. All quantities are times, so units must be consistent.

Best practices include using a clean reset strategy, synchronizing external controls, avoiding gated clocks when clock enables are sufficient, defining unused states, checking counter decoding for glitches, and verifying designs with simulation and hardware tests. Hardware description languages allow parameterized registers and counters, but the designer remains responsible for reset semantics, signedness, width, and synthesis behavior.

Applied Case: Conveyor-System Controller

Background

Consider an illustrative packaging conveyor that must move through four phases: WAIT, FILL, SEAL, and EJECT. A programmable controller provides a periodic clock, while sensors indicate that filling and sealing have completed.

Problem

The controller must retain its current phase, advance only when the required sensor is active, and generate one-hot control signals for motors and valves. It must also recover safely if electrical noise produces an invalid state.

Analysis and Solution

A four-state one-hot register is selected. The state vector is Q₃Q₂Q₁Q₀, with one bit representing each phase. A synchronous reset establishes WAIT = 0001. The next-state logic holds the current phase until the relevant sensor is asserted:

• WAIT advances to FILL when a start command is accepted;
• FILL advances to SEAL when the fill sensor is active;
• SEAL advances to EJECT when the seal sensor is active;
• EJECT advances to WAIT after the package leaves the station.

The outputs are Moore outputs: the fill valve is enabled only in FILL, the sealer only in SEAL, and the eject motor only in EJECT. Because outputs depend on registered state, an asynchronous sensor transition cannot directly create an output pulse. Each external sensor is first passed through a synchronizer, and the state machine samples the synchronized signal.

Outcome

The controller has simple decoding, deterministic reset behavior, and explicit recovery logic for all-zero or multiple-one states. A binary encoding would use only two flip-flops, but one-hot encoding makes actuator decoding and verification clearer. The engineering choice depends on available hardware, speed, power, and safety requirements.

Learning Points

The case illustrates that a register stores state, a state machine defines legal transitions, synchronizers protect clock-domain boundaries, and output design affects safety. It also shows why state encoding is a system-level decision rather than merely a flip-flop-count decision.

Contemporary Practice and Professional Relevance

Modern field-programmable gate arrays provide dedicated flip-flops, carry chains, and clock-management resources for efficient counters and registers. Application-specific integrated circuits may use scan-capable registers for manufacturing test. Serial interfaces such as SPI, UART implementations, and many sensor links rely on shift registers for serialization and deserialization.

Designers must distinguish data registers from clocks. Excessive use of derived ripple clocks can create timing-analysis and clock-domain-crossing problems. Synchronous enables, clock-tree resources, formal assertions, and automated synthesis reports are preferred in professional workflows. Verification should test normal sequences, reset during operation, invalid states, boundary transitions, maximum frequency, and asynchronous input behavior.

Chapter Summary

Registers store groups of bits under clock control. Parallel registers load complete words, while shift registers move data serially and support serial/parallel conversion. Universal shift registers combine hold, left shift, right shift, and parallel-load operations.

Counters are sequential state machines. A binary counter has up to 2ⁿ states, while a desired modulus requires at least ⌈log₂ M⌉ flip-flops. Ripple counters are simple but accumulate propagation delay and may produce transient decoded states. Synchronous counters use a common clock and additional logic to improve speed and predictability.

Ring counters circulate a single active bit and have n valid states for n stages. Johnson counters circulate an inverted feedback bit and have 2n valid states. Both require careful initialization and invalid-state handling. Toggle flip-flops and counters provide frequency division, but professional systems should use controlled clocking practices. Sequence-generator design requires state specification, encoding, next-state derivation, output definition, reset design, and verification. Timing constraints, metastability, synchronization, and fault recovery are central to reliable implementation.

Key Terms

Register: A group of flip-flops used to store a multi-bit word.

Shift register: A register that moves stored bits between adjacent stages.

Universal shift register: A register supporting hold, left shift, right shift, and parallel load.

Parallel load: Simultaneous transfer of multiple input bits into a register.

Serial input: Data entering a circuit one bit per clock.

Serial output: Data leaving a circuit one bit per clock.

Counter: A sequential circuit that advances through a defined state sequence.

Modulus: The number of distinct states in a counter’s repeating cycle.

Ripple counter: An asynchronous counter in which stages trigger one another.

Synchronous counter: A counter whose flip-flops share a common clock.

Frequency divider: A circuit that produces an output frequency lower than its input frequency.

Ring counter: A shift-register counter with direct feedback from the final stage.

Johnson counter: A shift-register counter using complemented feedback.

Sequence generator: A sequential circuit that produces a prescribed state or output sequence.

State encoding: Assignment of binary patterns to symbolic states.

Setup time: Required data-stability interval before a clock edge.

Hold time: Required data-stability interval after a clock edge.

Metastability: An uncertain temporary flip-flop condition caused by inadequate timing.

Clock enable: A control that permits state updates without creating a new clock.

Unused state: A binary state not included in the intended operating sequence.

Review Questions

Short Answer Questions

1. What is the principal difference between a combinational circuit and a sequential circuit?
2. List the four basic operations of a universal shift register.
3. Why does a ripple counter exhibit cumulative propagation delay?
4. How many valid states does an n-stage Johnson counter have?
5. What is the purpose of synchronizing an asynchronous input?

Long Answer Questions

1. Explain the operation of SISO, SIPO, PISO, and PIPO registers, including one application of each.
2. Compare ripple and synchronous counters in terms of clocking, speed, hardware complexity, and transient outputs.
3. Describe a complete design procedure for a sequence generator using D flip-flops.
4. Explain ring and Johnson counters and discuss initialization and invalid-state recovery.
5. Discuss setup time, hold time, propagation delay, clock skew, and metastability in a synchronous system.

Analytical / Application Questions

1. Design a modulo-6 synchronous counter. Determine the required number of flip-flops, specify the valid states, and propose a recovery strategy for unused states.
2. A 16 MHz clock drives a binary divider containing five toggle stages. Determine the frequency at the final stage and explain the assumptions used.
3. Design a four-phase controller for a traffic-light or industrial process application. Choose a state encoding, define reset behavior, identify asynchronous inputs, and justify the output strategy.

Multiple Choice Questions with Answers

Question 1

What is the main function of a register?

A. To store a group of binary bits

B. To amplify an analog signal

C. To convert binary to decimal mechanically

D. To eliminate the need for a clock

Correct Answer: A. To store a group of binary bits

Question 2

Which universal shift-register control operation loads all input bits simultaneously?

A. Hold

B. Shift right

C. Shift left

D. Parallel load

Correct Answer: D. Parallel load

Question 3

How many states are available in an ideal 4-bit binary counter?

A. 4

B. 8

C. 16

D. 32

Correct Answer: C. 16

Question 4

What is the principal timing limitation of a ripple counter?

A. It cannot store binary values

B. Propagation delays accumulate through stages

C. All flip-flops require separate data inputs

D. It has no repeating sequence

Correct Answer: B. Propagation delays accumulate through stages

Question 5

In a synchronous binary up-counter, when does bit i greater than zero toggle?

A. Whenever the most significant bit is zero

B. When all lower-order bits are one

C. Only when the external reset is active

D. Only after two complete counter cycles

Correct Answer: B. When all lower-order bits are one

Question 6

How many valid states does a five-stage Johnson counter normally have?

A. 5

B. 10

C. 16

D. 32

Correct Answer: B. 10

Question 7

A 12 MHz clock is divided by a modulo-10 counter. What is the complete-cycle output frequency?

A. 0.12 MHz

B. 1.2 MHz

C. 10 MHz

D. 120 MHz

Correct Answer: B. 1.2 MHz

Question 8

What is a major characteristic of a ring counter?

A. It normally circulates one active bit through its stages

B. It always uses every one of the 2^n binary states

C. It cannot be initialized

D. It requires no flip-flops

Correct Answer: A. It normally circulates one active bit through its stages

Question 9

Which timing condition must data satisfy before the active clock edge?

A. Hold time

B. Setup time

C. Reset recovery only

D. Output-enable time

Correct Answer: B. Setup time

Question 10

Why are asynchronous external inputs commonly passed through synchronizer flip-flops?

A. To increase the number of counter states

B. To convert parallel data into serial data

C. To reduce the risk of metastability propagating into logic

D. To guarantee zero propagation delay

Correct Answer: C. To reduce the risk of metastability propagating into logic