Memory and Programmable Logic

Introduction

Digital systems must do more than calculate values: they must store instructions, data, intermediate results, configuration information, and system state. Memory circuits provide this storage, while programmable logic devices allow designers to implement digital functions without wiring a separate gate for every Boolean expression. Together, memory and programmable logic form the foundation of computers, embedded controllers, communication equipment, and many industrial systems.

This chapter examines the organization and operation of ROM, RAM, and cache memory; address decoding and read/write timing; and the architectural differences among PLAs, PALs, CPLDs, and FPGAs. The emphasis is on selecting an appropriate implementation technology according to capacity, speed, flexibility, power, cost, and development requirements.

Learning Objectives

By the end of this chapter, you should be able to:

• distinguish ROM, SRAM, DRAM, cache, and nonvolatile memory;
• calculate memory capacity from address and data-line counts;
• explain address decoding and chip-selection logic;
• interpret read and write timing diagrams;
• compare PLA, PAL, CPLD, and FPGA architectures;
• explain lookup tables, programmable interconnects, and embedded FPGA resources;
• select a suitable memory or programmable-logic technology for an application.

1. Memory as a Digital System Resource

A memory is an array of storage locations. Each location has a unique address and stores a fixed number of bits called the word width. If a memory has 2ⁿ addressable locations and each word contains m bits, its total capacity is:

Here, n is the number of address lines, m is the number of data bits per location, and C is capacity. The relationship assumes that every address selects one word and that the memory is byte- or word-addressable as specified. Capacity in bytes is obtained by dividing the number of bits by 8.

For example, a memory with 12 address lines and an 8-bit data bus contains 2¹2 = 4096 locations and has capacity 4096 × 8 = 32768 bits, or 4096 bytes (4 KiB). In binary prefixes, 1 KiB equals 1024 bytes.

Important memory signals commonly include:

• Address lines (A): identify the location.
• Data lines (D): carry information into or out of the memory.
• Chip select (CS): enables a particular memory device.
• Output enable (OE): permits stored data to drive the output bus.
• Write enable (WE): commands a write operation.
• Read/write control: indicates the direction of transfer.
• Clock: used by synchronous memories and many modern interfaces.

A memory system can be wider, deeper, or both. Two 8-bit memories operated in parallel can produce a 16-bit word width. Two memories arranged so that one responds to lower addresses and the other to higher addresses increase depth.

2. Read-Only and Nonvolatile Memory

ROM

Read-only memory (ROM) retains its contents when power is removed. In a traditional mask ROM, the manufacturer creates the stored pattern during fabrication. ROM is economical in high-volume products but cannot normally be changed after manufacture.

Programmable ROM (PROM) is supplied blank and programmed once by the user. Erasable programmable ROM (EPROM) can be erased, traditionally using ultraviolet light, and reprogrammed. Electrically erasable programmable ROM (EEPROM) can be erased electrically, often in smaller units such as bytes or pages.

Flash memory is a form of electrically erasable nonvolatile memory that normally erases larger blocks. It offers high density and low cost, making it common in solid-state drives, memory cards, microcontrollers, and firmware storage. Flash has finite program/erase endurance, so controllers use wear leveling, error correction, and bad-block management when appropriate.

ROM organization

A ROM can be viewed as a decoder followed by a programmed connection or output network. The address decoder activates one word line; the programmed pattern determines the data appearing on the output lines. ROM is therefore useful not only for storing constants but also for implementing truth tables, character sets, microprograms, and nonlinear functions.

3. Random-Access Memory

Random-access memory (RAM) permits reading and writing at addresses selected by the user. “Random access” means that access time is approximately independent of the location, not that addresses are selected randomly.

SRAM

Static RAM (SRAM) stores each bit in a bistable latch, commonly implemented using six transistors in an integrated memory cell. It does not require refresh while power is applied. SRAM is fast and has simple timing, but its cell occupies more silicon area than a DRAM cell. It is therefore used for processor caches, buffers, register files, and small high-speed memories.

DRAM

Dynamic RAM (DRAM) stores charge on a capacitor controlled by a transistor. Leakage gradually removes the charge, so every row must be refreshed periodically. DRAM achieves high density and low cost per bit, but refresh, row activation, and precharge introduce more complex timing. Main memory in general-purpose computers is commonly implemented with synchronous DRAM technologies.

Volatile and nonvolatile storage

SRAM and DRAM are volatile: their contents disappear when power is removed. ROM, EEPROM, and flash are nonvolatile. Nonvolatile memory is suitable for firmware and persistent data, whereas volatile memory is normally preferred for frequently changing working data.

4. Cache Memory and the Memory Hierarchy

A processor is often much faster than main memory. Cache memory reduces the average time required to obtain data by keeping recently or frequently used blocks in a small, fast memory close to the processor.

Cache operation relies on two forms of locality:

• Temporal locality: a recently used item is likely to be used again.
• Spatial locality: locations near a recently used item are likely to be used soon.

A cache is organized into lines (or blocks). Each line contains data and metadata, commonly a valid bit and a tag. When the processor supplies an address, the cache examines the relevant index and compares the stored tag with the address tag. A matching valid tag is a hit; otherwise, it is a miss and the required block is obtained from a lower memory level.

For a simple cache, an address is divided into tag, index, and block-offset fields. If the address width is w bits, the cache has 2^s lines, and each line contains 2^b addressable units, then:

This applies to a direct-mapped cache with one line per index. In a set-associative cache, the index identifies a set and the tag is compared with multiple ways.

Average memory access time can be represented as:

Hit time and miss penalty must use the same time units. This simplified expression assumes one cache level and defines miss rate as the fraction of accesses that miss. For multiple levels, the lower-level access time is incorporated recursively.

Worked example: cache fields

Suppose a 32-bit byte address is used with a direct-mapped cache containing 1024 lines, each holding 16 bytes. The index requires log₂(1024) = 10 bits, and the block offset requires log₂(16) = 4 bits. Therefore, the tag contains 32 - 10 - 4 = 18 bits. The cache can rapidly identify the relevant line using the index, then verify identity using the tag.

Cache design involves trade-offs. Larger caches generally reduce capacity misses but may increase hit time, area, and power. Higher associativity reduces conflict misses but requires more tag comparisons and selection logic. Write-through caches send writes immediately to lower memory, whereas write-back caches update lower memory when a modified line is evicted. Write-back reduces traffic but requires a dirty bit and more complex control.

5. Address Decoding and Memory Organization

Address decoding converts binary address information into a chip-select or word-select signal. A full decoder with n inputs can generate up to 2ⁿ mutually exclusive outputs. In a memory chip, internal row and column decoders select the required storage cells.

Memory expansion

To increase word width, connect address and control lines in parallel and divide the data bus among devices. To increase depth, connect address lines shared by all devices but use higher-order address bits to generate separate chip-select signals.

Consider four 1K × 8 memory chips used to create a 4K × 8 memory. The lower 10 address lines, A₀ through A₉, connect to all chips. A₁₀ and A₁₁ feed a 2-to-4 decoder. Each decoder output selects one 1K chip. The data buses are connected in parallel, but only the selected chip is allowed to drive the bus during a read. During a write, only the selected chip receives the write-enable command.

A partial decoder may use only some high-order address bits. It requires less hardware but can produce address aliases: several address ranges select the same physical device. Partial decoding is acceptable when aliases are harmless, but it is unsafe when software expects unique addresses or when unselected devices might respond simultaneously.

Figure: Higher-order address bits select one of four memory chips, while lower-order address and data/control signals are shared.

6. Read and Write Timing

Memory interfaces are defined not only by logic levels but also by when signals change. In an asynchronous read, the address becomes valid, chip select and output enable are asserted, and the memory produces valid data after an access delay. Data must remain valid long enough for the receiving circuit to sample it.

Important timing parameters include:

• Address access time: time from a valid address to valid output data.
• Chip-select access time: time from chip selection to valid data.
• Output-enable time: time from output enable to valid data.
• Setup time: minimum interval that an input must be stable before a sampling edge.
• Hold time: minimum interval that an input must remain stable after a sampling edge.
• Write pulse width: minimum duration of the write command.
• Data setup and hold times: required stability around the write event.

In a synchronous memory, a clock edge defines the transaction. For a write, address and input data must satisfy setup and hold requirements around the active edge. Violating these constraints can cause incorrect or metastable behavior. A designer must use the memory data sheet rather than assume that a nominal clock frequency is sufficient.

A simplified read sequence is: place address on the bus; assert chip select; assert output enable; wait for the specified access time; sample valid data; deassert controls. A write sequence is: place address and data on the buses; assert chip select and write enable; maintain them for the specified pulse and setup/hold intervals; then deassert write enable.

Bus contention occurs when two devices drive different logic values on the same bus. Proper chip-select and output-enable design must ensure that inactive devices are high impedance. Timing analysis must also account for propagation delay through decoders and signal skew between related lines.

7. Programmable Logic Foundations

Programmable logic devices implement combinational or sequential logic using configurable connections. They reduce printed-circuit-board wiring, support rapid modification, and can integrate many gates into one device.

PLA and PAL

A programmable logic array (PLA) has a programmable AND plane followed by a programmable OR plane. Product terms generated by the AND plane can be connected to selected outputs, allowing flexible implementation of sum-of-products expressions.

A programmable array logic (PAL) generally has a programmable AND plane and a fixed OR plane. PALs are less flexible than PLAs but are often faster, smaller, or easier to manufacture because one plane is fixed. Both are especially suitable for relatively small glue-logic, decoding, and control functions.

CPLD

A complex programmable logic device (CPLD) combines multiple logic blocks connected through a programmable interconnect. Each block commonly contains macrocells with product-term logic, flip-flops, and output controls. CPLDs provide predictable timing, nonvolatile configuration in many families, and strong support for control-oriented logic, address decoding, and finite-state machines.

FPGA

A field-programmable gate array (FPGA) consists of configurable logic blocks, programmable routing, input/output blocks, and often embedded memories, clock-management circuits, digital signal-processing units, processors, and high-speed transceivers. FPGAs provide much greater capacity and architectural flexibility than traditional PLDs, although routing delay, configuration storage, power, and design complexity are significant considerations.

8. FPGA Logic, Interconnect, and Embedded Resources

An FPGA lookup table (LUT) implements a truth table stored in a small memory. A k-input LUT can represent any Boolean function of up to k inputs by storing 2^k output bits. A multiplexer tree selects one stored bit according to the input combination. For example, a 4-input LUT stores 16 configuration bits and can implement any single-output function of four variables, subject to the device architecture.

LUTs are usually grouped with flip-flops, carry logic, and multiplexers into slices or adaptive logic modules. Flip-flops provide state storage for counters, pipelines, and finite-state machines. Dedicated carry chains accelerate arithmetic compared with routing a carry through general-purpose LUTs.

Programmable interconnect is the network of wires and switch matrices that connects logic blocks. It determines whether a design can be routed and strongly affects speed and power. Short local routes are generally faster and lower power than long global routes. Clock networks use specialized low-skew resources because ordinary routing can produce unacceptable clock skew.

Embedded block RAM provides denser and more efficient storage than constructing large memories from LUTs. Many devices also include multiplier-accumulator blocks, phase-locked loops, serial interfaces, and processor cores. These resources improve performance and energy efficiency when the design maps naturally onto them, but they may constrain placement and consume scarce device resources.

9. Comparing Implementation Technologies

Technology selection should begin with requirements rather than device preference. Relevant criteria include logic capacity, memory capacity, maximum clock rate, latency, I/O voltage, configuration behavior, power, unit cost, nonrecurring engineering cost, security, development tools, and expected product lifetime.

A small address decoder requiring deterministic power-up behavior may be better implemented in a CPLD than an FPGA. A large image-processing pipeline with parallel arithmetic and embedded memory is a strong FPGA candidate. A fixed high-volume consumer product may justify an ASIC. A constant calibration table may require ROM or flash rather than programmable logic.

10. Illustrative Case: Controller for an Industrial Sensor Node

Background

An illustrative sensor node must collect measurements from several sensors, retain calibration constants, buffer samples, and communicate with a host controller. The design must start reliably after power-up and may require field updates.

Problem

The system needs 16 KB of nonvolatile calibration and firmware storage, a small fast buffer for incoming samples, address decoding for peripherals, and a state machine controlling acquisition. The product is expected to be manufactured in moderate volume, with occasional revisions.

Analysis

Flash is appropriate for firmware and calibration because the information must survive power loss and may be updated. SRAM is suitable for the sample buffer because measurements change frequently and require low-latency access. A small CPLD could implement the peripheral decoder and acquisition state machine with predictable timing. If later versions require filtering, compression, or several high-speed interfaces, an FPGA may provide better scalability.

Approach and solution

The design uses external or embedded flash for nonvolatile contents, SRAM for the volatile buffer, and a CPLD for address decoding, control sequencing, and interface adaptation. High-order address bits generate chip-select signals, while lower-order bits are shared by the selected memory. The CPLD also guarantees that only one peripheral drives the data bus at a time. A watchdog and defined reset state provide safe recovery from faults.

Outcome

This partition separates persistent storage, high-speed temporary storage, and deterministic control logic. It avoids using an FPGA merely for a small control problem, while preserving a migration path to FPGA technology if processing demands grow.

Learning points

The best technology is determined by the complete system requirement. Memory volatility, access timing, update frequency, capacity, and endurance matter as much as Boolean functionality. A technically powerful device can be a poor choice if it adds unnecessary cost, power, configuration risk, or development effort.

11. Limitations, Reliability, and Professional Practice

Memory systems may fail because of timing violations, electrical noise, power interruption, wear-out, radiation-induced bit errors, or software addressing errors. Error-detecting and error-correcting codes are used in systems where data integrity is important. Designers should consider whether a single-bit error can be detected, corrected, or safely ignored.

Nonvolatile memories require attention to endurance, retention, erase granularity, and secure update procedures. Firmware should be authenticated where unauthorized modification could create safety or security risks. Sensitive data should not be stored in unprotected configuration memory. FPGA bitstreams may need encryption and integrity checking, particularly in connected or safety-critical products.

Good practice includes reading the complete data sheet, documenting memory maps, reserving unused address space deliberately, simulating decoder behavior, checking bus contention, performing static timing analysis, and testing power-up and reset conditions. Hardware description languages and synthesis tools improve productivity, but synthesized logic must still be verified against the intended hardware behavior. Simulation, formal checks where appropriate, and laboratory measurements complement one another.

Contemporary systems increasingly combine programmable logic with embedded processors, high-speed serial links, machine-learning accelerators, and adaptive memory controllers. AI workloads often benefit from FPGA parallelism and local memory, but the designer must evaluate bandwidth, numerical precision, resource utilization, and energy per operation rather than assume that reconfigurability alone guarantees efficiency.

Chapter Summary

Memory stores data, instructions, and state using addressable locations. Capacity equals the number of locations multiplied by word width. ROM and flash retain contents without power, while SRAM and DRAM are volatile; SRAM is fast and costly per bit, whereas DRAM is dense but requires refresh. Cache improves average performance by exploiting temporal and spatial locality, using tags, indices, offsets, and replacement policies.

Address decoding selects one memory or peripheral from an address map. Memory depth and word width can be expanded by combining devices, but chip-select logic must prevent aliasing and bus contention. Read and write operations depend on access, setup, hold, pulse-width, and enable timing.

PLAs and PALs provide small-scale programmable logic. CPLDs offer predictable control-oriented logic, while FPGAs provide extensive LUT-based logic, programmable interconnect, flip-flops, embedded RAM, arithmetic blocks, and specialized resources. Technology selection should balance capacity, speed, power, flexibility, cost, reliability, security, and development effort.

Key Terms

Memory: A system that stores binary information for later use.

Address: A binary identifier for a storage location.

Word: The fixed number of bits stored or transferred as one unit.

ROM: Nonvolatile memory normally used for fixed or infrequently changed contents.

RAM: Read/write memory in which locations can be accessed by address.

SRAM: RAM using bistable storage cells without periodic refresh.

DRAM: RAM storing charge that must be periodically refreshed.

Flash memory: Electrically erasable nonvolatile memory commonly erased in blocks.

Cache: Small, fast memory holding recently or frequently used data.

Hit: A cache access in which the required block is present.

Miss: A cache access requiring data from a lower memory level.

Address decoder: Logic that converts address bits into selection signals.

Chip select: A signal enabling one memory or peripheral device.

Setup time: Required input stability before a sampling event.

Hold time: Required input stability after a sampling event.

PLA: Programmable AND and OR planes implementing logic expressions.

PAL: Programmable AND logic with a generally fixed OR structure.

CPLD: Complex programmable logic device containing interconnected logic blocks.

FPGA: Field-programmable gate array containing configurable logic and routing.

LUT: Lookup table that implements a Boolean function by storing truth-table values.

Review Questions

Short Answer Questions

1. What is the difference between volatile and nonvolatile memory?
2. Why does DRAM require refresh?
3. What roles do tag, index, and block offset play in a cache address?
4. What is the purpose of a chip-select signal?
5. How does a PLA differ from a PAL?

Long Answer Questions

1. Explain SRAM and DRAM construction, operation, advantages, and limitations.
2. Describe how four 1K × 8 memory chips can be combined to form a 4K × 8 memory.
3. Explain the sequence and timing requirements of a synchronous memory write.
4. Compare PLA, PAL, CPLD, and FPGA architectures and applications.
5. Explain how FPGA LUTs, flip-flops, routing, block RAM, and carry chains cooperate to implement a digital system.

Analytical / Application Questions

1. A system requires a 16-bit memory with 8192 addressable locations. Determine the number of address lines and total capacity in bits and bytes.
2. A direct-mapped cache uses 32-bit byte addresses, 256 lines, and 32-byte blocks. Determine the index, offset, and tag widths.
3. Recommend ROM/flash, SRAM, DRAM, CPLD, or FPGA technologies for a fixed lookup table, a high-speed sample buffer, a large operating memory, a small deterministic peripheral controller, and a parallel image-processing engine. Justify each choice.

Multiple Choice Questions with Answers

Question 1

A memory has 14 address lines and an 8-bit data width. What is its capacity?

A. 8 KiB

B. 16 KiB

C. 32 KiB

D. 64 KiB

Correct Answer: B. 16 KiB

Question 2

Which memory normally requires periodic refresh?

A. SRAM

B. Mask ROM

C. DRAM

D. PROM

Correct Answer: C. DRAM

Question 3

Which cache field identifies the location within a cache block?

A. Tag

B. Index

C. Block offset

D. Valid bit

Correct Answer: C. Block offset

Question 4

What is the principal purpose of an address decoder in a memory system?

A. Amplify the clock

B. Select a location or device from address bits

C. Convert analog signals to digital signals

D. Refresh SRAM cells

Correct Answer: B. Select a location or device from address bits

Question 5

In a synchronous memory write, data must normally satisfy which requirements around the active clock edge?

A. Only output-enable timing

B. Setup and hold timing

C. Only refresh timing

D. Only tag-comparison timing

Correct Answer: B. Setup and hold timing

Question 6

Which device has both programmable AND and programmable OR planes?

A. PLA

B. PAL

C. CPLD only

D. DRAM

Correct Answer: A. PLA

Question 7

A 4-input FPGA LUT can represent how many possible input combinations?

A. 4

B. 8

C. 16

D. 32

Correct Answer: C. 16

Question 8

Which technology is generally most appropriate for a large parallel image-processing pipeline with embedded memory?

A. A fuse PROM only

B. An FPGA

C. A small PAL

D. A single SRAM cell

Correct Answer: B. An FPGA

Question 9

What is a common advantage of a CPLD over a large FPGA for control logic?

A. It always contains more arithmetic units

B. It provides predictable control-oriented timing and simpler implementation

C. It requires DRAM refresh for configuration

D. It cannot implement sequential logic

Correct Answer: B. It provides predictable control-oriented timing and simpler implementation

Question 10

If a cache has a hit time of 2 ns, a miss rate of 5%, and a miss penalty of 40 ns, what is the simplified average memory access time?

A. 2 ns

B. 2.5 ns

C. 4 ns

D. 42 ns

Correct Answer: B. 2.5 ns