Digital Electronics, Timing, and Logic Families

Introduction

Digital systems represent information using discrete signal levels, usually interpreted as logic 0 and logic 1. Although Boolean algebra treats these values as perfectly distinct, physical circuits operate with voltages, currents, capacitances, resistance, temperature variation, manufacturing tolerances, and electromagnetic interference. Reliable digital design therefore requires more than writing truth tables: a designer must understand voltage specifications, noise immunity, loading, timing, power, and the electrical compatibility of interconnected devices.

This chapter focuses primarily on CMOS logic, the dominant logic technology in modern processors, memories, embedded systems, and programmable devices. It also compares CMOS with other logic families and examines tri-state interfaces, propagation delay, hazards, glitches, and practical interfacing constraints.

Learning Objectives

By the end of this chapter, you should be able to:

• interpret logic-family voltage and current specifications;
• calculate high and low noise margins;
• explain fan-in, fan-out, loading, and propagation delay;
• estimate dynamic and static power consumption;
• interpret timing diagrams and identify setup, hold, and propagation requirements;
• explain hazards and glitches and select suitable remedies;
• describe tri-state operation and shared-bus constraints;
• evaluate whether two digital devices can be safely interconnected;
• compare CMOS, TTL, open-drain, and related interface technologies.

1. From Boolean Values to Physical Signals

A Boolean variable has two values, but a digital input does not detect an abstract value. It detects a voltage relative to a reference, commonly ground. A device data sheet specifies ranges within which an input is guaranteed to be interpreted as LOW or HIGH.

For a supply voltage V_DD, typical specifications are:

• V_IL(max): maximum input voltage guaranteed to be LOW;
• V_IH(min): minimum input voltage guaranteed to be HIGH;
• V_OL(max): maximum output voltage when driving LOW;
• V_OH(min): minimum output voltage when driving HIGH.

The interval between V_IL(max) and V_IH(min) is not a valid guaranteed operating region. A slowly changing or noisy input in this interval may produce an unpredictable logical result and can increase short-circuit current in CMOS input stages.

An output must satisfy the receiving input’s requirements. For a LOW signal, the driver must produce a voltage no greater than the receiver’s V_IL(max), and for a HIGH signal it must produce a voltage no lower than the receiver’s V_IH(min). Logic compatibility must therefore be checked from data-sheet limits, not from nominal supply voltages alone.

Noise Margins

Noise margin is the voltage disturbance that can be tolerated while preserving a guaranteed logic interpretation. The worst-case DC noise margins are:

Here NM_L and NM_H are low- and high-level noise margins, respectively, measured in volts. These expressions assume that the output and input specifications refer to the same supply conditions and that the signal is within the specified current-loading limits.

For example, suppose a device specifies V_OL(max) = 0.4V, V_IL(max) = 0.8V, V_OH(min) = 4.4V, and V_IH(min) = 3.5V. Then:

NM_L = 0.8 - 0.4 = 0.4V

and

NM_H = 4.4 - 3.5 = 0.9V.

These are guaranteed worst-case margins, not necessarily the actual noise immunity of every manufactured circuit.

2. CMOS Logic Behavior

CMOS, or complementary metal–oxide–semiconductor, uses paired p-channel and n-channel MOSFETs. In a static CMOS inverter, the p-channel transistor connects the output to the positive supply when the input is LOW, while the n-channel transistor connects the output to ground when the input is HIGH. Ideally, one transistor is OFF when the other is ON.

This complementary arrangement gives CMOS three important characteristics:

1. High voltage gain: the transition region can sharply distinguish LOW from HIGH.
2. Very low static power in steady state: ideally, no direct DC path exists from supply to ground.
3. High input impedance: a MOS gate draws very little steady-state input current.

Real CMOS circuits are not ideal. Leakage currents flow through transistor junctions, protection structures, and subthreshold conduction. During a transition, both transistors may conduct briefly, creating short-circuit current. The output must also charge or discharge capacitance, consuming dynamic energy.

The CMOS inverter’s voltage-transfer characteristic contains a LOW-output region, a transition region, and a HIGH-output region. The transition point depends on transistor dimensions, threshold voltages, supply voltage, temperature, and process variation. Consequently, a design must use guaranteed data-sheet limits rather than assuming an exact switching threshold.

CMOS Inputs and Unused Pins

A floating CMOS input is dangerous. Because its input impedance is high, a floating pin can acquire charge from interference and switch unpredictably. Unused inputs should be tied to a defined logic level, directly where appropriate or through a resistor when configuration flexibility is needed. Outputs must never be tied together unless the technology explicitly supports it, such as open-drain or properly controlled tri-state outputs.

3. Fan-In, Fan-Out, and Loading

Fan-In

Fan-in is the number of inputs on a logic gate. Increasing fan-in generally increases transistor count, input capacitance, internal resistance, and propagation delay. A large CMOS NAND gate, for example, may contain several series-connected n-channel transistors. The series path becomes electrically weaker, especially for a transition requiring all transistors to conduct.

Large logical functions are often implemented as several smaller gates rather than one very high-fan-in gate. This can reduce delay, improve layout, and make timing behavior more predictable, although additional stages also introduce delay.

Fan-Out

Fan-out is the number of standard logic inputs that one output can drive while meeting voltage and timing specifications. In older logic families, fan-out is often limited by output current. In CMOS, DC input current is usually very small, so capacitive loading and transition speed are frequently more important.

For a conservative DC current calculation, if an output must supply HIGH-level current to each load, the maximum number of loads is bounded by:

For LOW-level sinking:

The floor symbol means that only a whole number of loads is permitted. The currents must be expressed in the same units, and the calculation applies only to the specified static current conditions. The practical fan-out is the smaller of the two values and may be further reduced by capacitive timing requirements.

Capacitive Loading

Every input, trace, connector, and package contributes capacitance. A simplified RC model estimates the time required for a signal to change:

Here R_eq is the driver’s effective output resistance in ohms, C_L is total load capacitance in farads, and t_10-90 is the approximate 10%–90% transition time in seconds. This is a first-order approximation for a single-pole RC response; actual CMOS waveforms may differ.

Large capacitance causes slower edges, greater short-circuit current in receiving gates, increased susceptibility to noise during transitions, and timing failure. A buffer may be inserted to drive a large load. Buffer chains are commonly sized progressively so that no single stage experiences an extreme capacitance ratio.

4. Propagation Delay and Timing

Propagation delay is the time between a defined change at a circuit input and the corresponding change at its output. Because rising and falling behavior is often different, data sheets specify t_PLH for LOW-to-HIGH output transitions and t_PHL for HIGH-to-LOW transitions. Delay is measured between specified voltage thresholds, commonly 50% of the supply voltage.

For a logic path containing several stages, a first approximation is:

where t_pd,i is the propagation delay of stage i and t_wire is interconnect delay. This sum assumes that the stages operate sequentially and that their delays are characterized under compatible conditions.

The maximum clock frequency of a synchronous system is constrained by the clock-to-Q delay of the launching flip-flop, combinational delay, setup time of the receiving flip-flop, and clock uncertainty. A simplified constraint is:

T_clk is the clock period; t_cq(max) is maximum clock-to-Q delay; t_comb(max) is maximum combinational delay; t_setup is receiving setup time; and t_skew and t_jitter represent clock uncertainty terms. A positive skew convention is assumed in this conservative expression. The corresponding frequency is f_max \le 1/T_clk. Hold-time constraints are separate and concern the earliest data arrival after the active clock edge.

Timing Diagrams

A timing diagram shows signal values against time. Important features include:

• edge direction: rising or falling;
• pulse width and period;
• propagation delay between related transitions;
• setup interval before a clock edge;
• hold interval after a clock edge;
• uncertain or invalid regions;
• glitches or pulses that are shorter than the system’s intended sampling interval.

A signal may be logically correct at steady state but still fail because it changes too late, violates setup or hold time, or produces a transient pulse that activates downstream logic.

5. Power Consumption

CMOS power has several components. Dynamic switching power is commonly approximated by:

where \alpha is the activity factor, C_L is switched capacitance, V_DD is supply voltage, and f is switching frequency. The activity factor depends on the definition of a switching event; it must be used consistently with the capacitance and frequency model.

The energy associated with charging a capacitor from 0 to V_DD is:

In a conventional CMOS charge-and-discharge cycle, approximately C_LV_DD² is drawn from the supply over a complete 0-to-1-to-0 cycle, because the stored energy is dissipated during discharge and an equal amount is supplied during charging. The exact average power depends on the assumed transition rate and activity definition.

Static power is approximated by:

where I_leak is total leakage current. Short-circuit power occurs briefly when both pull-up and pull-down networks conduct during an input transition. In modern low-voltage systems, leakage power can be significant, especially at high temperature.

Worked example. A node has C_L = 20pF, V_DD = 3.3V, switches with activity factor \alpha = 0.25, and has f = 10MHz. Then:

P_dyn = 0.25 × 20×10^-12 × 3.3² × 10×10⁶ ≈ 0.5445mW.

This estimate excludes leakage, short-circuit power, and power consumed elsewhere in the driver.

Reducing voltage is especially effective because dynamic power varies with the square of voltage. Reducing capacitance and unnecessary switching also improves power and often improves timing.

6. Logic Families and Interfacing

A logic family is a group of circuits with compatible electrical characteristics and a common implementation approach. Important families include CMOS, TTL, BiCMOS, ECL, open-drain/open-collector interfaces, and differential standards such as LVDS.

A 5 V CMOS output cannot automatically be connected to a 3.3 V input. The receiving device may not tolerate 5 V, even if its input recognizes a HIGH above 2 V. Conversely, a 3.3 V output may not meet the HIGH-input requirement of an older 5 V TTL or CMOS device. Designers may use level translators, open-drain circuits, series resistors, or specially specified 5 V-tolerant inputs.

Open-Drain Interfaces

An open-drain output can pull a line LOW but cannot actively drive it HIGH. An external pull-up resistor supplies the HIGH level. Multiple open-drain outputs may share a line safely if no device drives HIGH actively; the logical operation is wired-AND in positive logic. The pull-up resistor and bus capacitance determine the rising time. A smaller resistor produces a faster rise but increases LOW-level current:

This approximation assumes the output transistor is strongly ON and neglects its voltage drop. The resistor must satisfy both rise-time and current limits.

Tri-State Interfaces

A tri-state output has three states: logic LOW, logic HIGH, and high impedance, commonly written Z. In the Z state, the output is electrically disconnected enough that another authorized device can drive the line. A shared bus requires mutually exclusive output enables.

Tri-state control is not itself a logical value transmitted on the bus. It is an output-control condition. If two enabled outputs drive opposite values, the result is bus contention, potentially causing excessive current, voltage collapse, incorrect data, and permanent damage. Disable timing must include sufficient dead time when changing bus ownership.

7. Glitches and Hazards

A glitch is an unintended transient pulse. A hazard is a circuit condition in which unequal propagation delays can produce such a transient. Hazards are not necessarily errors in Boolean algebra; they arise because real gates do not change simultaneously.

A static-1 hazard occurs when the output should remain 1 but briefly falls to 0. Consider:

If B = 1 and C = 1, changing A should leave F = 1. However, the path through the inverter and the two product terms may have different delays. Both product terms can momentarily be 0, creating a LOW pulse. Adding the consensus term gives:

When B = C = 1, the term BC maintains the output during the transition. This Boolean redundancy does not change the steady-state function but improves asynchronous timing behavior.

A static-0 hazard can occur when an output intended to remain 0 briefly rises to 1. A dynamic hazard involves multiple unintended transitions, often in multilevel logic. Hazards are especially important in asynchronous circuits, clock generation, resets, interrupts, and control signals. In fully synchronous data paths, a glitch may be harmless if it settles before the receiving clock edge, but it remains a design risk if it reaches a clock, asynchronous reset, or sensitive enable.

Hazard reduction methods include adding consensus terms, balancing path delays, registering control signals, using synchronous design practices, filtering very narrow pulses where appropriate, and applying static timing analysis. A registered signal is not automatically safe: clock-domain crossings require synchronizers or other dedicated techniques.

8. A Practical Interface-Analysis Method

When connecting two digital devices, use the following procedure:

1. Identify both supply voltages and signal direction.
2. Compare driver V_OH(min) with receiver V_IH(min).
3. Compare driver V_OL(max) with receiver V_IL(max).
4. Check driver source and sink currents against receiver input currents.
5. Estimate total capacitance and verify rise/fall-time requirements.
6. Check absolute maximum input voltage and 5 V-tolerance claims.
7. Verify propagation delay, setup, hold, pulse-width, and clock requirements.
8. Determine reset, power-up, and power-down behavior.
9. For shared lines, verify enable sequencing and contention protection.
10. Consider ESD, ground bounce, crosstalk, termination, and connector effects.

Nominal voltage compatibility is only one part of the analysis. A connection can have valid DC logic levels but fail dynamically because the edge is too slow or the timing margin is too small.

9. Applied Case: Shared Sensor Bus in an Embedded Controller

This is an illustrative case. An embedded controller at 3.3 V communicates with three sensors over a shared two-wire open-drain bus. Each sensor can pull either line LOW, while a pull-up resistor returns the line HIGH. The bus capacitance is estimated as 200 pF, and the designer initially selects a 10 kΩ pull-up resistor.

Problem

The controller must operate at a bus speed requiring a maximum rising-time allowance of 1 μs. The designer must determine whether the pull-up is adequate and whether LOW-level current is acceptable.

Analysis

Using the first-order 10%–90% RC approximation:

where R_P = 10kΩ and C_B = 200pF. Thus:

t_10-90 ≈ 2.2 × 10,000 × 200×10^-12 = 4.4μs.

The estimated rise time exceeds the 1 μs allowance. The bus is too slow. When a device pulls LOW, the approximate pull-up current is:

I_LOW ≈ 3.3V / 10kΩ = 0.33mA.

This current is modest, but the resistor is too large for the timing requirement.

Approach and Solution

Ignoring device-specific limits temporarily, the maximum resistance suggested by the rise-time requirement is:

Therefore:

R_P \le 1μs /(2.2 × 200pF) ≈ 2.27kΩ.

A standard value such as 2.2 kΩ gives an estimated rise time of approximately 0.968 μs and LOW current of approximately 3.3V/2.2kΩ = 1.5mA. The designer must then verify that every sensor can sink this current while meeting its specified V_OL(max), and must include pin capacitance, trace capacitance, pull-up tolerance, temperature, and logic-high timing specifications. If current is excessive, an active pull-up or a lower-capacitance layout may be preferable.

Outcome and Learning Points

The original interface was logically plausible but failed its timing requirement. The revised design meets the first-order rise-time target with increased LOW current. The case demonstrates that open-drain compatibility requires simultaneous consideration of resistor value, capacitance, current, voltage limits, and data-sheet timing—not merely a shared logical protocol.

10. Design Best Practices and Limitations

Good digital design uses worst-case specifications, not typical values. It avoids floating inputs, minimizes unnecessary switching, separates noisy power paths from sensitive signals, uses decoupling capacitors close to integrated-circuit supply pins, and controls edge rates when interconnects are long. Ground reference quality is essential: a nominal 0 V signal can shift because of ground bounce or common-impedance coupling.

Equations in this chapter are engineering approximations. RC models omit nonlinear transistor behavior, package inductance, transmission-line effects, simultaneous switching noise, and measurement bandwidth. For high-speed designs, traces may need transmission-line analysis, controlled impedance, termination, differential signaling, and electromagnetic-compatibility testing. For safety-critical or medical systems, verification must follow applicable standards and documented design controls.

Modern systems also use adaptive voltage scaling, power gating, clock gating, multi-threshold CMOS, on-chip termination, programmable I/O standards, and formal or static timing analysis. These technologies improve energy efficiency and performance but increase configuration complexity. Artificial intelligence does not replace electrical verification: automated design tools can optimize or check a design only when constraints, libraries, models, and assumptions are correct.

Chapter Summary

Digital logic is implemented with physical voltages and currents rather than ideal Boolean symbols. CMOS provides high input impedance and low steady-state power, but leakage, capacitive loading, transition current, and supply variation remain important. Input and output voltage limits determine compatibility, while low- and high-level noise margins quantify guaranteed immunity.

Fan-in affects internal complexity and delay; fan-out is limited by current and capacitance. Propagation delay accumulates through logic paths and constrains clock frequency together with setup, hold, clock-to-Q, skew, and jitter. Dynamic CMOS power depends on activity, capacitance, the square of supply voltage, and frequency; leakage and short-circuit power must also be considered.

Open-drain outputs support shared wired signaling but require pull-ups. Tri-state outputs support buses but demand exclusive enable control. Glitches and hazards result from unequal path delays and can be reduced through consensus terms, registered control, careful timing analysis, and synchronous design. Reliable interfacing requires checking voltage, current, capacitance, timing, absolute maximum ratings, power sequencing, and signal integrity.

Key Terms

Logic family: A technology group with compatible electrical and logical characteristics.

CMOS: Complementary metal–oxide–semiconductor logic using paired p-channel and n-channel MOSFETs.

V_IL(max): Maximum input voltage guaranteed to be interpreted as LOW.

V_IH(min): Minimum input voltage guaranteed to be interpreted as HIGH.

Noise margin: Guaranteed voltage tolerance between driver output limits and receiver input limits.

Fan-in: Number of inputs connected to a logic gate.

Fan-out: Number of standard inputs that one output can drive within specifications.

Capacitive loading: Electrical capacitance presented by inputs, interconnects, and packages.

Propagation delay: Time between an input transition and the corresponding output transition.

Setup time: Minimum interval that data must be stable before a sampling clock edge.

Hold time: Minimum interval that data must remain stable after a sampling clock edge.

Dynamic power: Switching-related power, commonly approximated by \alpha C_LV_DD²f.

Leakage power: Power caused by nonideal steady-state currents.

Open-drain: Output structure that actively pulls LOW but requires an external pull-up for HIGH.

Tri-state: Output capable of LOW, HIGH, and high-impedance states.

Bus contention: Conflict caused by multiple active outputs driving incompatible values.

Glitch: Unintended transient pulse.

Hazard: Circuit condition capable of producing a glitch because of unequal delays.

Consensus term: Redundant Boolean term used to eliminate certain static hazards.

Level translator: Circuit that converts signals between incompatible voltage domains.

Review Questions

Short Answer Questions

1. What do V_IL(max) and V_IH(min) specify?
2. Why should a CMOS input not be left floating?
3. Define fan-in and fan-out.
4. What are the three output states of a tri-state driver?
5. Why does capacitive loading increase propagation delay?

Long Answer Questions

1. Explain CMOS inverter operation and discuss its static, dynamic, and short-circuit power components.
2. Derive and interpret the low- and high-level noise-margin equations.
3. Explain how setup time, hold time, clock-to-Q delay, and combinational delay constrain synchronous operation.
4. Compare ordinary CMOS, TTL, open-drain, and tri-state interfaces.
5. Explain static-1, static-0, and dynamic hazards, including methods for hazard reduction.

Analytical / Application Questions

1. A driver has V_OH(min) = 2.9V and V_OL(max) = 0.4V. A receiver requires V_IH(min) = 2.0V and V_IL(max) = 0.8V. Calculate both noise margins and assess compatibility.
2. A synchronous path has t_cq(max) = 0.8ns, t_comb(max) = 4.5ns, t_setup = 0.7ns, and 0.5 ns total clock uncertainty. Determine the minimum clock period using the simplified constraint and the corresponding upper-bound frequency.
3. A shared open-drain line has C_B = 150pF and a 4.7 kΩ pull-up. Estimate its 10%–90% rise time and explain two practical factors that could make the actual value different.

Multiple Choice Questions with Answers

Question 1

Which expression correctly defines the HIGH-level noise margin?

A. V_IL(max) - V_OL(max)

B. V_OH(min) - V_IH(min)

C. V_IH(min) - V_OH(min)

D. V_OL(max) - V_IL(max)

Correct Answer: B. V_OH(min) - V_IH(min)

Question 2

A CMOS input left floating is most likely to:

A. Remain permanently HIGH

B. Remain permanently LOW

C. Switch unpredictably because it can acquire charge and noise

D. Increase the supply voltage

Correct Answer: C. Switch unpredictably because it can acquire charge and noise

Question 3

What primarily limits CMOS fan-out in many practical applications?

A. Only the Boolean truth table

B. Capacitive loading and required transition speed

C. The number of power pins

D. The gate symbol used in a schematic

Correct Answer: B. Capacitive loading and required transition speed

Question 4

For C_L = 10pF, V_DD=2V, f=5MHz, and \alpha=0.5, what is the approximate dynamic power?

A. 0.01 mW

B. 0.1 mW

C. 1 mW

D. 10 mW

Correct Answer: B. 0.1 mW

Question 5

Which state allows a tri-state output to release a shared bus?

A. LOW

B. HIGH

C. High impedance

D. Metastable

Correct Answer: C. High impedance

Question 6

An open-drain output drives a HIGH level by:

A. Using an internal p-channel transistor

B. Using an external pull-up resistor

C. Shorting the output to ground

D. Disabling the receiving input

Correct Answer: B. Using an external pull-up resistor

Question 7

A static-1 hazard causes an output that should remain 1 to:

A. Briefly fall to 0

B. Remain permanently 1

C. Oscillate indefinitely by definition

D. Become high impedance

Correct Answer: A. Briefly fall to 0

Question 8

If R_eq=1kΩ and C_L=10pF, the first-order 10%–90% transition time is approximately:

A. 2.2 ps

B. 22 ps

C. 2.2 ns

D. 22 ns

Correct Answer: C. 2.2 ns

Question 9

Which condition creates tri-state bus contention?

A. All outputs are disabled

B. Only one output is enabled

C. Two enabled outputs drive opposite logic values

D. A pull-up resistor is present

Correct Answer: C. Two enabled outputs drive opposite logic values

Question 10

The simplified synchronous timing constraint includes which set of terms?

A. Only supply voltage and leakage current

B. Clock-to-Q, combinational delay, setup time, and clock uncertainty

C. Only fan-in and fan-out

D. Only input and output noise margins

Correct Answer: B. Clock-to-Q, combinational delay, setup time, and clock uncertainty