Computer Architecture and Hardware

Introduction

Computing systems are physical machines as well as software environments. Every program executed by a robot, industrial controller, simulation workstation, or embedded product ultimately depends on electronic circuits that store data, perform operations, transfer information, and communicate with the external world. Computer architecture describes the programmer-visible organization of these components, while computer organization describes how that architecture is implemented in hardware.

For mechatronics engineers, hardware knowledge is essential because mechanical, electrical, and computational subsystems must operate as one system. A control algorithm is useful only if the processor can execute it quickly enough, memory can supply data reliably, sensors can be sampled at the required rate, and actuators can be driven safely. Hardware selection therefore involves more than choosing the processor with the highest advertised clock frequency.

This chapter introduces the processor, memory hierarchy, buses, storage, input/output, peripherals, instruction execution, performance measurement, microcontrollers, and principles for selecting hardware for engineering tasks.

Learning Objectives

After studying this chapter, a student should be able to:

1. Explain the functional organization of a computer system.
2. Describe how a processor fetches, decodes, and executes instructions.
3. Distinguish registers, cache, main memory, secondary storage, and non-volatile memory.
4. Explain the roles of buses, interfaces, controllers, and peripherals.
5. Use basic performance measures such as latency, bandwidth, throughput, and execution time.
6. Compare microcontrollers with general-purpose microprocessors and embedded computers.
7. Select hardware systematically for a mechatronics application.
8. Identify reliability, safety, security, energy, and lifecycle considerations in hardware design.

1. Functional Organization of a Computer

A computer system can be viewed as five cooperating functions:

• Processing: arithmetic, logical, control, and data-transformation operations.
• Memory: temporary or permanent storage of instructions and data.
• Input: acquisition of information from users, sensors, networks, or other systems.
• Output: delivery of information to displays, actuators, networks, or storage devices.
• Interconnection: communication among processing, memory, and input/output units.

The classical stored-program concept places instructions and data in memory. The processor reads instructions from memory, interprets them, and performs the specified operations. In a modern system, this simple model is extended by caches, pipelines, multiple cores, direct-memory access, specialized accelerators, and complex peripheral controllers.

A useful distinction is between architecture and organization. The instruction set architecture (ISA) specifies instructions, registers, data types, addressing methods, and the programmer-visible behavior of a processor. Examples include ARM, RISC-V, and x86 families. Organization concerns implementation details such as pipeline depth, cache capacity, branch prediction, and internal interconnections. Two processors may implement the same ISA while having very different performance and power consumption.

2. The Processor

The central processing unit (CPU) consists primarily of an arithmetic and logic unit, a control unit, registers, and internal data paths.

2.1 Arithmetic and Logic Unit

The arithmetic and logic unit (ALU) performs operations such as addition, subtraction, comparison, shifts, bitwise AND, OR, and exclusive OR. Many processors also include a floating-point unit (FPU) for operations on real-number representations. A digital signal processor or vector unit may perform several arithmetic operations in parallel, which is useful in filtering, image processing, and motor-control calculations.

2.2 Registers

Registers are small, high-speed storage locations inside the processor. General-purpose registers hold operands and intermediate results. Special-purpose registers include:

• Program counter (PC): address of the next instruction to be fetched.
• Instruction register: instruction currently being decoded or executed.
• Stack pointer (SP): address of the active stack region.
• Status or flags register: condition information such as zero, carry, negative, and overflow.
• Control and configuration registers: operating modes and peripheral settings.

Register access is normally faster than access to cache or main memory, but the number of registers is limited by hardware cost and instruction-set design.

2.3 Control Unit and Clock

The control unit coordinates instruction execution. It generates signals that select registers, activate the ALU, read or write memory, and control peripheral operations. A clock provides timing references for synchronous circuits. The clock frequency is measured in hertz; one gigahertz means one billion cycles per second. However, frequency alone does not determine performance. Instructions may require different numbers of cycles, and processors may execute multiple instructions in a cycle or stall while waiting for memory.

2.4 Instruction Execution

A simplified instruction cycle consists of:

1. Fetch: use the PC to obtain an instruction from memory or cache.
2. Decode: determine the operation, operands, and addressing mode.
3. Read operands: obtain data from registers or memory.
4. Execute: perform an ALU, branch, load/store, or control operation.
5. Memory access: read or write data if required.
6. Write-back: place the result in a register or memory.
7. Update PC: select the next sequential or branch target address.

Modern processors overlap these stages in a pipeline. While one instruction is being executed, another may be decoded and a third fetched. Pipeline hazards occur when instructions cannot safely proceed in parallel. Data hazards arise from dependencies, control hazards from branches, and structural hazards when two operations require the same hardware resource. Forwarding, stalling, branch prediction, and out-of-order execution are techniques used to reduce these effects.

A processor that executes an instruction set with relatively simple, regular instructions is often described as reduced instruction set computing (RISC). A complex instruction set computer (CISC) provides more elaborate instructions, sometimes implemented internally as simpler micro-operations. These categories are useful historically, but contemporary processors combine ideas from both approaches.

3. Memory Hierarchy

No single memory technology simultaneously provides maximum speed, capacity, low cost, and non-volatility. Computer systems therefore use a hierarchy.

3.1 Locality

Caches exploit temporal locality, the tendency for recently used data or instructions to be used again, and spatial locality, the tendency for nearby addresses to be accessed soon. A cache hit supplies data from the cache; a cache miss requires access to a lower level.

A commonly used average memory access model is:

Here, T_avg is average access time, T_hit is the time to check and obtain a hit at the current level, r_miss is the miss rate, and P_miss is the additional penalty for accessing the next level. Times must use the same unit, such as nanoseconds. This simplified expression assumes one effective miss-rate category and does not separately model overlapping accesses or multiple cache levels.

For multiple cache levels, the penalty includes the time spent examining each level and the time to obtain data from the first level that contains it. Cache size, associativity, replacement policy, block size, and write policy influence performance.

3.2 RAM and Non-Volatile Memory

Dynamic random-access memory (DRAM) stores bits in capacitors that require periodic refresh. It provides high capacity at reasonable cost but loses its contents when power is removed. Static random-access memory (SRAM) uses bistable circuits and is faster but occupies more silicon area; it is commonly used for processor caches and small embedded memories.

Read-only memory terminology has evolved. Mask ROM and programmable ROM retain data without power. Electrically erasable programmable ROM and flash memory can be electrically reprogrammed. Flash is widely used for firmware and data logging, but it has finite write endurance and often writes in pages while erasing in larger blocks.

4. Buses and Interconnection

A bus or interconnect carries information among components. Traditionally, buses were described using three logical groups:

• Data lines: carry values being transferred.
• Address lines: identify a memory location or device register.
• Control lines: specify read, write, timing, arbitration, interrupt, or acknowledgment operations.

Modern systems may use point-to-point serial links rather than a shared parallel bus. Examples include PCI Express for high-speed expansion, USB for peripherals, Ethernet for networking, and serial interfaces such as SPI, I²C, UART, and CAN in embedded systems.

Important bus properties include:

• Width: number of bits transferred in parallel or represented by an address field.
• Clock or symbol rate: timing or signaling rate.
• Bandwidth: maximum data transfer rate.
• Latency: time between initiating and completing a transfer.
• Arbitration: method for deciding which device may use a shared resource.
• Protocol: rules for framing, addressing, error detection, and acknowledgment.

An idealized peak transfer rate for a parallel data path is:

where B_peak is peak bit rate in bits per second, W is transferred width in bits per cycle, and f is cycles per second. If a bus transfers data on both clock edges, the effective factor may be two; protocol overhead, wait states, encoding, and arbitration reduce practical throughput. Divide by eight to express a bit rate in bytes per second.

4.1 Memory-Mapped and Port-Mapped I/O

In memory-mapped I/O, peripheral registers occupy addresses in the processor's normal address space. A load or store instruction can therefore read or write a device register. Port-mapped I/O uses a separate address space and special instructions. Memory-mapped I/O is common in microcontrollers because it enables a uniform programming model.

A register may contain control bits, status bits, a data value, or a combination. Engineers must follow the device reference manual carefully because some bits are read-only, write-one-to-clear, or affected by hardware events.

5. Input, Output, and Peripherals

A peripheral is a hardware unit that extends the computer's capabilities. Common peripherals include:

• GPIO: digital input and output pins.
• Timers and counters: periodic events, pulse measurement, scheduling, and PWM generation.
• ADC: converts an analog voltage into a digital code.
• DAC: converts a digital code into an analog signal.
• UART: asynchronous serial communication.
• SPI: synchronous, usually full-duplex communication with one or more devices.
• I²C: two-wire addressed serial communication.
• CAN: robust message-based communication widely used in vehicles and machines.
• USB and Ethernet: higher-level peripheral and network connectivity.
• Interrupt controller: prioritizes events requiring processor attention.
• DMA controller: transfers data between peripherals and memory with limited CPU involvement.

5.1 Interrupts and Polling

With polling, the processor repeatedly checks a status register. Polling is simple and predictable for very small systems, but it wastes processing time when events are infrequent. With interrupts, a peripheral signals the processor, which temporarily suspends normal execution and runs an interrupt service routine. Interrupts improve responsiveness and efficiency, but they introduce timing complexity, priority decisions, and possible race conditions.

Direct memory access is valuable for high-rate data streams. A DMA controller can move samples from an ADC into a memory buffer while the CPU performs other work. Correct design requires attention to buffer ownership, cache coherency, alignment, overrun detection, and interrupt timing.

5.2 Sensors and Actuators

Sensors convert physical variables such as position, temperature, pressure, or acceleration into electrical signals. Actuators convert electrical commands into physical action. Hardware design must consider signal range, resolution, sampling rate, noise, isolation, grounding, filtering, protection, and calibration.

For an ideal N-bit ADC with input range from V_min to V_max, the quantization step is approximately:

where q is volts per code and N is the number of bits. This formula assumes an ideal converter and specifies the code spacing; real accuracy is also affected by offset, gain error, nonlinearity, noise, reference accuracy, and sampling behavior.

6. Storage Systems

Storage is distinguished by persistence, access method, capacity, cost, and endurance.

• Register and RAM storage support rapid active computation but are volatile.
• Flash storage is compact, non-volatile, and common for firmware and solid-state drives.
• Solid-state drives use flash with a controller that performs wear leveling, error correction, and address translation.
• Magnetic disks provide high capacity at low cost but have mechanical latency and sensitivity to shock.
• Network and cloud storage provide shared access but depend on communication links, authentication, and service availability.

Sequential access processes data in order; random access permits direct access to an address. Storage selection should account for write frequency, required endurance, environmental conditions, data retention, security, and recovery requirements. A data logger in an industrial machine may require a wear-aware file system, redundant storage, or a strategy that batches writes rather than writing every sensor sample individually.

7. Measuring Performance

Performance is multidimensional. Relevant measures include:

• Latency: time to complete one operation or respond to an event.
• Throughput: amount of work completed per unit time.
• Bandwidth: data-transfer capacity per unit time.
• Response time: elapsed time from request to result.
• Utilization: fraction of a resource's capacity being used.
• Energy per operation: energy consumed to perform a defined task.
• Real-time deadline: latest acceptable completion time.

For a workload containing instructions, a basic CPU execution-time relationship is:

where T_CPU is CPU execution time in seconds, I is instruction count, CPI is average cycles per instruction, and f is clock frequency in cycles per second. The relationship assumes that CPI represents the complete average cost of the workload and that frequency is sufficiently stable. Operating-system delays, I/O waiting, cache effects, interrupts, and thermal throttling may make measured elapsed time larger.

The corresponding instruction throughput is approximately:

where IPS is instructions per second. IPS is useful only for comparable instruction sets and workloads; it should not be treated as a universal measure of application performance.

Worked Example: Execution Time

A control routine executes 240,000 instructions. Its measured average CPI is 2.5, and the processor clock is 120 MHz. The estimated CPU time is:

Thus, the routine requires approximately 5 ms of processor time, assuming no additional waiting or preemption. If it must execute every 10 ms, the estimated CPU utilization for this routine is 5 ms ÷ 10 ms = 0.5, or 50 percent. In a real-time system, remaining capacity is needed for interrupts, other tasks, and timing variation.

Amdahl's law helps explain why accelerating one part of a system has limited total effect. If fraction p of execution time is improved by a factor s, the overall speedup is:

Here, 0 ≤ p ≤ 1 and s ≥ 1. The formula assumes the workload is fixed and that the improved and unimproved portions are correctly identified. For example, if 70% of execution time is accelerated by 4 times, the speedup is 1 ÷ (0.30 + 0.70 ÷ 4) ≈ 2.105. Improving the remaining 30% may be more valuable than further accelerating the already improved portion.

8. Microcontrollers and Microprocessors

A microprocessor is primarily a CPU and normally depends on external memory and peripherals. A desktop CPU, server processor, or high-performance embedded CPU is a microprocessor-based solution.

A microcontroller unit (MCU) integrates a processor core, memory, timers, communication interfaces, GPIO, and often ADCs or PWM units on one chip. MCUs are designed for dedicated control tasks, low cost, low power, deterministic I/O, and compact circuit boards.

An MCU may be programmed using bare-metal firmware, a real-time operating system (RTOS), or an embedded operating system. An RTOS provides task scheduling, timing services, synchronization, and communication mechanisms. It does not automatically make a system deterministic: interrupt behavior, memory allocation, priority inversion, drivers, and worst-case execution time must still be analyzed.

A programmable logic controller (PLC) is another important industrial platform. PLCs emphasize robust operation, standardized industrial I/O, diagnostics, and maintainability. A single-board computer may offer greater computing and networking capability but may require more careful design for boot reliability, storage integrity, and real-time behavior.

9. Selecting Hardware for Engineering Tasks

Hardware selection should begin with requirements rather than brand names or processor frequency. A practical process is:

1. Define functions: sensing, control, communication, logging, visualization, and safety.
2. Specify timing: sampling periods, control deadlines, startup time, and allowable jitter.
3. Estimate computation: arithmetic complexity, instruction demand, floating-point needs, and acceleration.
4. Specify data: memory size, storage capacity, data rates, retention, and write endurance.
5. Specify interfaces: voltage levels, ADC channels, PWM outputs, bus protocols, connectors, and isolation.
6. Assess environment: temperature, vibration, humidity, dust, electromagnetic interference, and supply variation.
7. Assess power: average and peak consumption, battery life, thermal dissipation, and power-fail behavior.
8. Assess safety and security: fault detection, safe states, authentication, secure updates, and access control.
9. Assess lifecycle: component availability, development tools, certification, support, and maintainability.
10. Prototype and verify: benchmark the actual workload and test worst-case conditions.

A useful selection matrix assigns weights to requirements and scores candidate platforms. Numerical scoring does not replace engineering judgment, but it makes trade-offs explicit. For a motor controller, deterministic timer and PWM behavior may matter more than display capability. For machine vision, memory bandwidth and accelerator support may matter more than the number of GPIO pins.

Illustrative Case: Conveyor Sorting Controller

Background. A small conveyor must identify packages using a photoelectric sensor and color sensor, then activate a pneumatic diverter. The control system must operate from a 24 V industrial supply and communicate status to a supervisory computer.

Problem. The controller must sample sensors every 1 ms, determine whether a package meets a programmed criterion, and trigger the diverter within 20 ms of detection. It must tolerate electrical noise and record fault conditions.

Analysis. A general-purpose desktop computer would provide more processing than required but would add size, power consumption, boot complexity, and uncertain I/O timing. A small MCU with hardware timers, ADC inputs, digital filtering, PWM or timed outputs, and CAN or Ethernet is more suitable. The 24 V signals cannot be connected directly to typical 3.3 V MCU pins; protected input circuits, level conversion, and electrical isolation may be necessary.

Approach. The design uses an industrial MCU board with a watchdog timer, isolated digital input, ADC, timer capture, and communication interface. A timer schedules the 1 ms task. Sensor readings are filtered, but the filter is selected so that it does not violate the 20 ms response requirement. The diverter output is driven through a protected transistor or relay interface rather than directly from a GPIO pin. A watchdog resets the controller if software stops servicing it. Fault states disable the actuator and report the cause.

Outcome. The MCU meets the computational and timing requirements with substantially lower complexity than a general-purpose computer. Verification includes worst-case interrupt latency, sensor-noise testing, power-cycle testing, watchdog testing, and electromagnetic compatibility testing.

Learning points. Requirements determine architecture. Electrical compatibility is as important as software compatibility. A hardware choice must include protection, diagnostics, timing verification, maintainability, and safe failure behavior.

10. Reliability, Safety, Security, and Ethics

Hardware failures can cause financial loss, environmental harm, or injury. Engineers should design for fault detection, graceful degradation, and a defined safe state. Watchdogs, redundant sensing, current limiting, over-temperature protection, brownout detection, and emergency-stop circuits are examples of protective measures. Safety functions should not depend solely on ordinary application software when an independent safety mechanism is required.

Cybersecurity is also a hardware concern. Connected controllers may require secure boot, signed firmware, protected debug ports, encrypted communication, unique device identities, least-privilege access, and secure update procedures. Default passwords and undocumented service interfaces create avoidable risks. Security controls must be balanced with maintainability and the ability to recover a failed device.

Environmental responsibility includes energy efficiency, repairability, component sourcing, hazardous-substance compliance, and end-of-life recycling. Engineers should avoid unnecessary over-specification because larger processors and power supplies increase cost and energy use. At the same time, excessive cost reduction can reduce reliability and increase lifecycle waste.

11. Contemporary Developments

Current systems increasingly combine CPUs with GPUs, neural-processing units, digital signal processors, and programmable logic. These accelerators can improve performance for vision, simulation, and machine learning, but they introduce data-transfer overhead, programming complexity, thermal demands, and verification challenges.

Edge computing places processing near sensors and actuators. It can reduce network latency and preserve privacy, but local devices still require secure updates and adequate resources. Heterogeneous systems combine cores with different performance and power characteristics. RISC-V is an example of an open ISA ecosystem that permits customized processor implementations, although a complete product still depends on toolchains, verification, peripherals, and long-term support.

Artificial intelligence is relevant when hardware must execute inference models locally. Selection should consider model size, arithmetic precision, memory bandwidth, accelerator support, latency, and energy per inference. A neural accelerator is not automatically beneficial if data movement dominates computation or if the application cannot tolerate uncertain execution time.

Best Practices

• Start from measurable system requirements.
• Distinguish average performance from worst-case timing.
• Benchmark representative workloads rather than relying on clock frequency.
• Account for communication and memory bottlenecks.
• Use hardware protection and electrical isolation where appropriate.
• Document pin assignments, timing assumptions, interfaces, and failure behavior.
• Design for software updates, diagnostics, testing, and component obsolescence.
• Verify the complete system under temperature, voltage, load, and fault conditions.
• Treat safety and cybersecurity as design requirements, not final additions.

Chapter Summary

Computer architecture organizes processing, memory, input, output, and interconnection into a programmable system. The processor executes instructions through fetch, decode, operand access, execution, memory access, and write-back stages; pipelines overlap these activities but introduce hazards. Registers and caches provide speed, while DRAM and persistent storage provide increasing capacity at greater latency.

Buses and interfaces transfer addresses, data, and control information. GPIO, timers, ADCs, DACs, communication interfaces, interrupts, and DMA connect computation to sensors, actuators, and networks. Performance must be evaluated through execution time, latency, throughput, bandwidth, energy, and real-time deadlines. Basic models such as T_CPU = I × CPI ÷ f and Amdahl's law are useful when their assumptions are understood.

Microcontrollers integrate computation, memory, and peripherals for dedicated embedded tasks, whereas microprocessors and computers support more demanding general-purpose workloads. Hardware selection for mechatronics requires analysis of timing, computation, memory, interfaces, environment, power, safety, security, lifecycle, and maintainability. The best design is not necessarily the most powerful; it is the one that satisfies verified requirements reliably and safely.

Key Terms

Processor: Hardware unit that interprets and executes instructions.

Instruction set architecture: Programmer-visible specification of instructions, registers, data types, and addressing.

ALU: Unit that performs arithmetic and logical operations.

Register: Small, high-speed storage location inside a processor.

Cache: Fast memory that stores recently or frequently used instructions and data.

Locality: Tendency of programs to reuse recent or nearby memory locations.

DRAM: Volatile main memory that requires periodic refresh.

Flash memory: Non-volatile, electrically reprogrammable memory.

Bus: Communication path carrying data, addresses, and control information.

Bandwidth: Maximum or measured data-transfer rate.

Latency: Time between initiating an operation and receiving its result.

Peripheral: Hardware unit that provides specialized input, output, timing, communication, or control functions.

Interrupt: Event signal that requests processor service.

DMA: Hardware mechanism for transferring data without continuous CPU control.

Microcontroller: Integrated chip containing a processor, memory, and peripherals for embedded control.

Real-time system: System whose correctness depends on both results and timing.

CPI: Average number of clock cycles required per instruction.

Throughput: Amount of work completed per unit time.

Watchdog timer: Timer that resets or signals a system if software fails to respond.

Memory-mapped I/O: Peripheral-register access using addresses in the processor's memory address space.

Review Questions

Short Answer Questions

1. What is the difference between computer architecture and computer organization?
2. What are the main stages of a simplified instruction cycle?
3. Why are caches effective when programs exhibit locality?
4. Distinguish latency from bandwidth.
5. State two advantages of a microcontroller in an embedded control system.

Long Answer Questions

1. Explain the memory hierarchy and discuss the trade-offs among speed, capacity, cost, and volatility.
2. Describe how interrupts and DMA improve the operation of an embedded system, including their design challenges.
3. Explain processor pipelining and discuss data, control, and structural hazards.
4. Compare a microcontroller, PLC, and single-board computer for industrial automation.
5. Develop a systematic hardware-selection process for a robotic subsystem.

Analytical / Application Questions

1. A routine executes 600,000 instructions with an average CPI of 1.8 on a 90 MHz processor. Calculate the estimated CPU execution time and determine whether it fits within a 20 ms period, ignoring operating-system and I/O delays.
2. An engineering team can accelerate 60% of a workload by a factor of 5. Use Amdahl's law to calculate the total speedup and explain why the result is less than 5.
3. Select an appropriate hardware platform for a battery-powered environmental monitoring node that samples temperature and humidity, stores readings, transmits data once per hour, and must operate unattended for one year. Justify the processor, memory, storage, communication, power, reliability, and security choices.

Multiple Choice Questions with Answers

Question 1

Which component normally holds the address of the next instruction to be fetched?

A. Program counter

B. Arithmetic and logic unit

C. Status register

D. Direct-memory access controller

Correct Answer: A. Program counter

Question 2

Which memory characteristic is most directly exploited by a processor cache?

A. Electrical isolation

B. Program locality

C. Mechanical rotation

D. Permanent data retention

Correct Answer: B. Program locality

Question 3

A processor executes 100,000 instructions with an average CPI of 2 at 100 MHz. What is the estimated CPU execution time?

A. 0.2 ms

B. 1 ms

C. 2 ms

D. 20 ms

Correct Answer: C. 2 ms

Question 4

Which device is most appropriate for generating precise periodic events and measuring pulse timing in an embedded controller?

A. Timer/counter peripheral

B. Flash memory

C. Cache controller

D. Keyboard interface

Correct Answer: A. Timer/counter peripheral

Question 5

What is a principal advantage of DMA?

A. It eliminates the need for memory

B. It transfers data while reducing continuous CPU involvement

C. It converts analog signals directly into mechanical motion

D. It increases flash write endurance automatically

Correct Answer: B. It transfers data while reducing continuous CPU involvement

Question 6

Which statement best distinguishes a microcontroller from a typical microprocessor?

A. A microcontroller integrates processing, memory, and peripherals on one chip

B. A microcontroller cannot execute stored programs

C. A microprocessor always consumes less power

D. A microprocessor cannot communicate with peripherals

Correct Answer: A. A microcontroller integrates processing, memory, and peripherals on one chip

Question 7

A bus has a width of 16 bits and transfers data at 50 million cycles per second, with one transfer per cycle. What is its ideal peak rate?

A. 0.8 Mbit/s

B. 16 Mbit/s

C. 50 Mbit/s

D. 800 Mbit/s

Correct Answer: D. 800 Mbit/s

Question 8

Which performance measure describes the amount of work completed per unit time?

A. Latency

B. Throughput

C. Address width

D. Cache associativity

Correct Answer: B. Throughput

Question 9

Why should a 24 V industrial sensor generally not be connected directly to a typical 3.3 V microcontroller input?

A. The sensor signal may exceed the pin's electrical limits

B. The microcontroller cannot execute interrupts

C. Flash memory is volatile

D. The processor requires a magnetic disk

Correct Answer: A. The sensor signal may exceed the pin's electrical limits

Question 10

Which consideration is especially important when selecting storage for frequent industrial data logging?

A. Screen resolution

B. Write endurance and data-retention behavior

C. Number of processor registers

D. Pipeline branch depth

Correct Answer: B. Write endurance and data-retention behavior