Chapter 10
Semiconductor, Analog and Digital Electronics
Bachelors Program in Electrical Engineering
Fundamentals of Electrical Engineering
•
Bachelor
Semiconductor, Analog and Digital Electronics
Introduction
Electrical engineering systems increasingly combine semiconductor devices, analog signal conditioning, digital logic, embedded computation, sensing, and power conversion. A sensor may produce a small analog voltage; an amplifier and filter condition it; an analog-to-digital converter (ADC) represents it numerically; digital logic processes the data; and a digital-to-analog converter (DAC) or power stage drives an actuator. Understanding the underlying devices and interfaces is therefore essential for analysis, design, troubleshooting, and safe professional practice.
Semiconductor electronics is based primarily on silicon, whose conductivity can be controlled by doping, electric fields, temperature, and applied voltage. The diode provides one-way conduction, the transistor provides controlled amplification or switching, the operational amplifier (op-amp) performs accurate analog functions using feedback, and logic gates implement Boolean decision-making. These devices are idealized in introductory analysis, but practical design must consider tolerances, frequency response, noise, power dissipation, loading, and nonideal switching behavior.
Learning Objectives
After studying this chapter, the reader should be able to:
Explain intrinsic and extrinsic semiconductor behavior and the formation of a p–n junction.
Analyze diode circuits, rectifiers, filters, and basic regulation.
Describe transistor operation as an amplifier and as a switch.
Analyze common op-amp circuits and first-order filters.
Interpret logic gates and Boolean functions using truth tables and algebra.
Distinguish combinational from sequential circuits.
Explain practical analog–digital interfaces and their limitations.
1. Semiconductor Fundamentals
1.1 Charge carriers and doping
A semiconductor has electrical conductivity between that of a conductor and an insulator. In pure, or intrinsic, silicon, thermal energy creates electron–hole pairs. An electron is a mobile negative charge carrier, while a hole behaves as a mobile positive carrier.
Doping introduces controlled impurity atoms. Donor atoms contribute extra electrons and produce n-type material; acceptor atoms create holes and produce p-type material. In an electrically neutral material, the concentrations of mobile carriers and fixed ionized dopants balance overall charge. Conductivity is commonly represented by
σ = q(nμn + pμp)
where σ is conductivity in siemens per metre, q is the elementary charge, n and p are electron and hole concentrations in m⁻³, and μ_n and μ_p are their mobilities in m²/(V·s). The expression assumes low-field drift and uniform material properties. Resistivity is ρ = 1/σ.
1.2 The p–n junction
When p-type and n-type regions are joined, electrons diffuse from the n side toward the p side, while holes diffuse in the opposite direction. Recombination leaves fixed charged ions near the junction, creating a depletion region and an internal electric field. This field establishes a built-in potential and opposes further diffusion.
Forward bias reduces the depletion barrier and permits substantial current. Reverse bias widens the depletion region and produces only a small minority-carrier current until breakdown. A simplified diode equation is
ID = IS [eVD/(nVT) − 1]
where I_D is diode current, I_S is reverse saturation current, V_D is diode voltage, n is the ideality factor (approximately 1 to 2), and V_T = kT/q is the thermal voltage. At 25 °C, V_T is approximately 25.9 mV. The equation assumes a stable junction temperature and neglects high-current series resistance, breakdown, and significant generation–recombination departures from the model.
For hand analysis, a silicon diode is often approximated as an open circuit when reverse biased and as a fixed drop of approximately 0.7 V when forward biased. This is a convenient model, not a universal physical constant; the actual voltage depends on current, temperature, and device construction.
2. Diodes and Rectifier Circuits
2.1 Diode applications
Diodes are used for rectification, signal clipping, clamping, protection against reverse polarity, voltage reference circuits, light emission, and high-speed switching. Important specifications include maximum forward current, peak inverse voltage (PIV), reverse leakage, forward voltage, power rating, switching time, and thermal resistance.
The instantaneous diode power is
pD(t) = vD(t)iD(t)
and average power is the time average of p_D(t). A design must ensure that both peak and average ratings are respected, including transient conditions.
2.2 Half-wave rectifier
A single diode connected to an AC source passes one half-cycle and blocks the other. For an ideal sinusoidal source v_s(t) = V_m sin(ωt) and resistive load R, the average output voltage is
VDC = Vm/π
and the rms output voltage is V_m/2. These results assume an ideal diode, no transformer resistance, and a purely resistive load. With a constant forward drop V_F, the actual conduction interval and output values are lower.
2.3 Full-wave rectifier
A center-tapped or bridge rectifier produces an output during both half-cycles. For an ideal full-wave rectifier,
VDC = 2Vm/π
The ripple frequency is twice the AC source frequency. A bridge uses four diodes, but only two conduct in each half-cycle, so the approximate conducting-path drop is 2V_F. The peak inverse voltage requirement differs between bridge and center-tapped arrangements and must be checked from the circuit topology.
2.4 Capacitor-input filtering
A capacitor across the rectifier load charges near each voltage peak and discharges through the load between peaks. If the ripple is small, an approximate peak-to-peak ripple voltage is
Vr(pp) ≈ IL/(fr C)
where I_L is load current, f_r is ripple frequency, and C is capacitance. The approximation assumes nearly constant load current and a short charging interval. For a full-wave rectifier supplied by frequency f, f_r ≈ 2f. The approximate average output is
VDC ≈ Vpeak − VF,path − Vr(pp)/2
where V_F,path is the total forward drop in the conducting path. Capacitor ripple current, equivalent series resistance, inrush current, and transformer regulation may be important in practical power supplies.
Worked Example 1: Rectifier capacitor
A full-wave bridge is supplied by 12 V rms, 50 Hz. Assume two diode drops of 0.7 V, a 1000 μF capacitor, and a 100 mA load.
The source peak is V_m = √2(12 V) ≈ 16.97 V. The approximate capacitor maximum is 16.97 − 1.4 = 15.57 V. Ripple frequency is 100 Hz. Therefore,
V_r(pp) ≈ 0.1/(100 × 0.001) = 1.0 V.
Thus V_DC ≈ 15.57 − 0.5 = 15.07 V. This is an estimate; diode conduction angle, source impedance, capacitor ESR, and load variation can produce a different measured value.
2.5 Zener regulation
A reverse-biased Zener diode can maintain an approximately constant voltage over a specified current range. A series resistor limits current. For supply voltage V_S, load current I_L, Zener current I_Z, and resistor R_S,
RS = (VS − VZ)/(IL + IZ)
The design must verify the worst-case minimum Zener current for regulation and maximum Zener power P_Z,max ≥ V_Z I_Z,max. Zener circuits are inefficient for high power because the resistor continuously dissipates energy.
3. Transistors
3.1 Bipolar junction transistor
A BJT has emitter, base, and collector regions. In active operation, the base–emitter junction is forward biased and the base–collector junction is reverse biased. For a common-emitter arrangement,
IC ≈ β IB
where β is the common-emitter current gain. This relationship is useful for approximate bias calculations but β varies widely with current, temperature, and device. A more fundamental relation is I_E = I_C + I_B.
A BJT used as a switch operates mainly in cutoff and saturation. In cutoff, base drive is insufficient and collector current is approximately zero. In saturation, both junctions are forward biased and the collector–emitter voltage is low, often approximated by V_CE(sat) from the data sheet. A switching design should provide sufficient base current without exceeding base-emitter or collector current ratings.
3.2 Field-effect transistor
A MOSFET controls channel current using gate voltage. The insulated gate draws extremely small steady-state current, although charging and discharging its gate capacitance requires current during switching. An n-channel enhancement MOSFET begins strong conduction when V_GS exceeds its threshold voltage V_TH, but V_TH is not a specification for a desired low on-resistance. The data-sheet R_DS(on) must be checked at the actual gate-drive voltage.
In switching applications, conduction loss is approximately
Pcond ≈ ID² RDS(on)
and capacitive switching loss increases with switching frequency. Gate-driver design, parasitic inductance, voltage overshoot, electromagnetic interference, and thermal management are significant practical concerns.
4. Operational Amplifiers and Analog Circuits
An op-amp is a high-gain differential amplifier with two inputs and one output. Its open-loop relation is approximately v_o = A(v_+ − v_−), but A is finite and frequency dependent. With negative feedback, ideal analysis commonly assumes:
input currents are zero;
the differential input voltage is zero when the amplifier operates linearly;
the output remains within its supply rails.
These assumptions are consequences of a very large open-loop gain and input resistance, not physical absolutes.
4.1 Inverting and non-inverting amplifiers
For an inverting amplifier with input resistor R_in and feedback resistor R_f,
vo = −(Rf/Rin)vi
The input impedance seen by the source is approximately R_in. For a non-inverting amplifier,
vo = (1 + Rf/Rg)vi
where R_g connects the inverting input to the reference node. These equations assume ideal resistors, a linear operating region, negligible input bias effects, and adequate bandwidth and slew rate.
4.2 Summing, difference, and integrator circuits
An inverting summing amplifier produces
vo = −Rf(v1/R1 + v2/R2 + … + vn/Rn)
A difference amplifier can subtract two signals, but accurate resistor matching is essential for good common-mode rejection. An ideal inverting integrator follows
vo(t) = −(1/RC)∫vi(t)dt + vo(t0)
where R and C are the input resistance and feedback capacitance. In practice, a resistor is often placed in parallel with the capacitor to limit DC gain and prevent saturation from offset voltage.
4.3 Nonideal op-amp behavior
Real op-amps have finite gain-bandwidth product, input offset voltage, input bias currents, limited output current, finite common-mode rejection ratio (CMRR), power-supply rejection limits, noise, and finite slew rate. The output cannot instantaneously follow an arbitrarily large signal. A circuit that is correct under ideal assumptions may clip or distort when its output swing, frequency, or load exceeds the data-sheet limits.
5. Analog Filters
A filter selectively attenuates or passes frequency components. The transfer function is
H(jω) = Vo(jω)/Vi(jω)
where j = √−1 and ω = 2πf is angular frequency in rad/s. For a first-order RC low-pass filter,
H(jω) = 1/(1 + jωRC)
Its cutoff frequency, defined where the magnitude is 1/√2 of the low-frequency value (−3.01 dB), is
fc = 1/(2πRC)
A high-pass RC filter has
H(jω) = jωRC/(1 + jωRC)
Both expressions assume ideal source and load conditions. If the source resistance or load resistance is comparable with R, the effective time constant changes. Higher-order active filters provide greater roll-off but may introduce sensitivity, noise, and stability concerns.
6. Digital Logic and Boolean Functions
Digital circuits represent information using discrete logic levels. Positive logic commonly assigns a low voltage to 0 and a high voltage to 1. The actual input thresholds and output voltage guarantees depend on the logic family, supply voltage, loading, and temperature. Noise margins quantify the tolerance between guaranteed output levels and input thresholds.
The fundamental gates are:
Gate
Boolean expression
Function
NOT
Y = ¬A
Inverts A
AND
Y = AB
1 only when all inputs are 1
OR
Y = A + B
1 when at least one input is 1
NAND
Y = ¬(AB)
Inverted AND
NOR
Y = ¬(A + B)
Inverted OR
XOR
Y = A ⊕ B
1 when inputs differ
XNOR
Y = ¬(A ⊕ B)
1 when inputs agree
Here, + denotes OR and juxtaposition denotes AND; these symbols are not ordinary arithmetic operations. NAND and NOR are universal gates because either type alone can implement NOT, AND, and OR.
6.1 Boolean algebra
Useful identities include:
A + 0 = A, A·1 = A, A + 1 = 1, A·0 = 0
A + A = A, A·A = A, A + ¬A = 1, A·¬A = 0
De Morgan’s laws are
¬(AB) = ¬A + ¬B
¬(A + B) = ¬A·¬B
A truth table lists output values for every input combination. Karnaugh maps provide a visual method for minimizing Boolean expressions, with adjacent groups formed in powers of two. Simplification reduces gate count, delay, power consumption, and often cost.
7. Combinational and Sequential Circuits
A combinational circuit’s output depends only on present inputs. Examples include adders, subtractors, multiplexers, demultiplexers, encoders, decoders, and comparators. A half-adder has sum S = A ⊕ B and carry C = AB. A full-adder additionally includes carry-in C_in:
S = A ⊕ B ⊕ Cin
Cout = AB + Cin(A ⊕ B)
Sequential circuits contain memory, so their output depends on present inputs and previous state. Latches and flip-flops store binary information. A D flip-flop transfers D to Q on an active clock edge, subject to setup and hold-time requirements. Violating these timing requirements can cause metastability, in which the output takes an unpredictable time to resolve to a logic level.
Registers store multiple bits. Counters progress through defined states, and finite-state machines combine state memory with next-state and output logic. Synchronous design uses a common clock and explicit timing constraints; asynchronous designs may respond immediately but are more difficult to analyze reliably.
A simplified timing condition for a synchronous path is
Tclk ≥ tpcq + tpd + tsetup + tskew
where T_clk is clock period, t_pcq is clock-to-Q delay, t_pd is combinational propagation delay, t_setup is receiving flip-flop setup time, and t_skew represents relevant clock skew. The expression is a design approximation and does not replace timing analysis across process, voltage, and temperature corners.
8. Analog–Digital Interfaces
A practical mixed-signal system can be represented as:
Analog and digital signal interface chain
Figure: Analog and digital signal interface chain
Figure: A typical sensor-to-digital processing chain and the corresponding reverse path.
8.1 Sampling and quantization
An ADC samples an analog signal at sampling frequency f_s. To avoid aliasing, the input must be appropriately band-limited and, for a sinusoidal component of maximum frequency f_max, the ideal sampling condition is
fs > 2fmax
This is the Nyquist condition; practical systems use margin and an anti-aliasing low-pass filter. Frequencies above half the sampling rate can appear as lower, false frequencies after sampling.
An N-bit ADC with reference range V_ref has 2^N nominal codes. The ideal quantization step is approximately
q = Vrange/2N
where V_range is the input span. Quantization error is commonly modeled as bounded by approximately ±q/2 for an ideal, non-overloaded converter, although real ADCs also exhibit offset error, gain error, integral nonlinearity, noise, missing codes, and reference instability.
A DAC converts a code into an analog level. Reconstruction filtering smooths the staircase or sample-and-hold waveform. Interface design must also address grounding, reference decoupling, signal levels, impedance, protection, clock jitter, and electromagnetic compatibility.
9. Illustrative Case: Temperature-Controlled Process
Background and problem
Consider an illustrative laboratory incubator requiring temperature measurement and heater control. A resistance temperature sensor produces a small voltage after signal conditioning. The controller must maintain 37.0 °C while rejecting electrical noise and preventing unsafe heating.
Analysis
The sensor output is analog and may include a 50 Hz interference component. An instrumentation amplifier provides high input impedance and differential measurement, followed by a low-pass filter whose cutoff is well above the desired temperature-change bandwidth but below significant interference. The ADC must have sufficient resolution: if the conditioned temperature range is 0–50 °C and the required ideal resolution is 0.1 °C, at least 500 distinguishable intervals are needed, so N must satisfy 2^N ≥ 500; 9 bits is the mathematical minimum, while a 10- or 12-bit ADC provides practical margin.
Approach and solution
A microcontroller samples above twice the filter passband, checks sensor plausibility, and applies a control algorithm. A transistor or MOSFET switches heater power. A flyback diode is required if the load is inductive, such as a relay coil. Independent thermal cutoff hardware disconnects the heater if temperature exceeds a safe limit. The digital output is converted into a duty cycle using pulse-width modulation, with filtering or thermal inertia producing approximately analog heating power.
Outcome and learning points
The system illustrates that no single component solves the engineering problem. Accurate control depends on sensor calibration, analog gain, anti-alias filtering, ADC reference quality, software timing, power-stage protection, and fail-safe design. Safety-critical functions should not rely solely on software or on an unverified transistor rating. Traceable calibration, documented limits, testing across temperature and supply conditions, and electromagnetic compatibility testing are professional best practices.
10. Limitations, Safety, and Contemporary Practice
Idealized circuit models are valuable because they expose the governing relationships, but designers must transition to data-sheet and simulation models before implementation. Temperature changes semiconductor parameters; semiconductor failure can create short circuits or excessive heat; and high-voltage rectifiers may retain dangerous charge after power is removed. Isolation, fusing, creepage and clearance, protective earth, current limiting, and discharge procedures are essential.
Modern systems increasingly use integrated mixed-signal devices, switching converters, silicon-carbide and gallium-nitride power semiconductors, high-resolution ADCs, and digitally assisted analog calibration. These technologies improve efficiency and integration but introduce faster edges, stricter layout requirements, electromagnetic interference, and more demanding thermal design. AI may assist fault diagnosis or adaptive control, but its use does not remove the need for deterministic protection, validation, cybersecurity, and human responsibility in safety-related equipment.
A sound design workflow is: define signal ranges and safety requirements; select an appropriate model; calculate nominal operation; check worst-case tolerances and transients; simulate; build and measure a prototype; compare measurements with specifications; and document assumptions and verification results.
Chapter Summary
Semiconductors control conductivity through mobile carriers and junction electric fields. The p–n junction gives the diode its rectifying behavior, while BJTs and MOSFETs provide controlled amplification and switching. Half-wave and full-wave rectifiers convert AC to pulsating DC, and capacitors reduce ripple according to load current, ripple frequency, and capacitance. Zener diodes provide limited-current voltage regulation.
Op-amps use negative feedback to implement inverting, non-inverting, summing, difference, integrating, and filtering functions. Their ideal equations require linear operation and adequate bandwidth, while real devices impose offset, noise, output-swing, current, and slew-rate limits. RC filters are characterized by transfer functions and cutoff frequency.
Digital logic represents discrete states using gates and Boolean algebra. Combinational circuits depend on current inputs; sequential circuits also retain state and require timing discipline. ADCs and DACs connect analog and digital domains, requiring anti-aliasing, adequate sampling, quantization analysis, references, protection, and careful grounding. Reliable engineering combines mathematical models with data-sheet verification, worst-case analysis, measurement, safety controls, and documented testing.
Key Terms
Semiconductor: Material whose conductivity lies between that of a conductor and an insulator.
Doping: Controlled addition of impurities to alter semiconductor carrier concentration.
p–n junction: Interface between p-type and n-type semiconductor regions.
Depletion region: Junction region depleted of mobile charge carriers.
Diode: Two-terminal semiconductor device that conducts preferentially in one direction.
Rectifier: Circuit that converts alternating voltage or current into unidirectional output.
Ripple: Residual periodic variation on a rectified or filtered DC output.
Zener diode: Diode designed to operate in controlled reverse breakdown.
BJT: Bipolar junction transistor controlled primarily by base current.
MOSFET: Field-effect transistor controlled by gate-to-source voltage.
Operational amplifier: High-gain differential amplifier normally used with feedback.
Negative feedback: Returning part of an output signal to reduce error and control behavior.
Cutoff frequency: Frequency at which a first-order filter magnitude falls to 1/√2 of its passband value.
Boolean algebra: Algebraic system for binary variables and logical operations.
Logic gate: Digital circuit implementing a Boolean function.
Combinational circuit: Circuit whose output depends only on present inputs.
Sequential circuit: Circuit whose output depends on inputs and stored state.
Metastability: Temporary uncertain state caused by violation of a flip-flop timing requirement.
ADC: Converter that maps an analog quantity into a digital code.
Aliasing: False frequency representation caused by insufficient sampling and inadequate input filtering.
Review Questions
Short Answer Questions
What physical process creates the depletion region in a p–n junction?
Why does a full-wave rectifier have a ripple frequency twice the source frequency?
State the ideal voltage gain of an inverting op-amp amplifier.
What is the purpose of an anti-aliasing filter before an ADC?
Distinguish a combinational circuit from a sequential circuit.
Long Answer Questions
Explain intrinsic and extrinsic semiconductor behavior and derive the qualitative operation of a forward- and reverse-biased p–n junction.
Compare half-wave, center-tapped full-wave, and bridge rectifiers, including ripple, diode stress, and practical losses.
Explain BJT and MOSFET operation as electronic switches and identify important design ratings.
Analyze ideal inverting, non-inverting, summing, and first-order active filter circuits, stating the assumptions used.
Explain Boolean minimization, universal gates, flip-flops, setup time, hold time, and metastability.
Analytical / Application Questions
Design a capacitor-input filter for a full-wave 60 Hz rectifier delivering 150 mA with no more than 1.5 V peak-to-peak ripple. State the capacitance estimate and practical considerations.
A sensor signal varies from 0 to 2 V and contains useful frequencies below 100 Hz. Select a minimum sampling frequency and explain the required analog filtering and ADC resolution considerations.
Develop a safe block-level design for a microcontroller-controlled DC motor system, identifying the sensor interface, protection devices, power transistor, flyback path, timing issues, and fail-safe behavior.
Multiple Choice Questions with Answers
Question 1
Which condition most directly characterizes forward bias of a p–n junction?
A. The depletion barrier is reduced and significant current can flow.
B. The depletion region widens and current becomes exactly zero.
C. Both junction terminals are disconnected from the supply.
D. The semiconductor becomes a perfect conductor.
Correct Answer: A. The depletion barrier is reduced and significant current can flow.
Question 2
A full-wave rectifier is supplied by a 50 Hz sinusoidal source. Its principal ripple frequency is approximately:
A. 25 Hz
B. 50 Hz
C. 100 Hz
D. 150 Hz
Correct Answer: C. 100 Hz
Question 3
A 1 kΩ input resistor and 10 kΩ feedback resistor are used in an ideal inverting op-amp circuit. The voltage gain is:
A. +0.1
B. −0.1
C. +10
D. −10
Correct Answer: D. −10
Question 4
For an RC low-pass filter, the −3 dB cutoff frequency is:
A. RC/(2π)
B. 1/(2πRC)
C. 2πRC
D. 1/(RC²)
Correct Answer: B. 1/(2πRC)
Question 5
Which gate produces a logic 1 only when its two inputs are different?
A. AND
B. OR
C. XOR
D. XNOR
Correct Answer: C. XOR
Question 6
Which Boolean identity is De Morgan’s law?
A. A + 0 = A
B. A·A = A
C. ¬(AB) = ¬A + ¬B
D. A + ¬A = 0
Correct Answer: C. ¬(AB) = ¬A + ¬B
Question 7
A circuit whose output depends on both present inputs and previously stored information is a:
A. Combinational circuit
B. Sequential circuit
C. Passive resistor network
D. Rectifier only
Correct Answer: B. Sequential circuit
Question 8
If a full-wave rectifier supplies 0.1 A to a capacitor input filter at 100 Hz, using C = 1000 μF, the approximate ripple is:
A. 0.01 V peak-to-peak
B. 0.1 V peak-to-peak
C. 1.0 V peak-to-peak
D. 10 V peak-to-peak
Correct Answer: C. 1.0 V peak-to-peak
Question 9
The main purpose of an anti-aliasing filter is to:
A. Increase transistor gain
B. Limit input frequency components before sampling
C. Convert digital codes into analog voltage
D. Provide reverse bias to a Zener diode
Correct Answer: B. Limit input frequency components before sampling
Question 10
For an ideal N-bit ADC with input span V_range, the nominal quantization step is approximately:
A. V_range × 2^N
B. V_range/N
C. N/V_range
D. V_range/2^N
Correct Answer: D. V_range/2^N
Fundamentals of Electrical Engineering
Chapter 10
of 15