Processor and Embedded Computer Architecture

Introduction and Context

An embedded system is a computer-based system designed to perform a dedicated function, often under constraints of time, power, cost, size, reliability, and safety. Its processor is not selected merely for maximum computational speed. The architecture must provide an appropriate balance among instruction-set capability, real-time determinism, memory capacity, peripheral integration, development cost, energy consumption, security, and long-term availability.

Embedded processors range from small 8-bit microcontrollers to multicore 64-bit application processors and specialized digital signal processors (DSPs). A modern product may also combine general-purpose processor cores with GPUs, neural-processing units, programmable logic, security engines, and real-time control cores. Understanding the architectural trade-offs among these alternatives is therefore central to embedded-system design.

Learning Objectives

After studying this chapter, the learner should be able to:

1. Distinguish microcontrollers, microprocessors, DSPs, and heterogeneous processors.

2. Explain instruction-set architecture, processor datapaths, control units, and privilege models.

3. Analyze pipelining, hazards, branch behavior, and real-time consequences.

4. Explain memory hierarchies, caches, buses, interrupts, DMA, and memory-mapped I/O.

5. Apply performance, cost, and energy models to architecture selection.

6. Evaluate an embedded architecture for functional, real-time, safety, security, and lifecycle requirements.

1. Embedded Processor Classes

1.1 Microcontrollers

A microcontroller unit (MCU) integrates a processor core, nonvolatile program memory, volatile data memory, timers, serial interfaces, analog peripherals, clock circuitry, and interrupt controllers on one integrated circuit. MCUs are optimized for low cost, low power, compact design, and direct control of physical devices. Typical applications include motor control, sensors, appliances, automotive body electronics, and wearable devices.

Integration reduces printed-circuit-board area and communication overhead. It also improves energy efficiency because data can remain close to the processor. Many MCUs provide deterministic interrupt response and tightly coupled memory, which are valuable in control systems. Their limitations may include modest memory capacity, lower peak throughput, and restricted operating-system support.

1.2 Microprocessors

A microprocessor unit (MPU) generally contains a more powerful CPU but relies on external or separate memory and peripherals. MPUs commonly support memory-management units, virtual memory, sophisticated caches, high-speed external memory, and operating systems such as Linux or Android. They are appropriate for gateways, multimedia systems, industrial human-machine interfaces, networking equipment, and edge-computing platforms.

The greater flexibility of an MPU introduces additional design complexity. External memory interfaces consume board area and energy, boot software is more elaborate, and cache and operating-system behavior can reduce timing determinism.

1.3 Digital Signal Processors

A DSP is optimized for repetitive numerical operations such as filtering, Fourier transforms, modulation, demodulation, image processing, and audio coding. Its architecture may include hardware multiply-accumulate units, multiple data memories, circular addressing, bit-reversed addressing, saturation arithmetic, and single-instruction multiple-data (SIMD) operations.

DSP performance is often described by the number of multiply-accumulate operations completed per second, but this metric is meaningful only when the workload maps efficiently to the DSP instruction set and memory system. A general-purpose CPU with SIMD extensions may outperform a DSP on irregular algorithms, while a DSP may provide superior energy efficiency for steady streaming workloads.

1.4 Heterogeneous and Application-Specific Architectures

A heterogeneous system combines different processing elements. For example, a real-time microcontroller core may control a motor, a high-performance application core may run a user interface, and a neural accelerator may classify sensor data. Field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), GPUs, and neural-processing units can provide high throughput for parallel workloads.

The cost of heterogeneity is software and system complexity. Data movement, shared-memory coherence, synchronization, tool-chain maturity, thermal design, and functional safety must be addressed explicitly.

2. Architectural Abstraction: ISA and Microarchitecture

The instruction-set architecture (ISA) is the programmer-visible contract between software and hardware. It specifies registers, instruction formats, data types, addressing modes, memory access rules, exception behavior, privilege levels, and often atomic and synchronization operations. Examples include ARM, RISC-V, x86, and specialized DSP ISAs.

Microarchitecture is the internal implementation of an ISA. Two processors may execute the same ISA but differ substantially in pipeline depth, cache capacity, branch prediction, execution width, clock frequency, and power consumption. This distinction permits software portability while allowing semiconductor vendors to optimize hardware.

2.1 RISC and CISC Considerations

Reduced instruction-set computer (RISC) designs traditionally emphasize a relatively regular instruction format, load/store operation, and a large role for compiler optimization. Complex instruction-set computer (CISC) designs provide more elaborate instructions and addressing modes. Contemporary processors blur this distinction: many CISC processors internally translate instructions into simpler micro-operations, while modern RISC processors include complex extensions.

The practical selection question is not whether RISC or CISC is universally superior. Relevant criteria include code density, compiler quality, interrupt behavior, hardware complexity, licensing, ecosystem, verification effort, and energy per task.

2.2 Registers, Datapath, and Control

The datapath contains registers, arithmetic logic units (ALUs), multipliers, shifters, floating-point units, and interconnection paths. The control unit decodes instructions and coordinates datapath activity. A typical instruction sequence involves fetch, decode, operand read, execute, memory access, and write-back, although not every processor exposes these stages separately.

Status registers record conditions such as zero, negative, carry, and overflow. Correct interpretation of signed and unsigned arithmetic is essential. For example, unsigned overflow and signed two's-complement overflow are different conditions and may require different status flags.

2.3 Privilege, Exceptions, and Protection

A protected processor distinguishes at least privileged and unprivileged execution. Privileged code can configure memory protection, interrupts, clocks, and peripheral access; application code is restricted. Exceptions include reset, faults, system calls, and hardware interrupts. A memory-protection unit (MPU) enforces region-based access rules, whereas a memory-management unit (MMU) translates virtual addresses and supports virtual memory.

Protection mechanisms improve robustness but do not automatically make software secure. Correct configuration, secure boot, authenticated updates, key protection, and isolation of peripheral access are also required.

3. Performance and Energy Models

Processor performance depends on instruction count, cycles per instruction, and clock period. A useful model is

CPU time = IC × CPI × T_cycle = (IC × CPI) / f

where IC is the number of executed instructions, CPI is average cycles per instruction, T_cycle is clock period in seconds, and f is clock frequency in hertz. The relationship assumes that the measured workload and operating conditions are fixed. CPI is an average; individual instructions may require different numbers of cycles because of memory stalls, branches, or contention.

For two implementations executing the same workload, speedup is

Speedup = execution time of baseline / execution time of improved system.

Increasing frequency does not necessarily yield proportional speedup because memory latency, branch penalties, synchronization, and I/O may dominate. Likewise, reducing instruction count can increase performance only if the replacement instructions do not introduce greater latency or memory traffic.

Dynamic switching power is commonly approximated by

P_dynamic ≈ α C V² f,

where α is activity factor, C is effective switched capacitance, V is supply voltage, and f is switching frequency. This approximation describes dynamic power under specified activity and circuit conditions; it excludes leakage, short-circuit power, regulator losses, and peripheral power. Reducing voltage is especially effective, but voltage reduction may lower maximum frequency and impair noise margins.

Energy for a task is

E_task = ∫ P(t)dt.

If power is approximately constant during execution, E_task ≈ P × t. A slower mode can consume less total energy if its reduction in power exceeds the increase in execution time; however, leakage and static power can reverse this conclusion. Energy must therefore be measured over the complete duty cycle, including sleep, wake-up, communication, and peripheral activity.

Worked Example: Architecture Comparison

An application executes 120 million instructions. Processor A has CPI = 1.5 at 600 MHz. Processor B has CPI = 1.0 at 400 MHz. Ignoring memory and I/O differences:

For A, time = (120 × 10⁶ × 1.5)/(600 × 10⁶) = 0.30 s.

For B, time = (120 × 10⁶ × 1.0)/(400 × 10⁶) = 0.30 s.

Thus, neither processor is faster for this workload. If A consumes 1.8 W during execution and B consumes 1.0 W, their task energies are 0.54 J and 0.30 J, respectively. B is preferable when throughput is sufficient and energy is the dominant criterion. The conclusion would change if B lacked a required peripheral or failed a deadline during memory contention.

4. Pipelining and Instruction-Level Parallelism

Pipelining overlaps instruction stages. In an ideal pipeline with k stages, after filling, approximately one instruction may complete per clock cycle. The ideal speedup over a non-pipelined implementation approaches k only under assumptions of balanced stages, independent instructions, uninterrupted instruction supply, and negligible pipeline overhead. Real speedup is lower because of hazards and stage imbalance.

A structural hazard occurs when two operations require the same hardware resource. A data hazard occurs when instructions depend on one another. A control hazard arises from branches, exceptions, and interrupts. Forwarding, interlocks, compiler scheduling, delayed branches, and speculation are techniques for reducing these penalties.

Branch prediction improves average throughput but can reduce timing predictability. A mispredicted branch requires discarded work and incurs a penalty related to pipeline depth. In hard real-time systems, worst-case execution time (WCET), rather than average benchmark performance, is the principal concern. A small, predictable core can therefore be preferable to a faster speculative processor.

Superscalar processors issue multiple instructions per cycle when dependencies and functional resources permit. Out-of-order execution hides latency by executing ready instructions before older stalled instructions. These techniques improve average performance but complicate WCET analysis, introduce speculative side channels, and increase verification and energy costs.

5. Memory Hierarchy and Consistency

The memory hierarchy exploits locality. Temporal locality means recently used data or instructions are likely to be used again; spatial locality means nearby addresses are likely to be accessed. Registers are fastest and smallest, followed by tightly coupled memory, caches, SRAM, DRAM, nonvolatile memory, and external storage. Lower levels usually provide greater capacity but higher latency and energy per access.

A cache stores copies of memory blocks. A cache hit is served from the cache; a miss requires fetching the block from a lower level. Important policies include direct mapping, set associativity, replacement policy, write-through versus write-back, and write-allocate versus no-write-allocate.

Average memory access time can be represented as

AMAT = hit time + miss rate × miss penalty.

For multiple levels, the second-level miss penalty applies only after an L1 miss, so the expression must be extended conditionally. The formula assumes stable average rates and is not a substitute for worst-case timing analysis.

Caches create coherency issues when DMA or multiple cores access shared data. A DMA engine may update memory while a processor retains an old cache line. Solutions include cache-coherent interconnects, cache maintenance operations, non-cacheable buffers, ownership protocols, and carefully designed synchronization. Volatile declarations do not by themselves guarantee atomicity, ordering, or cache coherence.

Memory consistency defines the permitted order in which reads and writes become visible to processors and devices. Barriers or fences are required when software must enforce ordering, especially around device registers, lock-free algorithms, and DMA descriptors.

6. Buses, Interconnects, and Memory-Mapped I/O

A bus or interconnect transports addresses, data, control information, and sometimes explicit transaction attributes such as security or privilege. Traditional shared buses are simple but may become bottlenecks. Modern systems use hierarchical or network-on-chip interconnects with arbitration, independent read and write channels, burst transfers, quality-of-service mechanisms, and multiple masters.

Bandwidth is the amount of data transferred per unit time. A simplified peak bandwidth expression is

Bandwidth = data transferred per transfer × transfers per second.

Actual sustained bandwidth is lower because of protocol overhead, arbitration, refresh, turnaround cycles, alignment, contention, and idle periods.

In memory-mapped I/O, peripheral registers occupy addresses in the processor's address space. Loads and stores then access devices using ordinary instructions, although device regions must have appropriate ordering and caching attributes. A status register may be read-only, a control register may be write-only, and some registers have side effects such as clearing an interrupt on read. Software must follow the peripheral specification exactly.

Port-mapped I/O uses a separate I/O address space and specialized instructions, but memory-mapped I/O is dominant in many contemporary embedded architectures because it simplifies programming and address decoding.

7. Interrupts, Exceptions, and Real-Time Behavior

An interrupt is an asynchronous request that causes the processor to suspend normal execution and enter an interrupt-service routine (ISR). Exceptions are synchronous events associated with the current instruction, such as an illegal operation or memory fault. A typical interrupt sequence saves necessary context, identifies the source, executes the ISR, clears or acknowledges the source, and returns to the interrupted program.

Important timing quantities include interrupt latency, ISR execution time, response time, and jitter. Interrupt latency includes recognition, completion or interruption of the current operation, context entry, and vector dispatch. It varies with masking, higher-priority ISRs, bus contention, cache state, and critical sections.

Good ISR practice is to perform only urgent, bounded work: capture time-critical data, acknowledge the peripheral, place an event in a queue, and defer substantial processing to a task. Shared data requires atomic operations or synchronization. Priority inversion can occur when a high-priority task waits for a lock held by a lower-priority task; priority inheritance or ceiling protocols can mitigate it.

Polling is simpler and sometimes more deterministic, but it wastes processor cycles when events are infrequent. Interrupts improve responsiveness and energy efficiency, although excessive interrupt rates can overload the CPU. Event aggregation, DMA, and hardware filtering often provide better solutions.

8. Direct Memory Access

DMA transfers data between a peripheral and memory, or between memory regions, with limited processor involvement. A typical transaction uses a descriptor containing source address, destination address, length, direction, and control attributes. DMA is valuable for high-rate ADC samples, network frames, audio streams, display buffers, and storage transfers.

DMA does not eliminate cost; it consumes bus bandwidth, descriptor memory, interrupt service time, and sometimes cache-maintenance operations. A correct design must specify buffer ownership. For a non-coherent cache, software may clean cache lines before a device reads memory and invalidate lines after a device writes memory. Alignment and buffer boundaries must be handled carefully.

Circular and double-buffered DMA allow continuous streaming. In double buffering, one buffer is processed while the other is filled. The processing time must fit within the time required to fill the alternate buffer; otherwise data loss occurs. This is a system-level deadline, not merely a processor-speed issue.

9. Selecting an Architecture: A Decision Framework

Architecture selection begins with requirements rather than a preferred processor brand. Requirements should include:

• computational workload and peak-to-average ratio;
• hard, firm, or soft real-time deadlines;
• memory capacity, code size, and data bandwidth;
• analog, timer, communication, security, and control peripherals;
• operating-system and software-ecosystem needs;
• energy budget and thermal limits;
• safety integrity, cybersecurity, and update requirements;
• unit cost, development cost, certification effort, and product lifetime;
• supply-chain resilience and component availability.

A useful process is to eliminate architectures that fail mandatory constraints, then compare surviving alternatives using weighted criteria. Measurements should use representative workloads, worst-case traffic, realistic compiler settings, and required peripherals. Marketing peak frequency is insufficient.

MCUs are often favored for deterministic control, low power, low bill of materials, and integrated peripherals. MPUs are favored for rich user interfaces, networking, large software stacks, and high data processing. DSPs or accelerators are favored when a stable numerical kernel dominates. Heterogeneous designs are justified when workload classes differ significantly and the added integration complexity is acceptable.

Cost includes nonrecurring engineering, software porting, tools, certification, board layers, memory components, power management, and maintenance—not only semiconductor price. Energy decisions should use energy per completed function and lifetime duty cycle, not only active power.

10. Illustrative Case Study: Industrial Predictive-Maintenance Node

Background

Consider an illustrative industrial sensor node attached to a rotating machine. It samples three vibration channels, detects abnormal spectral components, records events, and communicates summaries over an industrial network. The node must operate for five years from a constrained power source and must detect a fault within 100 ms.

Problem

A high-end MPU offers excellent spectral-processing throughput and a mature Linux ecosystem, but it requires external DRAM, consumes substantial idle power, and has less predictable interrupt and cache behavior. A low-power MCU has integrated ADCs, timers, DMA, and deterministic control, but limited floating-point performance and memory.

Analysis

The vibration stream is periodic and amenable to DMA. Sampling can be triggered by a timer, with ADC results transferred into ping-pong buffers. The MCU can perform fixed-point filtering and a reduced spectral feature extraction algorithm. A communication coprocessor or low-power radio can transmit only extracted features. If local processing is insufficient, an accelerator or DSP extension can be added without moving the entire system to an MPU.

The 100 ms requirement is a response deadline, not simply a throughput target. The design team must measure ADC acquisition, DMA transfer, feature extraction, fault classification, communication, and worst-case interrupt interference. Cacheless tightly coupled memory may simplify timing analysis. A secure bootloader and authenticated firmware update are required because a compromised node could falsify maintenance data or become a path into the industrial network.

Approach and Expected Outcome

The selected architecture is an MCU with an integrated ADC, timer-triggered DMA, DSP instructions, memory protection, secure boot support, and a low-power sleep mode. Double buffering permits acquisition and processing to overlap. The processor wakes for each buffer, computes features, and returns to sleep. An MPU remains a future option if the product later requires a graphical interface or complex local analytics.

Learning Points

The lowest-frequency processor is not automatically the lowest-energy choice, and the highest-performance processor is not automatically the best real-time choice. Peripheral integration, data movement, software complexity, security, and lifecycle cost can dominate CPU benchmarks. Architecture should be selected from measured end-to-end requirements.

11. Challenges, Safety, Security, and Governance

Embedded failures can create physical harm. Automotive, medical, aerospace, and industrial applications may require standards such as ISO 26262, IEC 61508, IEC 62304, or DO-178C, depending on sector and product role. Compliance is not achieved by choosing a particular processor; it requires traceability, hazard analysis, verification, configuration management, and controlled change.

Security threats include insecure boot, debug-port exposure, firmware substitution, speculative side channels, fault injection, buffer overflows, and supply-chain compromise. Hardware roots of trust, cryptographic accelerators, secure key storage, least privilege, memory isolation, signed updates, and vulnerability response processes reduce risk. Security controls must be balanced against latency, silicon area, energy, and maintainability.

AI accelerators introduce additional concerns: model integrity, data provenance, explainability in safety decisions, memory bandwidth, thermal behavior, and update governance. An AI classifier should not silently replace a safety mechanism whose behavior cannot be bounded or validated.

12. Contemporary Developments and Best Practices

Current embedded platforms increasingly integrate RISC-V customization, Arm-based heterogeneous cores, chiplet and system-in-package technologies, real-time virtualization, secure enclaves, coherent accelerators, and energy-aware scheduling. Tiny machine learning brings inference to MCUs, but model compression and memory movement often matter more than arithmetic throughput.

Best practices include:

1. Define deadlines, workload distributions, and worst-case conditions before selecting hardware.

2. Measure complete systems, including memory, peripherals, DMA, operating-system overhead, and communication.

3. Separate safety-critical and noncritical functions through hardware and software isolation.

4. Document cache, memory-ordering, interrupt, and DMA assumptions.

5. Use static analysis, profiling, WCET analysis where required, fault injection, and hardware-in-the-loop testing.

6. Design for secure boot, authenticated updates, debug control, and end-of-life support from the beginning.

7. Select components with credible supply continuity and tool-chain support.

Chapter Summary

Embedded computer architecture is the coordinated design of processor cores, instruction sets, pipelines, memory systems, buses, peripherals, interrupts, DMA, and protection mechanisms. MCUs provide integration and determinism; MPUs provide operating-system capability and high application performance; DSPs and accelerators excel at structured numerical workloads. Performance depends on instruction count, CPI, frequency, memory behavior, and parallelism, while energy depends on voltage, activity, leakage, execution time, and duty cycle. Caches and speculation improve average performance but complicate timing and coherency. Interrupts and DMA enable responsive, efficient data movement but require careful ownership, ordering, and worst-case analysis. Architecture selection must balance performance, cost, energy, real-time behavior, safety, security, software ecosystem, and product lifetime. The best architecture is the one that satisfies measured system requirements with acceptable technical and business risk.

Key Terms

Instruction-set architecture: Programmer-visible specification of instructions, registers, memory behavior, and exceptions.

Microarchitecture: Internal hardware implementation of an ISA.

Microcontroller: Integrated processor, memory, peripherals, and control functions on one chip.

Microprocessor: General-purpose processor typically supported by external memory and peripherals.

DSP: Processor optimized for repetitive numerical and signal-processing operations.

Pipeline: Overlapped sequence of instruction-processing stages.

Hazard: Condition that prevents an instruction pipeline from proceeding ideally.

CPI: Average number of clock cycles required per executed instruction.

Cache: Small, fast memory holding copies of recently accessed data or instructions.

AMAT: Average memory access time, including hit time and miss effects.

Memory-mapped I/O: Peripheral registers assigned addresses in the processor address space.

Interrupt: Asynchronous event that requests processor service.

Exception: Synchronous event caused by instruction execution or protection rules.

DMA: Hardware mechanism for transferring data with limited CPU intervention.

Memory barrier: Operation that constrains ordering or visibility of memory accesses.

WCET: Upper-bound execution time under defined system conditions.

MPU: Memory-protection unit enforcing access permissions on memory regions.

MMU: Memory-management unit translating virtual addresses and enforcing protection.

Priority inversion: High-priority activity delayed by lower-priority activity holding a resource.

Heterogeneous processor: System combining different processor types or specialized accelerators.

Review Questions

Short Answer Questions

1. Distinguish a microcontroller from a microprocessor.

2. What is the difference between ISA and microarchitecture?

3. Define a cache miss and explain why it affects execution time.

4. What is the purpose of DMA?

5. Why is WCET important in hard real-time systems?

Long Answer Questions

1. Explain the principal architectural differences among MCUs, MPUs, DSPs, and heterogeneous processors.

2. Discuss pipeline hazards and the techniques used to reduce their performance impact.

3. Explain cache organization, write policies, and DMA-related coherency problems.

4. Analyze the advantages and limitations of interrupts compared with polling.

5. Develop a processor-selection framework incorporating performance, cost, energy, security, and lifecycle factors.

Analytical / Application Questions

1. A processor executes 80 million instructions with CPI 1.25 at 400 MHz. Calculate execution time and explain which additional factors could make the real time larger.

2. Design a DMA-based double-buffering strategy for a continuous sensor stream. State the buffer-ownership and cache-coherency rules that software must follow.

3. Select between an MCU and an MPU for a battery-powered industrial node requiring deterministic control, occasional networking, and authenticated firmware updates. Justify the decision and identify conditions that could reverse it.

Multiple Choice Questions with Answers

Question 1

Which characteristic most strongly distinguishes a microcontroller from a typical microprocessor?

A. The microcontroller integrates processor, memory, and peripherals on one chip

B. The microcontroller cannot execute interrupts

C. The microprocessor always lacks caches

D. The microprocessor is restricted to one application

Correct Answer: A. The microcontroller integrates processor, memory, and peripherals on one chip

Question 2

For a fixed workload, CPU time is correctly expressed as:

A. IC × CPI × clock frequency

B. IC × CPI ÷ clock frequency

C. CPI ÷ IC × clock frequency

D. Clock frequency ÷ (IC × CPI)

Correct Answer: B. IC × CPI ÷ clock frequency

Question 3

Which event is a control hazard?

A. Two instructions require the same ALU

B. An instruction depends on a preceding load

C. A branch outcome changes the next instruction address

D. A register contains a signed negative value

Correct Answer: C. A branch outcome changes the next instruction address

Question 4

What is the principal purpose of DMA?

A. To translate virtual addresses

B. To transfer data with limited processor intervention

C. To predict conditional branches

D. To increase instruction-set size

Correct Answer: B. To transfer data with limited processor intervention

Question 5

In the simplified dynamic-power model P ≈ αCV²f, which change generally has the strongest direct effect on reducing dynamic power?

A. Increasing voltage

B. Reducing voltage

C. Increasing switching activity

D. Increasing frequency

Correct Answer: B. Reducing voltage

Question 6

Which statement about memory-mapped I/O is correct?

A. Peripheral registers are assigned addresses in the processor address space

B. Peripherals can be accessed only through floating-point instructions

C. It eliminates the need for interrupt controllers

D. It guarantees that all accesses are cacheable

Correct Answer: A. Peripheral registers are assigned addresses in the processor address space

Question 7

Why can cache coherence be a problem when DMA is used with a processor?

A. DMA changes the instruction set

B. The processor cache may contain stale data relative to main memory

C. DMA prevents all interrupts

D. Caches cannot store peripheral data

Correct Answer: B. The processor cache may contain stale data relative to main memory

Question 8

Which metric is most relevant when proving that a hard real-time deadline will always be met?

A. Average benchmark score only

B. Peak clock frequency only

C. Worst-case execution time and system response bounds

D. Cache capacity without workload information

Correct Answer: C. Worst-case execution time and system response bounds

Question 9

A system executes 120 million instructions at CPI 1.5 and 600 MHz. What is the idealized execution time?

A. 0.03 s

B. 0.20 s

C. 0.30 s

D. 3.00 s

Correct Answer: C. 0.30 s

Question 10

Which architecture is generally most suitable for a repetitive, numerically intensive filtering workload?

A. DSP with multiply-accumulate support

B. Minimal timer-only controller

C. Storage controller without computation units

D. Unclocked passive interface

Correct Answer: A. DSP with multiply-accumulate support