FPGA, SoC and Heterogeneous Embedded Platforms

Introduction and Context

Embedded systems have evolved from single-purpose microcontrollers into heterogeneous computing platforms that combine general-purpose processors, digital signal processors (DSPs), graphics or AI engines, programmable logic, dedicated accelerators, memory hierarchies, and high-speed communication interfaces. This evolution is driven by applications such as autonomous vehicles, software-defined radio, medical imaging, industrial machine vision, aerospace control, and edge artificial intelligence.

The central design question is no longer simply which processor is fastest. It is how computation should be partitioned among software, programmable hardware, and fixed-function hardware while satisfying performance, energy, cost, reliability, development-time, and certification constraints.

An application may contain sequential control, highly parallel numerical kernels, real-time signal-processing pipelines, and irregular algorithms. No single technology is optimal for all these workloads. CPUs provide flexibility and strong control-flow performance; DSPs efficiently execute regular numerical operations; GPUs offer massive data parallelism; FPGAs provide configurable spatial computation and deterministic timing; ASICs deliver the highest efficiency when volume and requirements justify non-recurring engineering cost. Modern systems-on-chip (SoCs) integrate several of these resources in one device.

This chapter develops a framework for evaluating these technologies and designing heterogeneous embedded platforms. It also introduces hardware-description-language (HDL) concepts, programmable-logic architectures, hardware acceleration, hardware–software partitioning, and practical design trade-offs.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Compare CPU, DSP, GPU, FPGA, ASIC, multicore SoC, and heterogeneous architectures.

2. Explain the structure and design implications of programmable logic.

3. Interpret fundamental HDL concepts including concurrency, clocked processes, synthesis, and timing constraints.

4. Estimate acceleration, throughput, latency, and energy implications of hardware offload.

5. Apply hardware–software partitioning principles to compute-intensive embedded applications.

6. Analyze memory bandwidth, communication overhead, determinism, and reconfiguration constraints.

7. Evaluate an embedded-platform architecture for performance, safety, security, cost, and lifecycle considerations.

1. Processing Technologies and Their Design Positions

1.1 CPU-based embedded systems

A central processing unit executes instructions sequentially, although superscalar issue, pipelining, branch prediction, SIMD extensions, and multicore execution may create substantial internal parallelism. CPUs are particularly effective for operating systems, communication stacks, dynamic control flow, configuration, exception handling, and algorithms whose structure changes frequently.

Their main advantages are software flexibility, mature tools, extensive libraries, and relatively low development effort. Their limitations include instruction-fetch overhead, nondeterministic execution caused by caches and operating-system activity, and lower energy efficiency for highly repetitive arithmetic kernels.

1.2 Digital signal processors

DSPs are specialized processors optimized for multiply–accumulate operations, vector arithmetic, circular buffering, saturation arithmetic, and predictable streaming data movement. They are effective for filtering, modulation, spectral analysis, motor control, and audio processing. Compared with a general-purpose CPU, a DSP usually offers better numerical throughput per watt for regular signal-processing workloads, while retaining software programmability.

A DSP is not automatically superior to a CPU or FPGA. Performance depends on data movement, instruction-set suitability, memory organization, compiler quality, and the degree of algorithmic regularity.

1.3 Graphics processing units

GPUs contain many arithmetic units intended to execute thousands of similar operations concurrently. They are well suited to matrix operations, image processing, neural-network inference, and simulation. Their performance depends strongly on occupancy, coalesced memory access, arithmetic intensity, and the ability to tolerate or hide memory latency.

GPU execution is often less attractive when workloads are small, irregular, strongly sequential, or subject to strict worst-case latency requirements. Data-transfer overhead between CPU and GPU memories can dominate execution time in embedded systems.

1.4 Application-specific integrated circuits

An ASIC implements a fixed hardware design in silicon. It can provide excellent performance, area efficiency, energy efficiency, and high-volume unit cost. However, design verification, mask generation, fabrication, and post-production correction are expensive and time-consuming. ASICs are therefore appropriate when requirements are stable, production volume is high, and the performance or energy target cannot be met economically by programmable devices.

ASIC design also carries technological risk. A functional error discovered after fabrication may require a costly redesign. Security vulnerabilities and changing standards can create similar risks.

1.5 Field-programmable gate arrays

An FPGA is a reconfigurable digital device containing configurable logic blocks, programmable routing, input/output resources, clock-management circuits, and often embedded memories, DSP slices, processors, and high-speed transceivers. Rather than executing a sequence of instructions, an FPGA implements a spatial data path. Independent operations can occur concurrently in different hardware resources.

FPGAs provide a useful middle ground: they approach application-specific hardware efficiency while preserving post-manufacture programmability. Their disadvantages include higher design complexity than software, significant routing and configuration overhead, lower energy efficiency than a well-optimized ASIC, and timing closure challenges.

1.6 Multicore and heterogeneous SoCs

An SoC integrates processor cores, memory controllers, interconnects, peripherals, accelerators, and sometimes FPGA fabric on one device. A heterogeneous SoC may include application-class CPU cores, real-time CPU cores, DSPs, GPUs, neural-processing units, and programmable logic.

Integration reduces board-level interconnect distance and can improve bandwidth and energy efficiency. It also creates system-level challenges: shared-memory contention, cache coherency, interrupt prioritization, isolation, thermal management, secure boot, and software coordination.

2. A Comparative Evaluation Framework

Technology selection should be based on workload and system constraints rather than on peak arithmetic performance alone. Important dimensions are:

• Performance: average throughput, response time, and worst-case latency.
• Determinism: predictability of execution and timing.
• Energy efficiency: energy per operation or per processed sample.
• Flexibility: ease of modifying algorithms after deployment.
• Development cost: tools, verification, engineers, intellectual property, and schedule.
• Unit cost: silicon, memory, packaging, and board cost at the intended production volume.
• Reliability and safety: fault tolerance, diagnostics, isolation, and certification evidence.
• Security: secure boot, bitstream protection, trusted execution, and resistance to fault injection.
• Lifecycle: availability, obsolescence risk, maintainability, and field update capability.

A CPU commonly ranks high in flexibility and low in specialized energy efficiency. An ASIC ranks high in efficiency and low in flexibility. FPGA and heterogeneous SoC solutions occupy intermediate positions, but their actual position depends on design quality and workload mapping.

A useful economic model is the total cost of ownership:

\[

C_{total}=C_{NRE}+N C_{unit}+C_{software}+C_{verification}+C_{maintenance},

\]

where \(C_{NRE}\) is non-recurring engineering cost, \(N\) is production volume, \(C_{unit}\) is per-unit hardware cost, and the remaining terms represent development and lifecycle costs. This simplified model assumes costs are measured over the same lifecycle and excludes financing effects. It illustrates why a high-NRE ASIC may become attractive at large volume, whereas an FPGA or processor-based solution may be preferable for small or uncertain markets.

3. FPGA Architecture and Programmable Logic

3.1 Configurable logic blocks

A typical FPGA logic element includes a lookup table (LUT), a flip-flop, multiplexers, and fast carry circuitry. A LUT implements a Boolean function by storing the truth-table output for each input combination. For an \(n\)-input LUT, up to \(2^n\) truth-table entries are stored, although larger functions are constructed by combining LUTs.

Flip-flops store state and normally update on a clock edge. Carry chains accelerate addition, subtraction, comparison, and address generation. The logic element is therefore capable of both combinational computation and sequential storage.

3.2 Routing and clock resources

Programmable routing connects logic blocks, memories, DSP slices, and I/O pins. Routing delay can exceed logic delay, especially for long or congested paths. Dedicated clock networks distribute clock signals with controlled skew. Clock management units can generate related frequencies and phases, but multiple clock domains require careful synchronization.

3.3 Embedded memories and DSP slices

Block RAMs provide compact synchronous storage for buffers, coefficient tables, FIFOs, and line memories. Distributed RAM may be implemented using LUTs for smaller structures. DSP slices generally contain multipliers, adders, accumulators, and pipeline registers. Mapping arithmetic to dedicated DSP blocks usually improves speed and resource efficiency compared with constructing multipliers from general LUTs.

3.4 Hard processors and transceivers

Many modern FPGAs include hard processor subsystems, memory controllers, Ethernet interfaces, PCI Express interfaces, analog components, and serial transceivers. These resources support processor–FPGA systems in which software manages configuration and communication while programmable logic performs deterministic acceleration.

4. HDL Concepts and Synthesizable Design

Hardware description languages such as VHDL and Verilog/SystemVerilog describe structure and behavior. Unlike ordinary sequential software, HDL describes hardware that operates concurrently.

A combinational HDL block produces outputs from current inputs. It must assign every output for every possible input condition; otherwise synthesis may infer a latch. A sequential block models state updated by a clock edge. A typical register-transfer-level (RTL) description consists of registers, combinational logic between registers, and explicit clock and reset behavior.

For a synchronous path, the maximum clock frequency is constrained approximately by

\[

T_{clk} \ge t_{cq}+t_{logic}+t_{setup}+t_{skew}+t_{uncertainty},

\]

where \(t_{cq}\) is clock-to-output delay of the launching flip-flop, \(t_{logic}\) is combinational-path delay, \(t_{setup}\) is receiving-flip-flop setup time, and the final terms account for clock skew and design uncertainty. The relationship applies to a single synchronous path with a common timing model; input/output delays, clock-domain crossings, and multicycle paths require additional constraints.

Pipelining inserts registers into a long combinational path. It can increase maximum frequency and throughput, but it also increases latency, register usage, control complexity, and possibly power. A pipeline with initiation interval one can accept one new data item per clock after filling, even though the result may emerge several cycles later.

4.1 Clock-domain crossing

Signals crossing between asynchronous or unrelated clock domains cannot be sampled directly without risk of metastability. A single-bit control signal is commonly synchronized using two cascaded flip-flops. Multi-bit data should use an asynchronous FIFO, handshake protocol, or another formally designed CDC mechanism. Synchronizers reduce metastability propagation probability but do not eliminate the physical phenomenon.

4.2 Synthesis and implementation flow

A conventional FPGA flow includes specification, algorithm modeling, RTL coding, simulation, synthesis, technology mapping, placement, routing, static timing analysis, bitstream generation, hardware validation, and, where necessary, formal verification. Simulation checks functional behavior; timing analysis checks whether constrained paths meet requirements. Neither alone proves complete correctness.

5. Hardware Acceleration and Partitioning

Hardware acceleration maps selected computational kernels to a specialized engine while leaving control-oriented functions in software. Good candidates often have high execution frequency, regular data access, substantial arithmetic intensity, and limited dependence on unpredictable branches.

Amdahl’s law gives an upper bound on speedup when only part of an application is accelerated:

\[

S=\frac{1}{(1-p)+p/s},

\]

where \(p\) is the fraction of original execution time affected by acceleration and \(s\) is the speedup of that fraction. This assumes the fractions are measured in the baseline execution and that other overheads are represented separately or negligible. If transfer and synchronization overhead are significant, a more realistic expression is

\[

S=\frac{T_{base}}{(1-p)T_{base}+(pT_{base}/s)+T_{overhead}}.

\]

The formula emphasizes that accelerating a small fraction of execution cannot produce large system-level gains.

Worked Example: Assessing an Accelerator

Suppose a workload requires 100 ms on a CPU. A matrix-processing kernel accounts for 70% of this time. An FPGA accelerator makes that kernel 20 times faster, but data movement and synchronization add 4 ms.

The non-accelerated time is 30 ms. The accelerated kernel takes \(70/20=3.5\) ms. Therefore,

\[

T_{new}=30+3.5+4=37.5\text{ ms}.

\]

The total speedup is

\[

S=100/37.5\approx2.67.

\]

Although the kernel itself is 20 times faster, application speedup is only about 2.67 because 30% of execution remains on the CPU and the interface overhead is significant.

5.1 Streaming versus memory-mapped acceleration

A streaming accelerator consumes and produces data through FIFOs or streams. It is appropriate for pipelines such as filtering, feature extraction, and video processing. Streaming can reduce external-memory traffic and provide predictable throughput.

A memory-mapped accelerator reads and writes shared address spaces. It is easier to integrate with software and is suitable for block-based algorithms, but cache coherency, burst efficiency, alignment, and memory contention must be addressed.

5.2 Throughput, latency, and initiation interval

Throughput is the sustained rate of completed work; latency is the time from input acceptance to corresponding output. These measures differ. A deeply pipelined accelerator may have high latency but excellent throughput. Real-time control systems may prioritize bounded latency, whereas image analytics may prioritize aggregate throughput.

For a pipeline accepting one item every \(I\) clock cycles at clock frequency \(f\), the ideal steady-state throughput is

\[

R=\frac{f}{I}

\]

items per second. This assumes the pipeline is continuously supplied, has no stalls, and produces one item per initiation interval.

6. Heterogeneous SoC Architecture

A heterogeneous platform commonly contains:

• application processors running Linux or another rich operating system;
• real-time cores running an RTOS or bare-metal firmware;
• programmable logic or fixed accelerators;
• shared or distributed memory;
• coherent and non-coherent interconnects;
• DMA engines and high-speed peripherals;
• security and power-management subsystems.

A practical partition may assign networking, user interfaces, and scheduling to an application processor; deterministic control loops to a real-time core; and high-rate filtering or vision kernels to programmable logic. Such allocation is not merely a performance decision. It defines fault-containment boundaries, update mechanisms, and verification responsibilities.

6.1 Memory hierarchy and bandwidth

Many accelerator designs fail to meet their theoretical arithmetic rate because memory cannot supply data quickly enough. If an algorithm requires \(B\) bytes per output and produces \(R\) outputs per second, the minimum sustained data bandwidth is

\[

BW_{min}=BR.

\]

This is an ideal lower bound and excludes protocol overhead, burst inefficiency, metadata, cache effects, and read/write duplication.

For example, an image pipeline requiring 8 bytes per pixel at 60 million pixels per second needs at least

\[

8\times60\times10^6=480\text{ MB/s}

\]

of data bandwidth under the stated convention of one megabyte as \(10^6\) bytes. Actual design bandwidth must be higher to accommodate overhead and concurrent traffic.

6.2 Coherency and communication

Cache-coherent sharing simplifies programming because processors observe a consistent memory view, but coherency traffic consumes energy and interconnect bandwidth. Non-coherent DMA can be efficient, but software must explicitly manage cache flush and invalidation operations where required. Incorrect cache maintenance can produce intermittent and difficult-to-reproduce failures.

Interprocessor communication may use shared-memory queues, message passing, interrupts, mailboxes, or hardware FIFOs. The protocol should define ownership, buffering, ordering, timeout behavior, and error recovery.

6.3 Real-time behavior

Average performance is insufficient for hard real-time systems. Designers must establish worst-case execution time, interrupt latency, scheduling interference, memory-access bounds, and accelerator back-pressure behavior. A high-performance cache-based processor may be less suitable than a slower but more predictable engine for a safety-critical control loop.

7. Case Study: Illustrative FPGA–SoC Machine-Vision Platform

Background

The following is an illustrative case. An industrial inspection system must examine 2,000 grayscale images per second. Each image is 1,024 pixels wide and contains a fixed sequence of filtering, edge extraction, connected-component analysis, and decision logic. A network interface transfers results to a factory controller.

Problem

A CPU implementation achieves only 700 images per second at acceptable utilization. Increasing processor frequency would raise power and thermal load. A GPU can provide high average throughput, but the system requires bounded processing time and has limited board power. The design team must select an architecture that supports future algorithm updates.

Analysis

The filtering and edge-extraction stages are regular and stream-oriented. They reuse neighboring pixels and can be implemented as pipelined operations with line buffers. Connected-component analysis contains more irregular memory access and is less naturally represented as a fixed pipeline. Decision logic and network management are control-oriented.

Approach and Solution

The selected platform is a heterogeneous SoC containing application processors and FPGA fabric. The FPGA implements line buffering, convolution, thresholding, and edge extraction. A DMA engine transfers compact feature data to processor memory. The processor performs connected-component analysis, configuration, diagnostics, and networking. Double buffering allows one feature block to be processed while another is transferred.

Timing constraints are applied to all clock domains, and asynchronous FIFOs isolate the sensor clock from the processing clock. Hardware counters measure input stalls, FIFO occupancy, processing latency, and dropped frames. The software includes watchdog supervision and a fallback mode that reduces inspection resolution if the accelerator reports a fault.

Outcome

The architecture meets the target rate with lower processor utilization and more predictable latency than the CPU-only design. The FPGA pipeline is efficient because it avoids repeatedly writing intermediate images to external memory. The processor remains available for algorithm updates and system management. However, verification effort increases because the team must validate RTL, DMA behavior, driver correctness, cache handling, and interactions between hardware and software.

Learning Points

1. Partitioning should follow dataflow and timing requirements, not only instruction count.

2. Local buffering can be more valuable than simply adding arithmetic units.

3. Heterogeneity permits flexible control software alongside deterministic datapaths.

4. Instrumentation and fault handling are essential in deployed accelerators.

5. The interface between hardware and software is a primary source of system risk.

8. Design Challenges and Limitations

Verification complexity

Hardware errors may involve rare timing, reset, CDC, or protocol conditions. Effective practice combines simulation, assertions, formal property checking, constrained-random verification, hardware-in-the-loop tests, and field diagnostics.

Timing closure

A logically correct design may fail to meet timing because of routing congestion, excessive fan-out, poor floorplanning, or cross-domain paths. Timing closure should begin during architecture development rather than after RTL completion.

Power and thermal limits

Dynamic power depends on switching activity, capacitance, voltage, and frequency; static power depends on device technology and temperature. Lowering voltage is especially effective but may reduce timing margin. Clock gating, operand isolation, data reuse, power-aware placement, and workload scheduling can reduce energy.

Partial reconfiguration

Some FPGAs permit a region of logic to be reconfigured while the remainder continues operating. This can reduce hardware resource requirements or support adaptable functions, but it introduces bitstream management, isolation, authentication, timing, and interruption challenges.

Security

The configuration bitstream should be authenticated and, where confidentiality is required, encrypted. Secure boot establishes a chain of trust from immutable hardware through firmware and FPGA configuration. Debug interfaces must be controlled, and accelerators must validate buffer addresses and lengths to prevent unauthorized memory access. Supply-chain risks include counterfeit devices, compromised intellectual property, and malicious hardware modifications.

Safety and governance

Automotive, aerospace, medical, and industrial systems may require evidence under standards such as ISO 26262, IEC 61508, DO-254, or IEC 62304, depending on domain and jurisdiction. Standards do not automatically make a design safe; they provide process and evidence expectations. Requirements traceability, independent review, fault analysis, configuration control, and reproducible builds are essential.

9. Contemporary Developments and Best Practices

Current platforms increasingly combine FPGA fabric with AI engines, high-bandwidth memory, chiplet-based integration, network-on-chip architectures, and domain-specific accelerators. High-level synthesis can generate RTL from C, C++, or OpenCL-like descriptions. It can improve productivity, but it does not remove the need to understand concurrency, memory architecture, fixed-point effects, timing, and verification.

AI inference at the edge creates additional constraints. Quantization can reduce memory and arithmetic cost, but accuracy must be validated for the target data distribution. An accelerator should be evaluated using end-to-end latency and energy, not only operations per second. Security concerns include model extraction, adversarial inputs, poisoned updates, and leakage through shared resources.

Recommended practices include:

• define measurable throughput, latency, energy, and reliability requirements before selecting hardware;
• profile the complete application and identify data movement costs;
• prototype algorithms in software before committing to RTL;
• use fixed-point analysis rather than assuming floating-point equivalence;
• design interfaces, ownership, and error recovery explicitly;
• constrain clocks and CDC paths accurately;
• verify hardware and software together;
• reserve resources for future revisions and diagnostic functions;
• protect configuration data and enforce secure update procedures;
• measure the deployed system under worst-case thermal and traffic conditions.

Chapter Summary

FPGA, ASIC, DSP, GPU, CPU, and heterogeneous SoC technologies occupy different positions in the embedded design space. CPUs maximize flexibility, DSPs efficiently execute regular numerical workloads, GPUs exploit broad data parallelism, ASICs maximize efficiency at the cost of flexibility, and FPGAs implement configurable spatial datapaths with deterministic behavior. Heterogeneous SoCs combine these strengths but introduce interconnect, memory, coherency, timing, security, and verification challenges.

FPGA design is based on concurrent hardware, configurable logic, routing, memories, DSP slices, and clock resources. HDL-based RTL design requires careful distinction between combinational and sequential behavior, explicit timing constraints, safe clock-domain crossing, and a disciplined synthesis-to-verification flow. Hardware acceleration is valuable only when kernel speedup exceeds communication and synchronization overhead. Amdahl’s law demonstrates why whole-application performance depends on the fraction accelerated.

Successful platform design is therefore an exercise in system-level partitioning. Workloads should be assigned according to parallelism, data movement, real-time constraints, flexibility, energy, safety, security, and lifecycle cost. The most effective architectures combine software programmability with carefully selected hardware datapaths and robust interfaces.

Key Terms

FPGA: A field-programmable device whose digital hardware structure can be configured after manufacture.

ASIC: An application-specific integrated circuit designed for a particular function or product.

DSP: A processor optimized for numerical signal-processing operations.

GPU: A massively parallel processor designed primarily for data-parallel computation.

SoC: A system-on-chip integrating processing, memory, interconnect, peripherals, and accelerators.

Heterogeneous computing: Use of different processor and accelerator types in one system.

LUT: A lookup table used in an FPGA to implement combinational Boolean functions.

RTL: Register-transfer-level representation of registers and combinational data paths.

Synthesis: Translation of HDL into an implementation using target hardware resources.

Timing closure: The process of ensuring all constrained paths meet timing requirements.

Clock-domain crossing: Transfer of signals between unrelated or differently timed clocks.

Pipeline: A sequence of processing stages separated by storage elements.

Initiation interval: Number of clock cycles between successive inputs accepted by a pipeline.

DMA: Direct memory access, allowing a peripheral or accelerator to transfer data without continuous CPU intervention.

Cache coherency: Consistency of data views among caches and shared memory.

Hardware acceleration: Use of specialized hardware to execute selected computational tasks.

Partial reconfiguration: Reprogramming part of an FPGA while other regions continue operating.

Amdahl’s law: A relationship limiting total speedup when only part of an application is accelerated.

Bitstream: Configuration data used to program FPGA resources.

Determinism: Predictability of execution time and system behavior.

Review Questions

Short Answer Questions

1. Why are FPGAs described as spatial computing devices?

2. State two advantages and two limitations of ASICs.

3. What is the purpose of a two-flip-flop synchronizer?

4. Distinguish throughput from latency.

5. Why can memory bandwidth limit accelerator performance?

Long Answer Questions

1. Compare CPU, DSP, GPU, FPGA, and ASIC technologies using performance, flexibility, energy, cost, and determinism.

2. Explain the main components of an FPGA and their roles in implementing an RTL design.

3. Discuss hardware–software partitioning in a heterogeneous SoC, including communication and coherency issues.

4. Derive and interpret the synchronous timing constraint for a register-to-register path.

5. Explain the verification, security, safety, and lifecycle challenges of FPGA-based embedded systems.

Analytical / Application Questions

1. An application spends 80% of its time in a kernel accelerated by a factor of 12. If transfer overhead equals 5% of the original execution time, calculate the total speedup and discuss whether further kernel optimization is likely to be valuable.

2. Design a processor–FPGA architecture for a software-defined radio receiver. Justify the allocation of sampling, filtering, demodulation, control, networking, and user-interface functions.

3. A vision accelerator requires 12 bytes of external-memory traffic per output pixel and must process 90 million pixels per second. Calculate the ideal minimum bandwidth and identify at least three reasons why the practical memory requirement will be higher.

Multiple Choice Questions with Answers

Question 1

Which technology generally provides the greatest post-manufacture hardware flexibility?

A. ASIC

B. FPGA

C. Fixed-function DSP

D. Mask-programmed ROM

Correct Answer: B. FPGA

Question 2

A pipeline operates at 200 MHz with an initiation interval of 2 cycles. What is its ideal steady-state throughput?

A. 50 million items/s

B. 100 million items/s

C. 200 million items/s

D. 400 million items/s

Correct Answer: B. 100 million items/s

Question 3

Which workload is most naturally suited to a streaming FPGA pipeline?

A. Highly irregular operating-system scheduling

B. Fixed-rate convolution of sensor samples

C. Interactive command interpretation

D. Large unpredictable pointer-based graph traversal

Correct Answer: B. Fixed-rate convolution of sensor samples

Question 4

In Amdahl’s law, the variable p represents:

A. The clock frequency

B. The fraction of execution time that can be accelerated

C. The number of processors

D. The accelerator power

Correct Answer: B. The fraction of execution time that can be accelerated

Question 5

What is the principal purpose of an asynchronous FIFO?

A. To increase instruction-set size

B. To safely buffer data between unrelated clock domains

C. To encrypt an FPGA bitstream

D. To replace all cache memory

Correct Answer: B. To safely buffer data between unrelated clock domains

Question 6

Which resource is especially appropriate for FPGA multiply–accumulate operations?

A. DSP slice

B. Clock pin only

C. Configuration flash alone

D. JTAG cable

Correct Answer: A. DSP slice

Question 7

An algorithm requires 6 bytes per output and produces 50 million outputs per second. Ignoring overhead, what bandwidth is required?

A. 30 MB/s

B. 300 MB/s

C. 3 GB/s

D. 30 GB/s

Correct Answer: B. 300 MB/s

Question 8

Which statement best distinguishes latency from throughput?

A. Latency is the sustained rate; throughput is response time

B. Latency is response time; throughput is sustained processing rate

C. They always have identical values

D. Latency applies only to software

Correct Answer: B. Latency is response time; throughput is sustained processing rate

Question 9

Why may an FPGA accelerator fail to deliver its theoretical arithmetic performance?

A. The HDL contains no Boolean operations

B. Memory bandwidth or data-transfer overhead may be insufficiently considered

C. FPGAs cannot use registers

D. All FPGA operations are necessarily sequential

Correct Answer: B. Memory bandwidth or data-transfer overhead may be insufficiently considered

Question 10

Which practice is most directly related to secure FPGA deployment?

A. Increasing LUT fan-out

B. Authenticating the configuration bitstream

C. Removing all timing constraints

D. Disabling reset logic

Correct Answer: B. Authenticating the configuration bitstream