Processor and Embedded Computer Architecture

Introduction

An embedded system is a computer-based system designed to perform a defined function within a larger product. In mechatronics, embedded computers connect sensing, computation, communication, and actuation. They appear in motor drives, robot controllers, automotive electronic control units, industrial instruments, medical devices, and consumer products. Unlike a general-purpose desktop computer, an embedded controller is usually designed around constraints of cost, size, power, timing, reliability, and environmental conditions.

The processor architecture determines how rapidly and predictably a controller can execute algorithms, how it accesses memory and peripherals, and how easily it can be integrated into a complete product. Selecting an architecture is therefore an engineering decision, not merely a choice based on clock frequency.

Learning Objectives

After studying this chapter, students should be able to:

• distinguish microcontrollers, microprocessors, systems-on-chip, CPUs, and embedded computers;
• explain buses, address spaces, memory organization, and processor registers;
• describe the instruction-execution cycle and pipelining;
• analyze interrupts, timers, watchdogs, and direct memory access;
• explain ADC and DAC operation and their relevance to mechatronic systems;
• select an architecture using performance, timing, power, cost, safety, and development criteria.

1. Embedded Processor Categories

1.1 CPU, processor, and computer

A central processing unit (CPU) is the datapath and control unit that interprets and executes instructions. It contains an arithmetic logic unit (ALU), registers, an instruction decoder, and control logic. The term processor is often used for a CPU, although in commercial contexts it may include additional components such as caches and memory-management hardware.

An embedded computer includes a processor together with memory, input/output interfaces, power circuitry, software, and often communication hardware. The computer may be a single integrated circuit or a circuit board containing several devices.

1.2 Microcontrollers

A microcontroller unit (MCU) integrates a CPU core, nonvolatile program memory, volatile data memory, timers, communication interfaces, GPIO, and often ADCs, DACs, and PWM units on one chip. This high integration gives an MCU low component count, low cost, and good control of digital and analog I/O.

MCUs are particularly suitable for closed-loop control, battery-operated instruments, appliance control, and safety-related monitoring. Many provide deterministic interrupt response and specialized peripherals that operate without continuous CPU involvement.

Typical limitations include modest memory capacity, limited computational throughput, and less sophisticated operating-system support than a microprocessor-based system.

1.3 Microprocessors

A microprocessor (MPU) generally integrates a high-performance CPU but requires external or separately packaged memory and peripheral devices. MPUs commonly support memory-management units, caches, virtual memory, and operating systems such as Linux. They are appropriate for computer vision, advanced user interfaces, networking, and applications requiring substantial software ecosystems.

An MPU-based design can deliver high performance but normally has greater power consumption, cost, board complexity, boot time, and software-management overhead than a simple MCU.

1.4 Systems-on-chip

A system-on-chip (SoC) integrates several functional subsystems on one semiconductor device. These may include one or more CPUs, GPU or DSP accelerators, memory controllers, communication peripherals, security hardware, and real-time cores. An SoC is not necessarily a microcontroller: some SoCs are designed for rich operating systems and multimedia, while others are highly integrated real-time controllers.

A heterogeneous SoC may contain different processor types. A real-time core can control a motor while an application core performs networking or image processing. This partitioning improves performance but introduces issues of shared memory, synchronization, software partitioning, and verification.

2. Internal Architecture and Buses

2.1 Datapath and control unit

The datapath moves and transforms binary data. Its principal elements are the ALU, registers, shifters, and sometimes floating-point and vector units. The control unit obtains an instruction, decodes its operation and operands, and generates signals that cause the datapath and memory system to perform the operation.

A typical instruction may add two registers, load a value from memory, compare values, or branch to another program location. The instruction set architecture (ISA) defines the programmer-visible instructions, registers, data types, addressing modes, and exception behavior. The microarchitecture is the internal implementation of that ISA, including pipelines, caches, and execution units.

2.2 System buses

A bus is a shared or point-to-point communication structure connecting processing elements, memory, and peripherals. Its conceptual signals include:

• address lines, identifying a storage location or peripheral register;
• data lines, carrying values;
• control signals, specifying read, write, timing, privilege, or transfer type.

If an address bus has n independent binary lines, it can represent up to 2ⁿ distinct addresses. If each address identifies one byte, the maximum directly addressable space is 2ⁿ bytes. The actual usable space may be smaller because of reserved regions, peripheral mappings, or architectural limitations.

A wider data bus can transfer more bits per transfer, but sustainable performance also depends on clock rate, wait states, arbitration, memory latency, and bus protocol. The idealized peak transfer rate of a bus is:

where R_peak is peak bytes per second, W is data width in bits, f is transfer frequency in hertz, and T is transfers per clock cycle. This estimate assumes continuous transfers with no overhead or wait states; real throughput is lower.

Peripheral buses often use memory-mapped I/O. In this arrangement, peripheral registers occupy addresses in the processor address space, so ordinary load and store instructions access them. A write to a timer-control address, for example, may start a timer rather than store data in RAM. Proper register access requires attention to bit fields, read-only status bits, write-one-to-clear flags, and volatile software declarations.

3. Memory Organization

3.1 Memory types

Program memory is commonly flash or ROM. It retains contents when power is removed and therefore stores firmware. RAM stores variables, stacks, buffers, and temporary results but loses data when power is removed. SRAM is fast and predictable; DRAM provides higher density but requires refresh and is common in larger systems.

Nonvolatile data may be stored in EEPROM, flash sectors, FRAM, or external memory. Each technology differs in endurance, write time, density, and energy requirements. Flash usually requires erase operations in blocks, so frequent small updates should use wear leveling or a memory technology designed for high write endurance.

3.2 Address space and memory map

A memory map assigns address ranges to flash, RAM, peripheral registers, external devices, and boot or security regions. A common arrangement places the reset vector and program image in nonvolatile memory, RAM at another range, and peripheral registers in a memory-mapped region.

The stack stores return addresses, saved registers, and local variables. The heap, when used, supports dynamic allocation. In safety-critical and hard real-time systems, dynamic allocation may be restricted because fragmentation and unpredictable allocation time can compromise determinism.

Endianness defines the order in which a multi-byte value is placed in memory. In a little-endian system, the least significant byte occupies the lowest address. In a big-endian system, the most significant byte occupies the lowest address. Endianness matters when exchanging binary data between processors or interpreting communication packets.

3.3 Cache and memory hierarchy

A cache stores recently used memory lines close to the CPU. It reduces average access time when programs exhibit temporal or spatial locality. However, caches make execution time less predictable and create data-coherency issues in systems with DMA or multiple processors. Real-time designers may disable caches for selected regions, lock critical data, use cache-maintenance operations, or select tightly coupled memory.

4. Registers and Instruction Execution

Registers are small, fast storage locations inside the CPU. Important classes include:

• the program counter (PC), holding the address of the next instruction;
• the instruction register, holding the current instruction;
• general-purpose registers, holding operands and results;
• the stack pointer (SP), identifying the active stack area;
• the status or flag register, holding condition codes and control bits;
• link or return-address registers, used by some architectures for subroutine calls.

The instruction cycle consists conceptually of fetch, decode, operand access, execute, and write-back. A simple processor completes these stages sequentially. A pipelined processor overlaps stages for different instructions. Once a pipeline is full, an ideal pipeline with k stages can approach one completed instruction per cycle, but branches, data dependencies, interrupts, and memory stalls reduce this rate.

The average execution time of a program can be represented as:

where T_CPU is CPU execution time, N_I is the number of executed instructions, CPI is average cycles per instruction, and f_clk is clock frequency in hertz. The formula assumes that the average CPI adequately represents stalls and instruction types. Increasing clock frequency is not the only way to reduce time: reducing instruction count or CPI may be more effective.

Worked example

A control routine executes 24,000 instructions. Its average CPI is 2.0 and the processor clock is 48 MHz. Therefore:

This is the processor time under the stated assumptions. It does not automatically equal the complete control-loop period because peripheral waits, interrupt service, bus contention, and operating-system activity may add time.

5. Interrupts and Real-Time Behavior

An interrupt is a hardware or software request that temporarily transfers execution to an interrupt service routine (ISR). Sources include timer events, ADC completion, communication reception, GPIO edges, faults, and watchdog expiry.

A typical sequence is: the processor recognizes a pending interrupt, saves essential context, obtains the vector address, executes the ISR, clears or acknowledges the source, restores context, and resumes the interrupted program. Interrupt priority determines which request is serviced first when several are pending. Some systems permit nesting, but nesting increases analysis complexity.

Interrupt latency is the time from an event becoming eligible for service to execution of the relevant ISR. Latency depends on instruction completion, interrupt masking, higher-priority service, bus delays, and context-saving hardware. Interrupt response must be distinguished from interrupt-service duration. A long ISR can delay other events and should usually perform only urgent work, placing longer processing in a task or main loop.

In a periodic control system, a timer interrupt may trigger sampling and computation. If the sampling period is T_s, the sampling frequency is:

where f_s is in hertz and T_s is in seconds. This relationship applies to uniform periodic sampling. The selected rate must accommodate plant dynamics, computation time, communication, and the requirements of the control algorithm.

6. Timers, PWM, and Watchdogs

A hardware timer counts clock events or an external signal. It can generate periodic interrupts, measure pulse width, capture timestamps, compare events, and produce pulse-width-modulated (PWM) outputs. With timer input clock f_timer, prescaler P, and a period register producing N timer counts, an idealized period is:

This assumes the timer counts exactly N clock ticks and excludes off-by-one conventions, synchronization delays, and clock tolerance. Datasheets must be consulted for the precise register interpretation.

PWM controls average power by varying duty ratio:

where D is dimensionless duty ratio, t_on is high-time, and T is the PWM period. For an ideal unipolar voltage-switching stage feeding a sufficiently filtered load, average output voltage is approximately V_avg ≈ D V_dc. Motor inductance and controller dynamics mean that mechanical speed is not determined by this equation alone.

A watchdog timer resets or otherwise places the system in a safe state if software fails to service it within a configured interval. It protects against deadlock, runaway execution, clock failure, and some classes of memory corruption. A watchdog is not a substitute for fault diagnosis: indiscriminate periodic refreshing can conceal a stalled control task. Best practice is to refresh it only after critical tasks have completed and to record reset causes.

7. Direct Memory Access

Direct memory access (DMA) transfers data between peripherals and memory, or between memory locations, with limited CPU intervention. A DMA channel is configured with source address, destination address, transfer count, direction, width, and increment rules. The DMA controller arbitrates for a bus, performs transfers, and commonly generates an interrupt when a block or half-block is complete.

DMA is valuable for ADC sample streams, communication packets, audio, and display data. It reduces CPU load and improves timing regularity. However, it can compete with the CPU for bus bandwidth. In cached systems, buffers require cache coherency management: data may need to be cleaned before transmission or invalidated before CPU reading. Circular and double-buffered DMA allow one buffer to be processed while another is filled.

8. ADC and DAC Interfaces

An analog-to-digital converter (ADC) maps an input voltage to a digital code. For an ideal N-bit ADC with input range from 0 to V_ref, the nominal code width is:

where q is volts per code. A common ideal quantization model represents the conversion uncertainty as approximately ±q/2, although real accuracy is affected by offset, gain error, integral nonlinearity, noise, reference error, source impedance, and sampling effects. The input must remain within the specified range, and signal conditioning may be required.

For an ideal ADC, a code near integer value C corresponds approximately to:

The exact endpoint convention depends on the ADC architecture and datasheet; the formula is a common approximation for unsigned unipolar converters.

Sampling frequency must be adequate for the signal bandwidth. For a band-limited signal with highest frequency f_max, the Nyquist condition requires f_s > 2 f_max for theoretical alias-free sampling. Practical systems use anti-alias filters and sample substantially faster than the theoretical minimum.

A digital-to-analog converter (DAC) produces an analog output from a digital code. An ideal N-bit unipolar DAC has an approximate step size q = V_ref/(2^N − 1) under an endpoint-scaled model. DAC outputs may require a buffer, reconstruction filter, or power amplifier. PWM followed by filtering is often used as a lower-cost alternative, but ripple and dynamic response must be considered.

Worked ADC example

An ideal 12-bit ADC uses a 3.3 V reference. Its approximate code width is:

If the measured code is 2048, the midpoint approximation gives:

This result is idealized; calibration and electrical noise determine the practical accuracy.

9. Selecting an Architecture

Architecture selection should begin with system requirements rather than processor popularity. Important criteria include:

1. Control timing: maximum interrupt latency, loop period, jitter, and worst-case execution time.
2. Computational workload: integer, floating-point, DSP, machine-vision, cryptographic, or AI acceleration requirements.
3. Memory: program size, RAM buffers, stack depth, nonvolatile data, cache behavior, and external-memory needs.
4. Peripherals: ADC resolution and rate, PWM channels, encoder interfaces, motor-control timers, CAN, Ethernet, USB, SPI, and I²C.
5. Power and thermal design: active, sleep, and standby consumption; heat dissipation; battery constraints.
6. Safety and security: memory protection, secure boot, cryptographic accelerators, diagnostics, lockstep operation, watchdogs, and certification evidence.
7. Cost and supply: unit price, external components, package, availability, longevity, and second-source strategy.
8. Software ecosystem: compiler quality, debugging, RTOS support, drivers, libraries, team expertise, and long-term maintenance.
9. Environmental conditions: temperature, vibration, electromagnetic compatibility, humidity, and radiation exposure.

A low-end MCU is usually preferable when the control problem is bounded, interfaces are modest, and deterministic response is essential. An MPU or application SoC is justified when rich operating systems, high-bandwidth networking, vision, or complex user interfaces dominate. A heterogeneous SoC is attractive when real-time control and high-level computation must coexist, but its partitioning and verification effort are greater.

10. Illustrative Case: Servo Axis Controller

Background

Consider a single-axis industrial positioning module. A brushless motor drives a lead screw, an encoder measures position, and a current sensor protects the power stage. The controller must execute a current loop every 50 μs, a velocity loop every 1 ms, and a position loop every 5 ms. It must also communicate over CAN and detect overcurrent and overtemperature faults.

Problem analysis

The fastest loop requires a 20 kHz update rate. The controller therefore needs timer-triggered ADC sampling, synchronized PWM, rapid interrupt response, encoder capture, and sufficient computation for the control law. Sampling should occur at a repeatable point in the PWM cycle to reduce switching noise. A general-purpose computer running a non-real-time operating system would create unnecessary timing uncertainty.

Approach and solution

A motor-control MCU is selected with a high-speed CPU, multiple synchronized PWM channels, ADCs triggered by timers, encoder interfaces, DMA, CAN, and hardware watchdogs. The ADC transfers current samples to RAM using DMA. A high-priority ISR executes the current controller and updates PWM compare registers. Lower-rate tasks perform velocity and position control. A watchdog is refreshed only after the current-control health flag and communication-monitoring task have completed.

Fault inputs are connected to hardware shutdown circuitry rather than relying solely on software. The system stores reset causes and fault records in protected nonvolatile memory. A separate host computer provides configuration and diagnostics but does not close the fast control loop.

Outcome and learning points

This partition gives deterministic fast control, efficient data movement, and a practical service interface. The case illustrates that peripheral synchronization and fault architecture can be more important than nominal CPU frequency. It also demonstrates a common pattern: a real-time MCU for control, paired with a higher-level processor only when visualization, networking, or advanced analytics require it.

11. Limitations, Safety, and Contemporary Developments

Processor specifications can be misleading when they emphasize peak clock rate without describing memory stalls, peripheral timing, interrupt latency, or worst-case behavior. Benchmarks must represent the intended workload. Analog specifications such as nominal ADC resolution do not guarantee effective number of bits in a noisy installation.

Safety engineering requires hazard analysis, independent protection paths where appropriate, diagnostic coverage, controlled failure modes, and evidence that software and hardware meet applicable standards. Industrial, automotive, medical, and aerospace products may be governed by sector-specific standards. Security requires threat modeling, secure boot, signed updates, access control, key protection, and careful treatment of debug ports.

Contemporary embedded designs increasingly combine real-time control with edge machine learning, time-sensitive networking, virtualization, and hardware security modules. AI accelerators can classify vibration or detect anomalies, but their memory demand, latency variation, explainability, and update governance must be evaluated. A learned model should not silently replace a deterministic safety limit unless the complete safety case supports that decision.

Best practice is to define timing budgets, measure worst-case behavior, document memory maps and register assumptions, use static analysis and hardware-in-the-loop testing, protect critical outputs with independent limits, and select components with credible long-term supply and tool support.

Chapter Summary

Embedded computer architecture links processor organization to the practical requirements of mechatronic products. MCUs integrate CPU, memory, and peripherals for economical deterministic control; MPUs provide higher software and computational capability; SoCs combine multiple processing and specialized subsystems. Buses connect these resources through address, data, and control transfers, while memory maps define how software reaches program storage, RAM, and peripheral registers.

Registers and the instruction cycle explain how programs execute, while CPI, instruction count, and clock frequency provide a useful—though idealized—performance model. Interrupts, timers, PWM, watchdogs, and DMA are central to real-time behavior. ADCs and DACs connect digital computation to physical variables, but resolution, sampling, noise, reference accuracy, and conditioning determine actual performance.

Architecture selection must consider timing determinism, workload, memory, peripherals, power, safety, security, cost, environmental conditions, and software lifecycle. The servo-axis case shows how synchronized peripherals, DMA, hardware protection, and task partitioning can produce a robust controller.

Key Terms

CPU: Central processing unit that executes instructions.

Microcontroller: Integrated processor containing memory and peripherals for embedded control.

Microprocessor: Processor-centered device that commonly relies on external memory and peripherals.

SoC: System-on-chip integrating multiple processing and peripheral subsystems.

ISA: Instruction set architecture visible to software.

ALU: Arithmetic logic unit that performs arithmetic and logical operations.

Bus: Communication structure carrying addresses, data, and control information.

Memory map: Assignment of address ranges to memory and peripherals.

Register: Small, fast storage location inside a processor or peripheral.

Pipeline: Overlapped instruction-processing stages.

Interrupt: Event that requests temporary execution of an interrupt service routine.

Interrupt latency: Time from an eligible event to commencement of its service.

Timer: Hardware counter used for timing, capture, comparison, or waveform generation.

PWM: Pulse-width modulation used to control average power or voltage.

Watchdog: Hardware timer that detects failure to service software and initiates recovery.

DMA: Direct memory access transfer with limited CPU intervention.

ADC: Converter that represents an analog input as a digital code.

DAC: Converter that produces an analog output from a digital code.

Cache: Fast storage holding recently used memory data.

Determinism: Predictability of execution time and system response.

Review Questions

Short Answer Questions

1. What distinguishes a microcontroller from a microprocessor?
2. What roles do address, data, and control signals play in a bus?
3. Why can a long interrupt service routine be harmful in a real-time system?
4. State two uses of DMA in a mechatronic controller.
5. What is the purpose of a watchdog timer?

Long Answer Questions

1. Explain the instruction-execution cycle and discuss how pipelining affects performance and timing predictability.
2. Compare MCU, MPU, and SoC architectures for an industrial robot controller.
3. Explain memory organization, including flash, RAM, stack, memory-mapped I/O, and cache.
4. Discuss ADC sampling, quantization, aliasing, and practical sources of conversion error.
5. Describe a complete timer-triggered control loop using interrupts, PWM, ADC, DMA, and watchdog supervision.

Analytical / Application Questions

1. A controller executes 30,000 instructions per loop with an average CPI of 1.5 at 60 MHz. Calculate the ideal CPU execution time and explain why the real loop time may be larger.
2. Select an architecture for a battery-powered temperature-controlled actuator that needs two PWM outputs, a 12-bit ADC, a periodic control loop, CAN communication, and low standby power. Justify the choice against an MPU-based alternative.
3. Design a fault-response strategy for a motor controller in which ADC sampling is performed by DMA and overcurrent can occur during a PWM cycle. Identify which protections should be hardware-based and which may be software-based.

Multiple Choice Questions with Answers

Question 1

Which device typically integrates a CPU, program memory, RAM, timers, and GPIO on one chip?

A. Microcontroller

B. External DRAM module

C. Standalone DAC

D. Bus transceiver

Correct Answer: A. Microcontroller

Question 2

If an address bus has 16 independent lines and each address identifies one byte, what is the maximum directly addressable space?

A. 16 bytes

B. 256 bytes

C. 65,536 bytes

D. 1,048,576 bytes

Correct Answer: C. 65,536 bytes

Question 3

Which register normally holds the address of the next instruction?

A. Status register

B. Program counter

C. Stack pointer

D. Data register

Correct Answer: B. Program counter

Question 4

A routine executes 12,000 instructions at an average CPI of 2 on a 24 MHz processor. What is the ideal CPU execution time?

A. 0.5 ms

B. 1 ms

C. 2 ms

D. 24 ms

Correct Answer: B. 1 ms

Question 5

What is the principal purpose of a watchdog timer?

A. To increase ADC resolution

B. To provide nonvolatile program storage

C. To recover from software failure by initiating a defined response

D. To convert digital data into analog voltage

Correct Answer: C. To recover from software failure by initiating a defined response

Question 6

Which technique transfers a block of peripheral data to memory with little continuous CPU involvement?

A. DMA

B. Polling only

C. Instruction pipelining

D. Cache invalidation

Correct Answer: A. DMA

Question 7

For an ideal 12-bit ADC with a 3.3 V reference, the approximate code width is:

A. 0.806 mV

B. 8.06 mV

C. 80.6 mV

D. 806 mV

Correct Answer: A. 0.806 mV

Question 8

Which feature is especially valuable for generating synchronized motor-control waveforms?

A. PWM timer

B. Keyboard controller

C. Audio codec only

D. Virtual-memory disk

Correct Answer: A. PWM timer

Question 9

Why can caches complicate hard real-time analysis?

A. They eliminate all interrupts

B. They introduce variable memory-access behavior

C. They prevent use of registers

D. They convert analog signals directly

Correct Answer: B. They introduce variable memory-access behavior

Question 10

Which architecture is generally most appropriate for a small, low-power controller with deterministic I/O and integrated peripherals?

A. High-end desktop computer

B. Microcontroller

C. External GPU only

D. Storage controller without a CPU

Correct Answer: B. Microcontroller