Serial Communication and Peripheral Protocols

Introduction

An embedded system rarely operates in isolation. Sensors, actuators, displays, memory devices, motor controllers, diagnostic tools, and other processors exchange information through communication interfaces. In an Internet of Things (IoT) node, the communication interface must often work with limited memory, low power, modest processing capability, electrical noise, and strict cost constraints.

Serial communication transfers data one bit or symbol at a time over a small number of electrical connections. Serial interfaces are generally cheaper and easier to route than wide parallel buses. This chapter examines five important interfaces: UART, I²C, SPI, CAN, and USB. They differ in electrical signalling, framing, addressing, arbitration, error detection, speed, topology, and software complexity.

Protocol selection is an engineering decision rather than a matter of choosing the fastest interface. A sensor board may favour I²C because two shared signal lines are sufficient. A display may require SPI bandwidth. An industrial controller may require CAN's robust arbitration and error confinement. A computer-connected device may need USB's host-controlled architecture.

Learning Objectives

After completing this chapter, the learner should be able to:

1. Explain the purpose of serial communication and distinguish synchronous from asynchronous transmission.
2. Describe UART framing, baud rate, parity, and common troubleshooting methods.
3. Implement and analyse I²C addressing, acknowledgements, clock stretching, and arbitration.
4. Explain SPI signalling, chip selection, clock polarity and phase, and throughput limitations.
5. Describe CAN frames, nondestructive arbitration, error detection, and bus reliability.
6. Explain the basic architecture of USB and distinguish it from simpler peripheral buses.
7. Estimate practical throughput and select an appropriate protocol for an IoT application.
8. Diagnose wiring, configuration, signal-integrity, and software faults in serial interfaces.

1. Serial Communication Foundations

1.1 Data, symbols, and links

A communication link has a transmitter, a receiver, a signalling medium, and rules defining how data is represented. A bit is a binary information unit. A symbol is a physical signalling state; in simple binary serial links, one symbol commonly represents one bit.

The raw bit rate is commonly expressed in bits per second (bit/s). If a frame contains useful payload bits and overhead bits, the useful throughput is lower than the raw rate. A general efficiency expression is:

where η is dimensionless efficiency, N_payload is the number of payload bits, and N_total is the total number of transmitted bits. The approximation assumes that all transmitted bits have equal time cost and excludes additional delays such as arbitration, software processing, and bus turnaround.

The effective payload rate is:

where R_raw is the physical bit rate in bit/s. In a real system, inter-frame gaps, acknowledgements, retries, host scheduling, and interrupt latency may reduce the measured rate further.

1.2 Synchronous and asynchronous communication

In synchronous communication, transmitter and receiver share timing information, usually through a clock signal. SPI and I²C are synchronous. The clock controls when data is sampled.

In asynchronous communication, no separate clock wire is transmitted. The receiver derives timing from an agreed baud rate and the transitions in the data frame. UART is the most familiar asynchronous interface. Its transmitter and receiver must use compatible timing settings, although small clock errors can often be tolerated.

1.3 Single-ended and differential signalling

Single-ended signalling measures a signal relative to a common ground. UART, I²C, and SPI are commonly implemented this way over short board-level distances. Differential signalling represents information using the voltage difference between two conductors. CAN uses differential signalling, which improves rejection of common-mode noise and supports longer, more robust wiring when correctly terminated.

Signal integrity depends on rise and fall time, trace length, capacitance, impedance, grounding, electromagnetic interference, and termination. A protocol can be logically correct yet fail electrically if its signals are distorted.

2. UART: Asynchronous Serial Communication

2.1 UART operation

A Universal Asynchronous Receiver/Transmitter (UART) converts parallel data in a microcontroller into a serial bit stream and converts received serial bits back into parallel data. A basic UART connection uses:

• TX: transmit output
• RX: receive input
• GND: common reference

The transmitter TX of one device must connect to the receiver RX of the other. Logic-level UART should not be connected directly to RS-232 voltage levels. RS-232 uses different voltage conventions and polarity; a level converter is required.

A UART frame normally consists of one start bit, a configurable number of data bits, an optional parity bit, and one or more stop bits. The line is idle in the logic-high state in common UART implementations. A start bit drives the line low, allowing the receiver to begin sampling.

A common notation such as 8-N-1 means 8 data bits, no parity, and 1 stop bit. The start and stop bits are still transmitted, so an 8-N-1 character occupies 10 bit periods.

2.2 Baud rate and character time

For a UART frame with S start bits, D data bits, P parity bits, and T stop bits, the frame length is:

The character transmission time is:

where B is the baud rate in symbols per second. For ordinary binary UART, baud rate and bit rate are numerically equal. This calculation assumes no pauses between bits or characters.

For 8-N-1 at 9,600 bit/s:

The maximum ideal payload rate is therefore approximately 960 bytes/s, not 9,600 bytes/s, because 10 transmitted bits are required for each 8-bit byte.

2.3 Parity and error detection

Parity adds one bit selected so that the number of logical 1s in the data plus parity bit is even or odd. Even parity detects any odd number of bit inversions within the protected field, but it cannot detect all errors. For example, two inverted bits preserve parity. Parity is therefore an error-detection aid, not an error-correction mechanism.

UART itself normally does not provide addressing, packet length, message authentication, or retransmission. An application protocol must define message boundaries, commands, checksums or cyclic redundancy checks (CRCs), timeouts, and recovery behaviour.

2.4 UART implementation and troubleshooting

A reliable UART design should define logic voltage, baud rate, data bits, parity, stop bits, idle state, maximum cable length, and framing rules. Common faults include:

• TX and RX connected incorrectly.
• Missing or unsuitable common ground.
• Mismatched baud rate or frame format.
• Confusion between 3.3 V logic, 5 V logic, RS-232, and RS-485.
• Incorrect clock configuration causing baud-rate error.
• Buffer overflow because software does not service the receiver promptly.
• Missing line termination or transceiver configuration on longer links.

An oscilloscope or logic analyser can reveal whether the idle level, start bit, bit period, and frame format are correct. A framing error often indicates baud mismatch, noise, incorrect polarity, or a wrong number of data or stop bits.

3. I²C: Addressed Two-Wire Communication

3.1 Bus structure

The Inter-Integrated Circuit (I²C) bus uses two signals:

• SDA: serial data
• SCL: serial clock

Both lines are generally open-drain or open-collector. Devices pull a line low but release it to allow a pull-up resistor to produce the high level. This arrangement permits multiple devices to share the bus and supports wired arbitration.

A simplified connection is:

Figure: Typical shared I²C bus. Pull-up resistors establish the high level; devices actively pull the lines low.

The pull-up resistor value must provide acceptable rise time while limiting sink current. Excessive bus capacitance and weak pull-ups produce slow rising edges. Very low resistance increases current when a device pulls the line low. The correct value depends on supply voltage, capacitance, device specifications, and bus speed.

3.2 Addressing and transactions

I²C devices use addresses, commonly 7-bit addresses, although 10-bit addressing is also defined. A transaction usually begins with a START condition, followed by an address and a read/write direction bit. The addressed receiver returns an acknowledge (ACK) or not-acknowledge (NACK). Data bytes are transferred with an ACK/NACK after each byte, and the controller ends the transaction with a STOP condition.

A repeated START permits a controller to change direction or address without releasing the bus. A typical register read writes a register address, issues a repeated START, and then reads one or more data bytes.

The address space is not equivalent to the number of physically connectable devices. Some addresses are reserved, and many products offer only a small selection of hardware address pins. Address conflicts can require an I²C multiplexer, separate bus segments, or devices with alternative addresses.

3.3 Arbitration and clock stretching

Because devices only actively drive low, a high level is effectively recessive and a low level dominant. If two controllers transmit simultaneously, a controller that sends a high but observes a low has lost arbitration and stops transmitting. The winning transaction continues without corrupting the bus.

A target device may hold SCL low to delay the controller; this is called clock stretching. Although supported by the I²C specification, not every controller, bridge, or operating-system driver handles it equally well. Designs must verify compatibility.

3.4 I²C limitations

I²C is convenient for short, low-to-moderate-speed board interconnections, but it is not normally intended for long cables. Bus capacitance limits rise time, and noise or ground offsets can cause errors. I²C also has protocol overhead from addressing and acknowledgement, and a stuck-low device can hold the whole bus. Recovery procedures may include disabling the peripheral, manually toggling SCL, issuing a STOP-like sequence, and resetting the faulty device.

4. SPI: High-Speed Synchronous Peripheral Communication

4.1 Signals and topology

Serial Peripheral Interface (SPI) commonly uses:

• SCLK: serial clock
• MOSI: controller-out, peripheral-in
• MISO: peripheral-out, controller-in
• CS or SS: chip select

SPI has no universal addressing or packet format. The controller selects a peripheral, supplies the clock, and transfers data. Multiple peripherals can share SCLK, MOSI, and MISO, but each normally requires a separate chip-select signal. A peripheral must place MISO in a high-impedance state when deselected.

SPI is full duplex: a bit can be shifted out and another bit shifted in during each clock cycle. It can achieve high throughput with low protocol overhead, making it suitable for displays, external flash memory, ADCs, DACs, and radio modules.

4.2 Clock polarity and phase

SPI devices specify a clock polarity (CPOL) and clock phase (CPHA). CPOL defines the idle clock level. CPHA defines whether data is sampled on the first or second clock edge after the cycle begins. The four combinations are commonly called SPI modes 0 to 3. The controller and peripheral must use the same mode.

A mode mismatch may produce data that appears shifted, constant, or random. The data sheet must be followed rather than relying on default driver settings.

4.3 Throughput and practical constraints

If one data bit is transferred per clock edge and one bit per clock period is used for the relevant channel, the nominal transfer rate is approximately the SCLK frequency. For an N-byte transaction with command, address, dummy, and payload fields, efficiency is:

where all N values are measured in bytes. This expression assumes each field occupies one byte and ignores chip-select gaps and software delays.

SPI's disadvantages include additional pins, lack of standard device discovery, absence of built-in acknowledgement, and usually no inherent error detection. Applications commonly add command status, CRC, sequence numbers, or read-back verification.

5. CAN: Robust Multi-Node Control Networking

5.1 Purpose and physical layer

Controller Area Network (CAN) is a message-oriented, multi-master network designed for robust communication among controllers. It uses a differential pair, commonly CAN_H and CAN_L, and requires appropriate termination at the two physical ends of a linear bus. Nodes attach through transceivers that translate logic signals to the differential bus.

CAN identifies messages by an arbitration identifier rather than by a destination address in the usual sense. Every node can observe a transmitted frame and decide whether the identifier is relevant.

5.2 Nondestructive arbitration

CAN uses dominant and recessive bus states. A dominant bit overrides a recessive bit. During arbitration, a node transmits its identifier while monitoring the bus. If it transmits recessive but observes dominant, it has lost arbitration and stops transmitting. The message with the highest priority identifier—numerically lowest in standard CAN arbitration—continues without being corrupted.

This mechanism provides deterministic priority under normal conditions. It does not guarantee that a low-priority message will always meet a deadline; excessive high-priority traffic can cause starvation. Network design must therefore allocate identifiers and analyse worst-case loading.

5.3 Frames and error handling

A classical CAN data frame includes a start-of-frame bit, arbitration field, control information, data field, CRC field, acknowledgement field, and end-of-frame field. Classical CAN carries up to 8 data bytes per frame. CAN FD extends the data field and can use a faster data phase, subject to transceiver and network constraints.

CAN detects errors through bit monitoring, bit stuffing checks, frame-format checks, acknowledgement checks, and CRC. Nodes signal detected errors with an error flag. Faulty nodes maintain transmit and receive error counters and may move through error-active, error-passive, and bus-off states. This error confinement prevents a persistently faulty node from indefinitely disrupting the network.

Bit stuffing inserts a complementary bit after a prescribed run of equal bits. The receiver removes the stuffed bits. This supports timing resynchronisation and provides another consistency check.

5.4 CAN design limitations

CAN requires compatible bit timing across nodes, correct termination, a suitable topology, and careful electromagnetic design. The maximum practical cable length decreases as bit rate increases because signal propagation and sampling margins become more demanding. CAN does not define the meaning of application data; higher-layer protocols such as CANopen or J1939 may supply device profiles, transport, and diagnostics.

6. USB: Host-Controlled Peripheral Connectivity

Universal Serial Bus (USB) is a comprehensive host-controlled system rather than merely a shift register interface. A USB system includes a host, devices, hubs, endpoints, descriptors, transfers, enumeration, and defined electrical and protocol layers.

When a device is connected, the host detects it and performs enumeration. It requests descriptors that identify the device, its configurations, interfaces, endpoints, and capabilities. The host then assigns an address and selects a configuration. Devices do not normally initiate bus transactions independently; they respond to host scheduling.

USB supports different transfer types:

• Control transfers configure and manage devices.
• Bulk transfers provide reliable delivery for large data volumes when bandwidth is available.
• Interrupt transfers provide bounded-latency polling for small amounts of data; the name does not imply an electrical interrupt.
• Isochronous transfers provide scheduled bandwidth for time-sensitive streams, with limited retransmission guarantees.

USB includes CRCs and handshaking at relevant protocol layers, but reliable application behaviour still requires correct descriptors, endpoint management, buffering, and error handling. USB is more complex than UART, I²C, or SPI and generally requires a protocol stack, connector rules, power management, and compliance considerations.

7. Comparing Protocols and Selecting an Interface

A practical selection process asks:

1. Is the connection on the same PCB, within a cabinet, or over a cable exposed to noise?
2. How many devices must share the medium?
3. Is deterministic priority or collision-free multi-master operation required?
4. What payload rate and latency are required?
5. Are pins, power, and software resources constrained?
6. Does the device ecosystem require standard host compatibility?
7. What error detection, recovery, and safety evidence are required?

The fastest nominal clock is not always the best choice. A low-speed CAN link may deliver more dependable system performance than a faster single-ended SPI cable in a noisy industrial environment.

8. Worked Engineering Examples

Example 1: UART payload rate

A sensor sends 200 bytes using 8-E-1 UART at 19,200 bit/s. Each frame contains 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit:

The transmission time is:

Thus the ideal payload transfer takes approximately 115 ms, before software gaps and processing delays. The useful payload rate is approximately 19,200 × 8/11 ≈ 13,964 bit/s, or about 1,746 bytes/s.

Example 2: SPI efficiency

An SPI memory transaction contains 1 command byte, 3 address bytes, 1 dummy byte, and 64 payload bytes. The efficiency is:

At an 8 MHz clock, the 69-byte transfer takes:

The payload rate during this transaction is approximately 64 bytes / 69 μs ≈ 0.928 MB/s, ignoring chip-select setup and software delays.

9. Implementation and Troubleshooting Practice

A disciplined implementation begins with the data sheet and interface contract. Record pin functions, voltage levels, electrical limits, timing parameters, address assignments, frame formats, and reset states. Separate the hardware driver from the application protocol so that a UART driver, for example, does not contain device-specific command interpretation.

Use logic analysers to decode protocol fields, but verify the analyser's voltage threshold and decoder settings. A decoded trace can be misleading if the sampling rate is inadequate or the wrong SPI mode is selected. Oscilloscopes are especially useful for observing rise time, ringing, overshoot, differential amplitude, and clock quality.

A useful troubleshooting sequence is:

1. Confirm power, ground, pin multiplexing, and voltage compatibility.
2. Test the physical signal at the connector or device pin.
3. Verify clock, baud, polarity, phase, address, and termination settings.
4. Reduce speed and simplify the transaction.
5. Check acknowledgements, status flags, and driver error codes.
6. Add timeouts so a failed peripheral cannot block the system indefinitely.
7. Test reset and bus-recovery behaviour.
8. Stress the link with noise, repeated transactions, power cycling, and maximum payloads.

Firmware should use bounded buffers, clear ownership of shared buses, and explicit recovery paths. Interrupt-driven or DMA-based transfers reduce CPU overhead, but they introduce concurrency concerns. Shared SPI buses require protection against two tasks changing chip select or mode simultaneously. I²C buses require recovery for devices that remain stuck low. CAN applications must monitor bus-off events and define safe recovery. USB applications must handle device removal, reset, and enumeration failure.

10. Illustrative Case: Environmental Monitoring Gateway

Background

Consider an illustrative agricultural IoT gateway containing a microcontroller, temperature and humidity sensors, a high-resolution display, a CAN-connected pump controller, and a USB port for configuration.

Problem

The first prototype uses UART for every peripheral. This requires separate links, lacks systematic addressing, and provides weak fault isolation. The display update is slow, and a long cable to the pump controller experiences intermittent corruption.

Analysis

The sensors are on the same PCB and require modest data rates. I²C is suitable because several sensors can share two lines, provided their addresses do not conflict. The display needs frequent transfers and can use SPI with a dedicated chip-select line. The pump controller is in a noisy electrical environment and needs message priority and error confinement, so CAN is more appropriate. USB is retained for a host computer because enumeration and standard transfer classes are valuable.

Approach and solution

The design assigns I²C addresses and verifies pull-up resistance against total bus capacitance. The display driver specifies its SPI mode and maximum clock rate and uses DMA for large screen regions. The CAN network uses two end terminators, a controlled linear topology, priority identifiers, and bus-off diagnostics. The USB firmware implements descriptors and a configuration interface. Each application message includes a version field and, where needed, a sequence number and application-level integrity check.

Outcome

The revised design reduces wiring for local sensors, improves display throughput, and provides a more robust pump-control link. Fault handling is clearer because each interface has explicit timeout and recovery behaviour. The gateway's design is not based on one universal protocol; it uses each protocol where its characteristics provide the greatest system benefit.

Learning points

Protocol selection should follow physical environment, topology, timing, throughput, interoperability, and failure consequences. A communication interface is part of the safety and maintainability design, not merely a connection between pins.

11. Limitations, Governance, and Contemporary Practice

Communication protocols do not automatically provide confidentiality, authentication, or safe control. UART, I²C, SPI, and classical CAN commonly expose data in plaintext. USB devices can also present security risks if untrusted peripherals are accepted. IoT products should authenticate firmware updates, validate commands, protect debug ports, and apply least-privilege principles.

Safety-critical or industrial designs require documented requirements, traceable verification, fault analysis, and standards appropriate to the sector. A CRC detects many accidental transmission errors but does not prove that a message came from an authorised source. Acknowledgement proves a receiver responded, not that the requested physical action completed safely.

Contemporary systems increasingly combine traditional buses with CAN FD, USB-C, higher-speed USB variants, low-power microcontrollers, DMA, protocol gateways, and time-sensitive networking. These developments increase capability but also increase configuration complexity. Engineers should prefer a simpler interface when it satisfies requirements, and should document every non-obvious timing, recovery, and compatibility assumption.

Chapter Summary

Serial protocols provide structured ways for embedded devices to exchange data. UART is simple and commonly point-to-point, but its framing, addressing, and error recovery are largely application responsibilities. I²C provides an addressed, shared two-wire bus using open-drain signalling, acknowledgements, arbitration, and optional clock stretching; its performance is constrained by bus capacitance and pull-up behaviour. SPI offers high-speed, full-duplex transfers with low overhead, but requires chip-select management and application-defined framing and error handling. CAN is a robust multi-master network using differential signalling, priority-based nondestructive arbitration, CRC and other error checks, and error confinement. USB is a host-controlled, enumerated peripheral architecture with a comparatively complex protocol stack.

Correct implementation requires attention to voltage levels, wiring, timing, termination, configuration, buffers, timeouts, recovery, and signal integrity. Protocol selection should consider topology, environmental noise, throughput, latency, scalability, interoperability, software complexity, and consequences of failure. Professional designs combine appropriate hardware with explicit application protocols, diagnostics, security controls, and verification testing.

Key Terms

UART: Hardware that performs asynchronous serial transmission and reception.

Baud rate: Number of signalling symbols transmitted per second.

Frame: Structured group of bits containing control information and data.

Parity: An error-detection bit representing the parity of a data field.

I²C: Synchronous, addressed two-wire inter-integrated-circuit bus.

Open-drain: Output arrangement that actively pulls low and releases the line for a high level.

ACK: Acknowledge response indicating acceptance of a transferred byte or transaction element.

Clock stretching: A device's action of holding a synchronous clock line low to delay transfer.

SPI: Synchronous serial peripheral interface using clock, data, and chip-select signals.

CPOL: SPI parameter defining the idle level of the clock.

CPHA: SPI parameter defining the clock edge used for sampling or changing data.

CAN: Robust multi-master controller area network.

Arbitration: Process by which competing transmitters determine which message continues.

Dominant bit: CAN bus state that overrides a recessive state.

CRC: Cyclic redundancy check used to detect transmission errors.

Bus-off: CAN error state in which a node disconnects itself from normal bus participation.

USB: Host-controlled universal serial bus architecture.

Enumeration: USB process of detecting, identifying, addressing, and configuring a device.

Signal integrity: Quality of electrical waveforms relative to timing and voltage requirements.

Throughput: Useful data delivered per unit time.

Review Questions

Short Answer Questions

1. What is the difference between synchronous and asynchronous serial communication?
2. Why does an 8-N-1 UART frame require 10 bit periods per byte?
3. What is the purpose of pull-up resistors on an I²C bus?
4. What do CPOL and CPHA specify in SPI?
5. Why is CAN arbitration described as nondestructive?

Long Answer Questions

1. Explain UART framing, parity, baud rate, and the major causes of framing errors.
2. Describe an I²C read transaction, including START, address, ACK, repeated START, data, and STOP.
3. Compare SPI and I²C in terms of wiring, speed, addressing, error handling, and scalability.
4. Explain CAN arbitration, frame checking, error confinement, and the role of termination.
5. Describe USB enumeration and compare USB transfer types with simpler embedded buses.

Analytical / Application Questions

1. An embedded controller must connect to eight low-speed sensors on one circuit board. Analyse whether I²C or SPI is more appropriate and identify the electrical and addressing issues that must be checked.
2. A CAN node repeatedly enters the bus-off state after a wiring change. Propose a systematic diagnostic procedure, including physical-layer and software checks.
3. Select protocols for a battery-powered environmental gateway with local sensors, a fast display, a noisy motor controller, and a laptop configuration port. Justify each selection using topology, throughput, robustness, and implementation complexity.

Multiple Choice Questions with Answers

Question 1

A UART configured as 8-N-1 transmits how many bit periods for each data byte?

A. 8

B. 9

C. 10

D. 11

Correct Answer: C. 10

Question 2

Which I²C mechanism allows a device to delay the controller temporarily?

A. Parity insertion

B. Clock stretching

C. Chip select

D. Bit stuffing

Correct Answer: B. Clock stretching

Question 3

What is the primary purpose of a separate SPI chip-select signal?

A. To provide bus termination

B. To select the peripheral participating in a transaction

C. To generate parity

D. To assign a CAN identifier

Correct Answer: B. To select the peripheral participating in a transaction

Question 4

In CAN arbitration, what happens to a node that transmits recessive but observes dominant?

A. It continues and overwrites the dominant bit

B. It resets the entire bus

C. It loses arbitration and stops transmitting

D. It changes its baud rate

Correct Answer: C. It loses arbitration and stops transmitting

Question 5

Which protocol normally requires a host to initiate and schedule device transfers?

A. UART

B. SPI

C. CAN

D. USB

Correct Answer: D. USB

Question 6

A UART frame has 1 start bit, 8 data bits, 1 parity bit, and 1 stop bit. At 19,200 bit/s, what is the ideal time for 200 bytes?

A. 83.3 ms

B. 104.2 ms

C. 114.6 ms

D. 208.3 ms

Correct Answer: C. 114.6 ms

Question 7

Which feature most directly improves CAN communication in a noisy environment?

A. Single-ended open-drain signalling

B. Differential signalling and error confinement

C. Separate chip select for every message

D. USB enumeration

Correct Answer: B. Differential signalling and error confinement

Question 8

What is a major limitation of I²C compared with SPI on a circuit board?

A. I²C cannot acknowledge data

B. I²C has no device addresses

C. I²C rise time is affected by pull-ups and bus capacitance

D. I²C cannot use multiple devices

Correct Answer: C. I²C rise time is affected by pull-ups and bus capacitance

Question 9

An SPI transaction contains 5 overhead bytes and 64 payload bytes. What is its ideal payload efficiency?

A. 64/69 ≈ 92.8%

B. 5/64 ≈ 7.8%

C. 64/5 = 1280%

D. 69/64 ≈ 107.8%

Correct Answer: A. 64/69 ≈ 92.8%

Question 10

Which statement about parity is correct?

A. Parity corrects all corrupted bits

B. Parity detects every possible multi-bit error

C. Parity can detect some errors but does not provide correction

D. Parity provides message authentication

Correct Answer: C. Parity can detect some errors but does not provide correction