Digital Electronics and Computer Fundamentals

Introduction

Embedded systems for the Internet of Things (IoT) are built from digital electronic circuits and small computers. A temperature node, smart meter, wearable device, industrial sensor, or connected actuator must represent information electrically, process that information, store program instructions and data, and communicate with other devices. These functions depend on a common foundation: binary numbers, logic gates, digital circuits, memory, processors, clocks, buses, registers, and input/output interfaces.

This chapter develops that foundation from the electrical representation of digital information to the operation of a simple CPU. The emphasis is on concepts that a diploma-level IoT practitioner can apply when selecting a microcontroller, reading a datasheet, connecting a sensor, configuring a peripheral, or diagnosing a hardware problem.

Learning Objectives

After studying this chapter, you should be able to:

1. Convert and interpret binary, decimal and hexadecimal numbers.
2. Explain Boolean variables, logic gates and Boolean algebra.
3. Analyse basic combinational and sequential circuits.
4. Describe memory organization, capacity and addressing.
5. Explain CPU architecture, registers and the instruction cycle.
6. Relate clock frequency, timing and performance.
7. Distinguish address, data and control buses.
8. Explain memory-mapped input/output and apply it to IoT devices.
9. Select suitable design practices for reliable embedded hardware.

1. Digital Information and Number Systems

1.1 Analogue and digital representation

An analogue signal can take a continuous range of values. A microphone voltage, for example, may vary smoothly with sound pressure. A digital system represents information using discrete symbols, most commonly two voltage ranges called logic 0 and logic 1. The actual voltage limits depend on the technology and supply voltage; therefore, a logic value is not necessarily exactly 0 V or exactly the supply voltage.

Digital representation provides noise tolerance, repeatability, convenient storage and reliable processing. However, physical quantities in IoT systems are often analogue. Sensors therefore commonly require an analogue-to-digital converter (ADC), while actuators such as motors may require digital-to-analogue conversion, pulse-width modulation (PWM), or switching circuits.

1.2 Binary and positional notation

The binary number system has radix 2 and uses the digits 0 and 1. In a positional system, each position has a weight determined by a power of the radix. For an n-bit binary number with bits bₙ₋₁ through b₀, its unsigned decimal value is:

Here, bᵢ ∈ {0, 1}, n is the number of bits, and V is the decimal value. The expression applies to unsigned integers. An n-bit unsigned number represents values from 0 to 2ⁿ − 1.

For example:

10110110₂ = 1×128 + 0×64 + 1×32 + 1×16 + 0×8 + 1×4 + 1×2 + 0×1 = 182₁₀.

A binary fraction uses negative powers of two. For example, 0.101₂ equals 1/2 + 0/4 + 1/8 = 0.625₁₀. In embedded work, fractional values are often represented using fixed-point or floating-point formats rather than unrestricted binary fractions.

1.3 Hexadecimal notation

Hexadecimal has radix 16 and uses 0–9 and A–F. One hexadecimal digit represents exactly four binary bits:

Binary-to-hexadecimal conversion is performed by grouping bits from the right into groups of four. Thus, 1101\ 0110₂ = D6₁₆. Hexadecimal is widely used for addresses, register values, machine instructions and bit masks because it is more compact than binary while preserving bit boundaries.

1.4 Signed integers and two’s complement

Unsigned representation cannot express negative values. The most common signed-integer representation in microcontrollers is two’s complement. For n bits, the representable range is:

The leftmost bit has a negative weight, −2ⁿ⁻¹, while the remaining bits have positive weights. For eight bits, the range is −128 to +127. To obtain the two’s complement representation of −5, write +5 as 00000101, invert the bits to 11111010, and add 1, giving 11111011.

Two’s complement is useful because ordinary binary addition hardware can perform both positive and negative addition. Overflow occurs when a result lies outside the representable range. For example, adding 127 and 1 in an 8-bit signed system produces the bit pattern 10000000, which represents −128; this is overflow, not a valid representation of +128.

1.5 Data units and coding

A bit is a binary digit. A group of eight bits is a byte. A word is a processor-dependent unit, such as 16, 32 or 64 bits. Storage capacity is commonly expressed in bytes, while communication rates are expressed in bits per second.

Binary numbers represent magnitude, but digital systems also encode characters and structured data. ASCII represents common characters using seven bits, usually stored in an eight-bit byte. Unicode supports a much larger character set through encodings such as UTF-8. IoT protocols may encode data using compact binary formats, text formats such as JSON, or application-specific packet structures.

2. Boolean Logic and Digital Gates

Boolean algebra operates on variables that have two values, usually 0 and 1. It provides a mathematical model for digital circuits. The fundamental operations are AND, OR and NOT.

• AND produces 1 only when all inputs are 1.
• OR produces 1 when at least one input is 1.
• NOT complements one input: 0 becomes 1 and 1 becomes 0.

The symbols commonly used are Y = A·B for AND, Y = A + B for OR, and Y = \overline{A} for NOT. In Boolean algebra, + does not mean ordinary arithmetic addition, and multiplication denotes logical conjunction.

XOR, or exclusive OR, is 1 when the inputs differ. NAND is NOT-AND and NOR is NOT-OR. NAND and NOR are universal gates: any Boolean function can be constructed using only NAND gates or only NOR gates.

Important Boolean identities include:

De Morgan’s laws are:

These laws are useful when changing between active-high and active-low logic or implementing a circuit with available NAND or NOR gates.

2.1 Combinational logic

A combinational circuit produces an output determined only by its present inputs. It has no memory of previous input values. Examples include adders, multiplexers, decoders, encoders and comparators.

A half-adder adds two one-bit inputs. Its sum and carry outputs are:

A full-adder also includes an input carry, Cᵢₙ:

These equations describe ideal logic and do not include gate propagation delays. A multi-bit binary adder is formed by connecting full-adders, although faster architectures may reduce carry propagation delay.

A multiplexer selects one of several inputs. For a two-input multiplexer with data inputs D₀ and D₁ and select input S:

When S = 0, Y = D₀; when S = 1, Y = D₁. Multiplexers are used inside processors and peripheral systems to route signals.

2.2 Propagation delay and hazards

Real gates do not change output instantaneously. Propagation delay is the time between an input transition and the corresponding valid output transition. Unequal delays can create short unwanted pulses called glitches or hazards. In safety-related or high-speed designs, timing analysis, synchronisation and appropriate circuit design are necessary. A circuit that is logically correct in a truth table may still fail if its timing is ignored.

3. Sequential Logic and State

A sequential circuit depends on present inputs and stored previous state. Storage elements include latches and flip-flops. A latch is generally level-sensitive; a flip-flop is commonly edge-triggered by a clock.

3.1 Clocks and flip-flops

A clock is a periodic digital signal used to coordinate state changes. Its frequency f and period T are related by:

Frequency f is measured in hertz and period T in seconds. A 16 MHz clock has a period of 62.5 ns, assuming an ideal clock source.

A D flip-flop transfers its D input to Q on a specified clock edge. The value remains stored until the next active edge. Correct operation requires setup time, the interval during which D must be stable before the edge, and hold time, the interval during which D must remain stable after the edge. Violating these requirements can cause metastability, an uncertain or delayed output state.

A register is a group of flip-flops storing a multi-bit value. Counters, shift registers and finite-state machines are important sequential structures. A finite-state machine (FSM) consists of a finite set of states, rules for changing state based on inputs, and outputs associated with states or transitions. FSMs are useful for communication protocols, device control and power-management sequences.

4. Memory Concepts

4.1 Memory organization

Memory stores binary information in uniquely addressable locations. If an address bus contains n independent bits, it can identify up to 2ⁿ distinct addresses. If each address refers to one byte, the maximum directly addressable capacity is:

This formula assumes byte-addressable memory and that all address combinations are usable. Actual systems may reserve addresses, mirror devices or implement a different addressable unit.

For example, a 16-bit byte-address bus can identify 2¹⁶ = 65,536 byte locations, equivalent to 64 KiB. Here, KiB means 1024 bytes; it should not be confused with the decimal unit kB, which commonly means 1000 bytes.

Memory is often described by organisation, such as 4096 × 8, meaning 4096 locations each holding 8 bits. Its capacity is 4096 × 8 bits = 32,768 bits = 4096 bytes.

4.2 Memory types

Read-only memory (ROM) retains its contents without power and is suitable for permanent firmware. Programmable variants include PROM, EPROM and EEPROM. Flash memory is electrically erasable and is widely used for microcontroller program storage and non-volatile data.

Random-access memory (RAM) can be read and written during operation. SRAM uses flip-flop-like cells, is fast and does not require refresh, but occupies more silicon area. DRAM stores charge in capacitors, requires refresh and provides high density. Microcontrollers commonly integrate SRAM for variables, stack and buffers, and flash for program code.

Non-volatile memory retains data when power is removed. It is useful for configuration, calibration constants and event logs. Write endurance, retention time and write latency must be considered. Repeatedly writing a flash location can wear it out, so wear levelling or a suitable data-logging strategy may be needed.

4.3 Memory hierarchy

A processor may access registers, cache, main memory and external storage, in that order of generally increasing capacity and access latency. Registers are inside the CPU and are fastest. Cache stores recently used instructions and data close to the CPU. Small microcontrollers may have no cache, while larger IoT processors often use one or more cache levels.

A program must also manage stack and heap regions. The stack stores function-call information, local variables and saved registers. The heap supports dynamic allocation where provided. In resource-constrained embedded systems, uncontrolled dynamic allocation can cause fragmentation and unpredictable failure; static allocation or bounded memory pools are often safer.

5. CPU Architecture and Instruction Execution

A central processing unit (CPU) executes instructions. Its principal components are the arithmetic and logic unit (ALU), control unit, registers, clocking system and interfaces to memory and peripherals.

• The ALU performs arithmetic, comparison, shifts and Boolean operations.
• The control unit interprets instruction fields and generates control signals.
• Registers hold operands, addresses, intermediate values and status information.
• The program counter (PC) identifies the next instruction address.
• The instruction register (IR), where present, holds the instruction being decoded.
• A stack pointer (SP) identifies the active stack location.
• A status or flags register records conditions such as zero, carry, negative and overflow.

Instruction execution is commonly described as fetch, decode and execute. During fetch, the CPU uses the PC to read an instruction from memory. The PC is advanced, unless a branch or interrupt changes it. During decode, the instruction opcode and operands are interpreted. During execute, the ALU, registers, memory system or peripheral interface performs the requested operation. Some processors divide these activities into pipeline stages, allowing several instructions to be in different stages simultaneously.

The exact number of clock cycles per instruction depends on the architecture, instruction type, memory wait states, pipeline and peripheral conditions. Therefore, clock frequency alone does not fully determine performance.

Figure: Simplified CPU, memory and peripheral arrangement in a microcontroller system.

5.1 Instruction sets

An instruction set architecture (ISA) defines the programmer-visible instructions, registers, data types and addressing modes. RISC designs generally use a relatively small set of regular instructions, while CISC designs may provide more complex instructions. Modern distinctions are not absolute, but the ISA remains important for compiler support, code size, performance and available development tools.

An instruction may contain an opcode and operand fields. Addressing modes determine how operands are obtained: immediate addressing embeds a constant; register addressing uses a register; direct or absolute addressing specifies a memory location; indirect addressing obtains an address from a register. Understanding addressing modes helps when reading assembly code and debugging compiler output.

6. Buses, Registers and Timing

A bus is a shared pathway for transferring information. The address bus identifies a source or destination, the data bus carries the value, and the control bus carries signals such as read, write, interrupt, reset and enable. In a simple system, a read transaction places an address on the address bus, asserts a read control signal, and returns data on the data bus. A write transaction places both an address and data value and asserts write control.

Bus width affects the amount transferred or the number of locations selected, but interpretation depends on the architecture. A 32-bit data bus can transfer 32 data bits in one bus operation, whereas a 32-bit address bus can identify up to 2³² address values if all are implemented and byte addressing is used.

Registers are small storage locations with defined functions. General-purpose registers hold operands; special-purpose registers control operation or expose peripheral state. A register description in a datasheet normally specifies reset value, bit meaning, read/write permissions and side effects. Some bits are write-one-to-clear, read-only, reserved or automatically modified by hardware. Software must not blindly write reserved bits.

Timing includes setup and hold requirements, clock-to-output delay, bus turnaround time and peripheral response time. Synchronisers are used when a signal crosses between unrelated clock domains. Mechanical switches and many sensors also require debouncing or filtering because their signals may change repeatedly before settling.

7. Memory-Mapped Input/Output

Memory-mapped I/O assigns peripheral control and data registers addresses within the processor’s normal address space. A CPU writes to a GPIO direction register to configure a pin, writes to an output register to drive a value, or reads an input register to observe a signal. The same load and store instructions used for memory may access peripherals.

For example, assume a hypothetical microcontroller maps a GPIO output register at address 0x40001000 and the least significant bit controls an LED. A read-modify-write operation can set that bit:

1. Read the register value.
2. Apply the mask 0x00000001 using bitwise OR.
3. Write the result back.

In pseudocode:

GPIO_OUT = GPIO_OUT OR 0x00000001

The actual syntax depends on the programming language and hardware abstraction layer. If the register is declared volatile, the compiler must perform the access because hardware may change the value independently of program flow. Volatile does not make a multi-step operation atomic; an interrupt or another bus master could still intervene. Hardware set/clear registers or critical sections may be required.

Memory-mapped I/O differs from isolated or port-mapped I/O, in which a separate address space and special instructions are used. Memory-mapped I/O is common in microcontrollers because it simplifies the CPU interface and allows ordinary load/store mechanisms.

7.1 Interrupts and polling

Polling repeatedly tests a status register. It is simple but consumes processor time and may respond slowly if the polling interval is long. An interrupt allows a peripheral to request CPU attention. The CPU saves relevant context, branches to an interrupt service routine, services the event and returns to the interrupted program.

Interrupt routines should be short, deterministic and safe. Shared data between an interrupt routine and foreground code may require atomic access, suitable data types, or a carefully designed communication mechanism. Interrupt priorities and nesting must be understood in real-time applications.

8. Applied Case: Battery-Powered Environmental Sensor Node

Background

This illustrative case concerns a battery-powered node that measures temperature and humidity, displays a status indicator and transmits measurements periodically over a wireless interface.

Problem

The node must remain asleep for most of its operating life, wake every five minutes, acquire reliable measurements, detect a low-battery condition and return to a low-power state. A design that leaves the CPU or sensor powered continuously would reduce battery life.

Analysis

The designer selects a microcontroller with flash for firmware, SRAM for variables and communication buffers, a timer for wake-up scheduling, an ADC for battery measurement, GPIO for sensor power and an SPI or I²C interface for the environmental sensor. A clock source is chosen with consideration for accuracy, startup time and energy consumption.

The firmware uses an FSM with states such as SLEEP, WAKE, MEASURE, TRANSMIT and ERROR. A timer interrupt exits SLEEP. GPIO enables sensor power, a peripheral register configures the serial interface, and status flags indicate when data is ready. The ADC converts battery voltage into a digital code. If an ADC has an ideal resolution of N bits and input range from 0 to VREF, the code for an input voltage V_IN is approximately:

This relationship assumes an ideal ADC, a voltage within the input range, and a suitable reference. Quantisation, reference error, noise and input impedance create practical errors.

Approach and solution

The firmware configures pins and peripherals once, then uses interrupt-driven wake-up and communication. Sensor readings are stored in a small RAM buffer. The node validates values against plausible limits, adds a sequence number and transmits a compact packet. After transmission, the radio and sensor are disabled and the microcontroller enters a sleep mode.

Register accesses use named definitions and masks rather than unexplained numeric constants. Read-only and write-one-to-clear status bits are handled according to the datasheet. A watchdog timer provides recovery if the program becomes unresponsive. Brownout detection protects against unreliable operation when the battery voltage falls.

Outcome

The resulting architecture separates hardware control from application logic, reduces energy use and makes faults observable. The design is maintainable because each peripheral has a clear configuration procedure and the FSM makes operating states explicit.

Learning points

1. CPU, memory, buses and peripherals form one coordinated system.
2. Low-power operation depends on clock, memory and peripheral management, not merely on a low-power CPU.
3. Datasheet register definitions are part of the engineering design process.
4. Correct digital logic must be combined with timing, power, noise and fault considerations.

9. Design Practices, Limitations and Contemporary Considerations

Reliable embedded design begins with a clear hardware specification. Define voltage levels, current limits, timing requirements, reset behaviour, memory capacity, peripheral interfaces and failure responses before selecting components. Use debouncing, filtering, watchdogs, brownout detection and defensive range checks where appropriate.

Digital circuits are abstractions of analogue electrical behaviour. Noise margins, signal integrity, ground reference, rise and fall times, electromagnetic compatibility and power integrity can determine whether a logical design works in practice. Long wires, poor decoupling and unsuitable pull-up resistors can cause intermittent failures.

Security is also a hardware concern. IoT devices should protect firmware and credentials, restrict debug access in production, validate updates, use secure boot where supported, and avoid exposing sensitive data through diagnostic registers or unsecured interfaces. Safety-critical systems require hazard analysis, independent verification and applicable regulatory compliance.

Contemporary microcontrollers increasingly integrate hardware cryptography, secure enclaves, low-power wireless radios, DMA controllers and machine-learning accelerators. These features can improve performance and energy efficiency, but they add configuration complexity. A designer should prefer documented, testable features and should not assume that an accelerator or higher clock automatically produces a better system.

Chapter Summary

Digital electronics represents information with discrete logic levels, principally binary 0 and 1. Binary positional notation, hexadecimal shorthand and two’s complement are essential for interpreting data, addresses and signed values. Boolean algebra describes gates and supports the design and simplification of combinational circuits such as adders and multiplexers.

Sequential circuits use storage elements and clocks to retain state. Setup time, hold time, propagation delay and metastability explain why practical timing matters. Memory is organised into addressed locations, with RAM, flash, ROM, registers and caches serving different purposes. An n-bit address system can identify 2ⁿ locations when all address combinations are implemented.

A CPU executes instructions through fetch, decode and execute activities using the ALU, control unit, registers and program counter. Address, data and control buses connect the CPU with memory and peripherals. In memory-mapped I/O, peripheral registers occupy addresses in the processor’s address space and are controlled through carefully defined reads and writes. These concepts provide the foundation for designing, programming and troubleshooting IoT embedded systems.

Key Terms

Binary number: A number represented using radix 2 and the digits 0 and 1.

Bit: A single binary digit.

Byte: A group of eight bits.

Hexadecimal: A radix-16 number system using digits 0–9 and A–F.

Two’s complement: A signed binary representation commonly used for integers.

Boolean algebra: Algebra for variables and operations having values 0 and 1.

Logic gate: A circuit that implements a Boolean operation.

Combinational circuit: A circuit whose output depends on present inputs.

Sequential circuit: A circuit whose output depends on present inputs and stored state.

Flip-flop: An edge-triggered storage element.

Register: A group of storage elements used to hold a digital value.

Clock: A periodic signal used to coordinate digital operations.

Propagation delay: The time between an input change and the corresponding output change.

Metastability: An uncertain temporary state caused by a timing violation.

CPU: The processor that fetches and executes instructions.

ALU: The arithmetic and logic unit that performs data operations.

Bus: A pathway carrying addresses, data or control signals.

Memory-mapped I/O: Peripheral registers assigned addresses in the normal memory space.

Interrupt: A hardware or software event that requests processor attention.

Volatile access: An access that software must perform because hardware may change the value independently.

Review Questions

Short Answer Questions

1. Why is hexadecimal notation useful when working with binary addresses and register values?
2. State the difference between a combinational circuit and a sequential circuit.
3. What roles do the program counter and stack pointer perform?
4. Define setup time and hold time.
5. What is memory-mapped input/output?

Long Answer Questions

1. Explain binary, hexadecimal and two’s complement representations, including their ranges and practical uses.
2. Describe Boolean gates and Boolean algebra, and explain how a full-adder operates.
3. Explain the organisation and characteristics of RAM, flash memory, registers and cache.
4. Describe the fetch–decode–execute instruction cycle and the functions of the main CPU components.
5. Explain address, data and control buses and discuss how timing affects bus transactions.

Analytical / Application Questions

1. An eight-bit signed register contains 11111011₂. Determine its decimal value and explain the method used.
2. A microcontroller has a 16-bit byte-address bus. Calculate its maximum directly addressable capacity and express the result in KiB, assuming every address is implemented.
3. Design a high-level finite-state-machine sequence for a battery-powered sensor node that wakes, measures, transmits, handles an error and returns to sleep. Identify suitable interrupts and memory-mapped peripherals.

Multiple Choice Questions with Answers

Question 1

What is the decimal value of 1101₂?

A. 11

B. 12

C. 13

D. 14

Correct Answer: C. 13

Question 2

Which representation is most commonly used for signed integers in microcontrollers?

A. One’s magnitude

B. Two’s complement

C. BCD only

D. Gray code

Correct Answer: B. Two’s complement

Question 3

What is the output of an XOR gate when its two inputs are different?

A. 0

B. 1

C. Undefined

D. Always equal to the first input

Correct Answer: B. 1

Question 4

Which circuit retains information about a previous input?

A. Combinational circuit

B. Decoder

C. Sequential circuit

D. Multiplexer only

Correct Answer: C. Sequential circuit

Question 5

What is the period of an ideal 20 MHz clock?

A. 20 ns

B. 50 ns

C. 200 ns

D. 500 ns

Correct Answer: B. 50 ns

Question 6

A memory with 10 address bits and byte-addressable locations can directly identify how many bytes, assuming all addresses are implemented?

A. 10 bytes

B. 100 bytes

C. 512 bytes

D. 1024 bytes

Correct Answer: D. 1024 bytes

Question 7

Which CPU component performs Boolean operations and arithmetic?

A. ALU

B. Program counter

C. Stack pointer

D. Clock oscillator only

Correct Answer: A. ALU

Question 8

Which bus carries the location of a memory or peripheral register?

A. Data bus

B. Address bus

C. Power bus

D. Audio bus

Correct Answer: B. Address bus

Question 9

What does memory-mapped I/O mean?

A. Only RAM can be accessed by the CPU

B. Peripherals use addresses within the processor’s memory address space

C. I/O devices cannot generate interrupts

D. All peripheral data is stored permanently in ROM

Correct Answer: B. Peripherals use addresses within the processor’s memory address space

Question 10

For an ideal 8-bit ADC with a 3.3 V reference, which approximate code corresponds to an input of 1.65 V?

A. 0

B. 64

C. 128

D. 255

Correct Answer: C. 128