11. Oscillators, Timing and Data-Conversion Circuits

Introduction and Context

Oscillators and data-conversion circuits form the interface between continuous-time physical phenomena and discrete-time electronic systems. An oscillator generates a periodic waveform without an externally applied periodic input. Timing circuits establish accurate temporal reference points, while sample-and-hold circuits, analogue-to-digital converters (ADCs), and digital-to-analogue converters (DACs) translate information between analogue and digital representations.

These circuits are central to communication systems, instrumentation, control, power electronics, embedded systems, medical equipment, audio systems, and industrial automation. Their design cannot be judged by function alone. Frequency accuracy, phase noise, jitter, linearity, resolution, conversion speed, power consumption, stability, and error budget must be considered together. A converter with high nominal resolution may be ineffective if its reference, clock, input driver, or grounding arrangement introduces larger errors than one least significant bit.

This chapter develops the operating principles and design methods for sinusoidal and relaxation oscillators, multivibrators, waveform generators, phase-locked loops, sample-and-hold circuits, ADCs, and DACs. Particular attention is given to practical trade-offs and to the relationship between circuit-level imperfections and system-level performance.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the conditions required for sustained oscillation and distinguish sinusoidal from relaxation oscillators.

2. Design and analyse common RC, LC, crystal, timer, and comparator-based oscillators.

3. Explain astable, monostable, and bistable multivibrator operation.

4. Describe PLL architecture, lock behaviour, capture limitations, and applications.

5. Analyse sampling, aperture uncertainty, acquisition time, and hold droop in sample-and-hold circuits.

6. Compare ADC architectures using resolution, conversion time, accuracy, noise, and power as criteria.

7. Analyse DAC architectures and identify major static and dynamic error sources.

8. Construct performance-oriented error budgets for timing and data-conversion systems.

9. Select appropriate circuits for practical engineering applications.

Oscillation as a Feedback Phenomenon

A sinusoidal oscillator may be viewed as an amplifier combined with a frequency-selective positive-feedback network. For a linear feedback model, the loop gain is

\[

T(j\omega)=A(j\omega)\beta(j\omega).

\]

The Barkhausen conditions for an ideal steady sinusoid are

\[

|A\beta|=1,\qquad \angle A\beta=0^\circ \;(\text{or }360^\circ).

\]

These conditions identify the oscillation frequency and the required loop gain, but they do not fully explain start-up or amplitude stabilization. In practice, the small-signal loop gain must initially exceed unity so that noise or a disturbance grows. A nonlinear mechanism subsequently reduces the effective gain until the steady-state amplitude is stable. If the excess gain is too large, distortion increases; if it is too small, start-up may be unreliable.

The frequency-selective network determines which frequency experiences the required phase and gain. The active device supplies energy lost in the resonator. Thus oscillator design involves both a frequency problem and an amplitude-control problem.

Sinusoidal Oscillators

An RC phase-shift oscillator uses several RC sections to provide 180 degrees of phase shift, while an inverting amplifier supplies the remaining 180 degrees. For three identical ideal sections, the oscillation frequency is approximately

\[

f_o \approx \frac{1}{2\pi RC\sqrt{6}},

\]

and the amplifier gain must exceed approximately 29 for start-up. Loading between sections changes both values, so buffered or carefully analysed networks are preferred in precision designs.

A Wien-bridge oscillator uses a lead-lag RC network. With equal resistors and capacitors, its nominal frequency is

\[

f_o=\frac{1}{2\pi RC}.

\]

The bridge has zero phase shift at this frequency, and the amplifier gain must be approximately three. Amplitude stabilization may be achieved with a lamp, back-to-back diodes, a field-effect transistor used as a variable resistor, or an automatic gain-control loop. Diodes are simple but introduce distortion; thermal or closed-loop control generally produces better spectral purity.

LC oscillators are preferred at higher frequencies because an inductor-capacitor resonator provides a high-Q frequency-selective network. For an ideal parallel or series LC resonator,

\[

f_o=\frac{1}{2\pi\sqrt{LC}}.

\]

The Colpitts oscillator uses a capacitive divider, whereas the Hartley oscillator uses an inductive divider. The resonator, transistor parasitics, load capacitance, and layout determine the actual frequency. At radio frequency, stray capacitance and inductance must therefore be included in the design model.

Crystal oscillators exploit the piezoelectric resonance of quartz. Their high Q provides excellent frequency stability and low phase noise compared with ordinary RC oscillators. A crystal does not automatically guarantee accuracy: crystal tolerance, temperature coefficient, ageing, load capacitance, drive level, and pulling by the oscillator circuit all contribute to frequency error. Temperature-compensated and oven-controlled crystal oscillators improve performance at increased cost and power.

Relaxation Oscillators

A relaxation oscillator alternately charges and discharges an energy-storage element between threshold levels. Its output is usually a square wave, while the storage element produces a ramp, triangle, or exponential waveform. A Schmitt trigger combined with an integrator is a representative structure. Hysteresis provides two switching thresholds and prevents noise from causing rapid unwanted transitions.

For a capacitor charged through a resistor between lower and upper thresholds, the time interval is determined by the exponential capacitor voltage. If the thresholds are symmetric about the supply midpoint, the period can often be written in the form

\[

T=2RC\ln\left(\frac{1+\beta}{1-\beta}\right),

\]

where \(\beta\) represents the normalized hysteresis threshold. The exact expression depends on the circuit topology. This dependence illustrates an important design principle: timing accuracy is controlled not only by R and C but also by threshold accuracy, supply sensitivity, leakage, and comparator delay.

The 555 timer is a widely used practical relaxation-oscillator building block. In its astable configuration, two resistors and a capacitor determine charge and discharge intervals. The conventional circuit produces a duty cycle greater than 50 percent unless steering diodes or a separate charge-discharge path is added. Modern timer ICs and microcontroller timers may provide superior repeatability, programmability, and synchronization.

Timing Circuits and Multivibrators

Multivibrators are switching circuits with two regenerative states. An astable multivibrator has no stable state and oscillates continuously. A monostable multivibrator has one stable state and produces a timed pulse when triggered. A bistable multivibrator has two stable states and functions as a latch or flip-flop.

In an astable circuit, cross-coupled gain and timing capacitors cause one device to conduct while the other is cut off. As the capacitor voltage changes, the circuit reaches a threshold and regeneratively switches. The timing interval is approximately proportional to RC, but transistor saturation storage, threshold variation, and unequal component values affect pulse symmetry and transition timing.

A monostable circuit is useful for pulse stretching, switch debouncing, missing-pulse detection, and one-shot timing. Its pulse width may be set by

\[

t_p\approx kRC,

\]

where the constant \(k\) depends on the threshold and topology. A monostable must be specified with its retriggering behaviour, minimum trigger width, recovery time, and tolerance to trigger noise.

A bistable circuit stores one bit of information. In digital systems, regenerative feedback provides noise immunity, but setup time, hold time, propagation delay, and metastability become important when asynchronous signals are sampled. A timing circuit is therefore not adequately specified by nominal delay alone; uncertainty in the switching instant matters as much as the average delay.

Waveform Generation and Practical Design Choices

A square wave can be generated directly by a comparator or timer. A triangle wave is obtained by integrating a square wave, and a ramp is obtained by integrating a unidirectional pulse train. A sine wave may be produced by filtering a square wave, using a nonlinear sine-shaping circuit, or employing a resonant oscillator.

Waveform selection depends on the application. A function generator should specify amplitude range, frequency range, distortion, DC offset, output impedance, duty-cycle range, and load capability. In a digital timing system, edge placement and jitter may be more important than amplitude fidelity. In an instrumentation source, harmonic distortion and long-term frequency stability may dominate.

A common design mistake is to treat an operational amplifier as ideal while selecting extreme resistor or capacitor values. Large resistors increase thermal-noise voltage and make bias-current and leakage errors significant. Large capacitors may have poor tolerance or dielectric absorption. High-speed circuits require attention to slew rate, gain-bandwidth product, output recovery, parasitic capacitance, and comparator overdrive.

Phase-Locked Loops

A phase-locked loop (PLL) is a feedback system that forces the phase of a voltage-controlled oscillator (VCO) to track the phase of a reference. Its principal blocks are a phase detector, loop filter, VCO, and, in many systems, a frequency divider. A simplified relation is

\[

f_{out}=Nf_{ref}

\]

for an integer-N synthesizer, subject to the divider and detector arrangement.

The phase detector produces an error proportional, over a suitable range, to phase difference. The loop filter converts this error into a slowly varying control voltage. The VCO converts control voltage into frequency. When locked, the average frequency error is nearly zero, while a finite phase error may remain depending on detector and filter characteristics.

PLL design is a control-system problem. Loop bandwidth determines a trade-off between tracking speed and noise filtering. A wide bandwidth permits fast acquisition and tracks reference changes, but passes more reference and detector noise. A narrow bandwidth reduces noise but increases settling time and may fail to track rapid changes. Phase margin and damping must be selected to avoid excessive overshoot or instability.

The capture range is the frequency range over which the unlocked loop can acquire lock; the lock or hold range is the range over which it remains locked after acquisition. These ranges are not necessarily equal. Cycle slipping, VCO tuning nonlinearity, supply noise, reference spurs, and divider quantization affect synthesizer performance. Fractional-N PLLs provide fine frequency resolution by varying the effective division ratio, but quantization noise and fractional spurs require noise-shaping and careful filtering.

PLLs are used for clock recovery, carrier recovery, frequency synthesis, motor control, jitter cleaning, demodulation, and clock multiplication. In a clock-recovery application, the loop must track data-rate variations while rejecting data-dependent phase disturbances. In a frequency synthesizer, reference spur suppression and phase-noise performance may be more important than rapid acquisition.

Sampling and Sample-and-Hold Circuits

Sampling converts a continuous-time signal into a sequence of values. For a band-limited signal with highest frequency \(f_{max}\), ideal uniform sampling requires

\[

f_s>2f_{max},

\]

known as the Nyquist criterion. This condition alone does not prevent aliasing in practice. An anti-aliasing low-pass filter must attenuate signal components above half the sampling frequency, and the sampling clock must have sufficiently low timing uncertainty.

A sample-and-hold circuit contains an analogue switch, a hold capacitor, and a buffer. During acquisition, the switch connects the input to the capacitor. During hold, the switch opens and the buffer presents the stored voltage to the converter. The acquisition time depends on switch resistance, source resistance, hold capacitance, and the required settling accuracy. For a first-order path, the residual error after time \(t\) is approximately

\[

e(t)=e_0e^{-t/RC}.

\]

The hold interval is affected by capacitor leakage, buffer bias current, dielectric absorption, switch charge injection, clock feedthrough, and droop. Aperture uncertainty is uncertainty in the effective sampling instant. For an input sine wave of frequency \(f_{in}\), timing uncertainty \(t_j\) produces approximately

\[

v_{err,rms}\approx 2\pi f_{in}V_{pk}t_{j,rms}.

\]

Thus clock jitter becomes increasingly damaging at high input frequency and high signal amplitude. A converter may have many nominal bits but obtain fewer effective bits if aperture jitter or analogue noise is excessive.

Analogue-to-Digital Converters

An ADC maps an analogue input range into a finite set of digital codes. For an ideal N-bit converter with full-scale range \(V_{FS}\), the nominal quantization step is approximately

\[

q=\frac{V_{FS}}{2^N}.

\]

The ideal quantization error is bounded by approximately ±q/2, and its rms value for an uncorrelated input is \(q/\sqrt{12}\). The signal-to-quantization-noise ratio for a full-scale sine wave is often approximated by

\[

SNR\approx 6.02N+1.76\;\text{dB}.

\]

This expression is an ideal benchmark, not a guarantee of actual performance.

Principal ADC Architectures

A flash ADC uses one comparator per threshold, requiring approximately \(2^N-1\) comparators. It offers very high speed but consumes substantial area and power, and resistor-ladder mismatch limits accuracy.

A successive-approximation-register (SAR) ADC uses a sample-and-hold, capacitive or resistive DAC, comparator, and binary-search logic. It provides a strong compromise among speed, resolution, power, and size. During conversion, the SAR tests each bit from most significant to least significant. The reference, capacitor matching, comparator offset, and input settling are major error sources.

A dual-slope ADC integrates the input for a fixed interval and then integrates an opposite-polarity reference until the integrator returns to zero. The measured time is proportional to input voltage. This architecture is slow but rejects certain periodic interference components and offers excellent DC accuracy, making it common in digital multimeters.

A pipeline ADC divides conversion into stages. Each stage resolves a few bits, subtracts the corresponding DAC value, amplifies the residue, and passes it to the next stage. Pipelining provides high throughput but introduces latency and requires calibration for gain, offset, and capacitor mismatch.

A sigma-delta ADC oversamples the input, shapes quantization noise toward higher frequencies, and digitally filters and decimates the result. It achieves high resolution over a limited bandwidth, although conversion latency and modulator stability must be considered.

ADC Performance Metrics

Offset error is the deviation of the actual transfer curve from the ideal curve near zero input. Gain error is the slope error after offset is accounted for. Integral nonlinearity (INL) measures deviation of actual codes from a chosen ideal straight line. Differential nonlinearity (DNL) measures code-width deviation; a DNL less than −1 LSB can produce missing codes. Other important specifications are effective number of bits (ENOB), signal-to-noise-and-distortion ratio (SINAD), spurious-free dynamic range, aperture jitter, throughput, latency, reference sensitivity, and power consumption.

An ADC error budget should include quantization noise, thermal noise, reference noise, input-driver noise, clock jitter, offset, gain, INL, DNL, crosstalk, supply coupling, and temperature drift. Errors may be random or systematic. Random noise is commonly combined by root-sum-square when sources are independent; systematic errors require calibration or correction rather than simple averaging.

Digital-to-Analogue Converters

A DAC produces an analogue output corresponding to a digital code. A basic N-bit DAC has an ideal step size close to full-scale range divided by \(2^N\). The output may be a voltage or current, and an output amplifier may be required to provide scaling, buffering, and low impedance.

A binary-weighted-resistor DAC uses resistors with values proportional to binary weights. It is conceptually simple but becomes difficult to match over a wide resistance range. An R–2R ladder uses only two resistor values and is more suitable for integrated implementation. A current-steering DAC switches matched current sources and is appropriate for high-speed applications. A string DAC uses a resistor string and multiplexer; it offers monotonicity and simplicity but may be slower or consume static current.

DAC specifications include settling time, monotonicity, zero-scale and full-scale error, gain error, INL, DNL, glitch impulse, output noise, reference sensitivity, and temperature coefficient. Glitch impulse occurs when several bits change simultaneously and do not switch at exactly the same time. It can be reduced by segmented architectures, carefully timed switches, return-to-zero techniques, or output filtering.

For a unipolar DAC, a simple output model is

\[

V_o=V_{ref}\frac{D}{2^N},

\]

where D is the digital code, subject to the selected endpoint convention. In precision systems, the reference is part of the conversion system, not an auxiliary component. Reference noise and drift directly appear at the output, while reference impedance and decoupling influence dynamic behaviour.

Error-Budget Method for Converter and Timing Design

A disciplined design begins by translating system requirements into electrical quantities. Suppose an instrumentation channel requires a total input-referred error below 0.5 mV. The designer may allocate portions to sensor conditioning, reference uncertainty, ADC quantization, noise, gain drift, offset drift, and layout-induced interference.

For independent rms noise sources,

\[

e_{total,rms}=\sqrt{e_1^2+e_2^2+\cdots+e_n^2}.

\]

For worst-case bounded systematic errors, magnitudes may be added conservatively. A 16-bit nominal ADC is not automatically appropriate: if the input range is 5 V, one LSB is about 76 µV, but reference drift, amplifier offset, and noise may exceed that value. Conversely, averaging and bandwidth limitation can improve random-noise performance without improving static linearity or missing-code behaviour.

The same reasoning applies to clock systems. Total timing uncertainty can include oscillator phase noise, PLL residual jitter, divider noise, buffer additive jitter, and substrate or supply coupling. Independent rms contributions are combined by root-sum-square, while correlated disturbances require more careful analysis.

Applied Case: Precision Temperature-Measurement Module

Background

Consider an illustrative industrial temperature module measuring a conditioned thermocouple signal over a 0–2.5 V range. The module must provide 16-bit output, reject 50/60 Hz interference, and update the digital result at 20 samples per second.

Situation and Problem

A first prototype uses a fast SAR ADC clocked from a noisy microcontroller oscillator. Although the nominal resolution is 16 bits, measured results fluctuate by several codes, and readings change when a digital communication interface becomes active.

Analysis

The application has low bandwidth, so maximum conversion speed is not the dominant requirement. The relevant error sources are input amplifier noise, reference noise and drift, sampling transients, digital supply coupling, and interference near the mains frequency. The oscillator's short-term jitter is not the principal limitation at the low input frequency, but its supply noise is coupling into the ADC reference and analogue ground.

Approach and Solution

The design is revised as follows:

• An anti-aliasing low-pass filter is placed before the ADC, with a bandwidth selected substantially below half the sampling rate.
• A low-noise, temperature-stable reference is used with local bypassing and a layout that separates high-current digital return paths.
• The ADC input driver is selected for adequate settling into the sampling capacitor, and a small series resistor-capacitor network limits charge kickback.
• The sampling rate is increased internally, followed by digital averaging and a mains-rejection filter.
• The clock source is isolated from noisy digital loads, and converter, reference, and analogue amplifier supplies are filtered separately.
• Calibration removes measured offset and gain error; temperature coefficients are characterized rather than assumed negligible.

Outcome

The revised design does not obtain its performance merely by selecting a higher-resolution ADC. It obtains it through bandwidth control, reference integrity, input settling, grounding, clock management, and calibration. The effective resolution improves because the complete signal chain, rather than only the converter data sheet, is treated as the measurement instrument.

Learning Points

1. Nominal resolution and usable resolution are different specifications.

2. The reference and input driver are integral parts of an ADC design.

3. Oversampling helps random noise but cannot correct large systematic nonlinearity.

4. Low-frequency measurement systems often benefit more from filtering and interference control than from increased conversion speed.

5. Error budgets should be created before component selection.

Challenges, Risks, and Common Design Errors

Oscillators may fail to start because loop gain is insufficient, loading changes the phase condition, or amplitude control suppresses the disturbance required for start-up. Excessive loop gain causes clipping and harmonic distortion. Relaxation oscillators are vulnerable to threshold variation, leakage, and supply dependence.

PLL designs commonly suffer from inappropriate loop bandwidth, inadequate phase margin, reference spurs, VCO pushing, and failure to account for divider noise. A loop that appears stable in simulation may perform poorly when supply and substrate coupling are included.

ADC systems are often compromised by aliasing, insufficient acquisition time, overdriven input protection, reference decoupling mistakes, and digital return currents flowing through analogue ground. DACs may exhibit nonmonotonicity, output-amplifier settling errors, and large glitches at major-carry transitions. Datasheet specifications must be interpreted under the actual temperature, reference, sampling rate, input frequency, and loading conditions.

Professional and Ethical Considerations

Timing and conversion errors can affect safety-critical control, medical diagnosis, energy protection, and industrial shutdown decisions. Engineers should not report nominal resolution as measurement accuracy or conceal calibration assumptions. Uncertainty, environmental limits, out-of-range behaviour, and fault responses should be documented. Traceable calibration, production testing, electromagnetic-compatibility evaluation, and compliance with applicable sector standards are essential where measurement results influence safety, finance, or regulatory decisions.

Emerging Directions

Modern converter systems increasingly combine analogue front ends with digital calibration, background mismatch correction, adaptive filtering, and digitally assisted PLLs. Time-interleaved ADCs extend sampling rate but require correction of channel offset, gain, and timing mismatch. Digitally controlled oscillators and all-digital PLLs reduce dependence on large analogue loop-filter components and integrate readily with CMOS processes. Machine-learning techniques may assist calibration and anomaly detection, but they do not eliminate the need for physically meaningful error models, validation, and deterministic behaviour in safety-related systems.

Best Practices for Design

1. Define frequency, bandwidth, accuracy, latency, jitter, power, and environmental requirements before selecting a topology.

2. Use start-up and steady-state analyses for oscillators; do not rely on the Barkhausen condition alone.

3. Treat references, clocks, input drivers, grounding, and layout as parts of the converter.

4. Use anti-aliasing filters and verify acquisition time at the highest input impedance and temperature extremes.

5. Distinguish random noise, bounded error, drift, and nonlinearity in the error budget.

6. Verify designs with transient, noise, temperature, Monte Carlo, and worst-case simulations, followed by laboratory measurements.

7. Calibrate only errors that are stable and observable; do not use calibration to mask an unstable architecture.

8. Report ENOB, SINAD, jitter, and uncertainty under stated operating conditions rather than quoting nominal bit count alone.

Chapter Summary

Oscillators generate periodic energy exchange through frequency-selective feedback or threshold-controlled charging and discharging. Sinusoidal oscillators emphasize phase, loop gain, resonator Q, and amplitude stabilization, whereas relaxation oscillators emphasize thresholds, hysteresis, and timing components. Multivibrators provide astable, monostable, and bistable timing functions. PLLs use feedback to synchronize a VCO with a reference, with loop bandwidth, damping, capture behaviour, phase noise, and spurs determining performance.

Sampling and conversion connect analogue signals to digital systems. Sample-and-hold circuits must achieve adequate acquisition and low droop, while anti-aliasing and clock-jitter control protect sampled accuracy. ADC architectures make different trade-offs among speed, resolution, power, latency, and accuracy. DACs use weighted resistors, R–2R ladders, current steering, or resistor strings, with matching, settling, glitch, and reference quality determining output fidelity. Across all these circuits, an error budget is more informative than a nominal specification because system performance is governed by the complete signal chain.

Key Terms

Oscillator: A circuit that generates a periodic waveform without a periodic input.

Barkhausen condition: The ideal requirement of unity loop gain and zero net phase shift for sustained oscillation.

Relaxation oscillator: An oscillator based on charging and discharging an energy-storage element between thresholds.

Hysteresis: Separation between switching thresholds that improves noise immunity.

Multivibrator: A regenerative switching circuit having zero, one, or two stable states.

Phase-locked loop: A feedback system that synchronizes oscillator phase and frequency to a reference.

VCO: A voltage-controlled oscillator whose frequency varies with control voltage.

Capture range: The frequency range over which an initially unlocked PLL can acquire lock.

Jitter: Short-term uncertainty in the timing of a signal transition or sampling instant.

Sample-and-hold: A circuit that acquires an analogue voltage and maintains it during conversion.

Aperture uncertainty: Uncertainty in the effective instant at which sampling occurs.

Aliasing: Misrepresentation of high-frequency input components as lower-frequency components after sampling.

Quantization: Mapping a continuous amplitude into a finite set of digital codes.

INL: Deviation of a converter transfer characteristic from an ideal straight-line relationship.

DNL: Deviation of an individual converter code width from one ideal LSB.

ENOB: Effective number of bits inferred from measured noise and distortion performance.

SAR ADC: An ADC that resolves bits successively through a binary-search process.

Sigma-delta ADC: An oversampling ADC that shapes quantization noise and digitally filters it.

Glitch impulse: A transient output error caused by unequal switching times in a DAC.

Error budget: A quantitative allocation of allowable contributions from individual error sources.

Review Questions

Short Answer Questions

1. State the two ideal Barkhausen conditions for sustained oscillation.

2. What distinguishes an astable, monostable, and bistable multivibrator?

3. Define PLL capture range and explain why it differs from hold range.

4. Why is an anti-aliasing filter required before an ADC?

5. Define INL and DNL.

Long Answer Questions

1. Explain the operation and amplitude-stabilization requirements of a Wien-bridge oscillator.

2. Compare flash, SAR, dual-slope, pipeline, and sigma-delta ADCs in terms of speed, resolution, and application.

3. Describe PLL architecture and explain the effect of loop bandwidth on acquisition, noise, and stability.

4. Explain the operation of a sample-and-hold circuit and analyse acquisition error, droop, charge injection, and aperture jitter.

5. Compare R–2R, current-steering, binary-weighted, and string DACs, including their principal error sources.

Analytical / Application Questions

1. A 12-bit ADC has a 4.096 V input range. Calculate its nominal step size and discuss why this value is not equal to guaranteed measurement accuracy.

2. A sampled sine wave has a peak amplitude of 1 V and frequency of 100 kHz. If rms sampling-clock jitter is 2 ns, estimate the rms voltage error caused by jitter using the small-error approximation.

3. An instrumentation system has independent rms noise contributions of 20 µV, 30 µV, and 40 µV. Calculate the combined rms noise and explain why systematic gain error should not be combined in the same way.

22. Multiple Choice Questions with Answers

Question 1

Which condition is required for the ideal steady-state operation of a feedback oscillator?

A. Loop gain magnitude is zero and phase shift is 180 degrees

B. Loop gain magnitude is unity and net phase shift is zero degrees

C. Amplifier gain is always less than unity

D. The feedback network must have no frequency selectivity

Correct Answer: B. Loop gain magnitude is unity and net phase shift is zero degrees

Question 2

A Wien-bridge oscillator with equal R and C components has a nominal frequency of:

A. RC/2π

B. 2πRC

C. 1/(2πRC)

D. 1/(RC√6)

Correct Answer: C. 1/(2πRC)

Question 3

Which multivibrator continuously alternates between two quasi-stable states?

A. Astable

B. Monostable

C. Bistable

D. Sample-and-hold

Correct Answer: A. Astable

Question 4

In a PLL frequency synthesizer with an integer divider N, the locked output frequency is ideally:

A. fref/N

B. Nfref

C. N/fref

D. Independent of the reference frequency

Correct Answer: B. Nfref

Question 5

For a sinusoidal input, aperture jitter becomes more damaging when:

A. Input frequency and signal amplitude are both increased

B. Input frequency is reduced to zero

C. The hold capacitor is made ideal

D. The ADC resolution is reduced

Correct Answer: A. Input frequency and signal amplitude are both increased

Question 6

Which ADC architecture generally provides very high speed at the cost of many comparators?

A. Dual-slope

B. Sigma-delta

C. Flash

D. Single-slope

Correct Answer: C. Flash

Question 7

A DNL value below −1 LSB can result in:

A. Increased PLL capture range

B. Missing ADC codes

C. Perfect DAC monotonicity

D. Reduced oscillator phase shift

Correct Answer: B. Missing ADC codes

Question 8

Which ADC is especially suitable for high-accuracy, low-bandwidth measurements and strong rejection of periodic interference?

A. Flash ADC

B. Dual-slope ADC

C. Pipeline ADC

D. Time-interleaved ADC

Correct Answer: B. Dual-slope ADC

Question 9

A major-carry transition in a DAC may produce a transient because:

A. All switches necessarily change at exactly the same time

B. Unequal switching delays create a glitch impulse

C. Quantization is absent at that code

D. The reference voltage becomes zero permanently

Correct Answer: B. Unequal switching delays create a glitch impulse

Question 10

Independent rms noise sources of 3 µV and 4 µV combine to produce approximately:

A. 1 µV

B. 5 µV

C. 7 µV

D. 12 µV

Correct Answer: B. 5 µV