5. Field-Effect Transistors

Introduction and Context

Field-effect transistors (FETs) are voltage-controlled semiconductor devices in which an electric field regulates the current flowing through a conducting channel. Unlike bipolar junction transistors, whose operation depends primarily on carrier injection and base current, FETs are controlled through an insulated or reverse-biased input terminal and therefore offer very high input resistance. This property, together with low static power consumption, excellent scalability, and compatibility with integrated-circuit fabrication, has made FETs central to analog, digital, mixed-signal, power, and radio-frequency electronics.

The principal families considered in this chapter are the junction field-effect transistor (JFET), the metal–oxide–semiconductor field-effect transistor (MOSFET), and complementary MOS (CMOS) circuits. The JFET provides an important physical introduction to channel depletion and pinch-off. The MOSFET extends this idea through an insulated gate and supports enhancement-mode operation, which is fundamental to modern integrated circuits. CMOS combines complementary n-channel and p-channel MOSFETs to obtain low static power and high noise margins.

A useful FET analysis must go beyond ideal square-law equations. Device behavior is influenced by body effect, channel-length modulation, mobility degradation, velocity saturation, parasitic capacitances, leakage mechanisms, temperature, process variation, and short-channel effects. These nonidealities determine gain, output resistance, switching speed, power consumption, noise, reliability, and the limits of scaling.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the physical operation and terminal characteristics of JFETs and MOSFETs.

2. Identify cutoff, triode or linear, saturation, and subthreshold operating regions.

3. Derive and apply large-signal and small-signal MOSFET models.

4. Analyze body effect, channel-length modulation, mobility reduction, and velocity saturation.

5. Estimate intrinsic and extrinsic capacitances and assess high-frequency performance.

6. Explain CMOS inverter operation, noise margins, power dissipation, and delay.

7. Evaluate scaling, leakage, reliability, and design trade-offs in practical technologies.

8. Select suitable device models for circuit analysis and design decisions.

From Controlled Depletion to the MOS Channel

JFET operation

An n-channel JFET consists of a narrow n-type channel between source and drain, with p-type gate regions forming reverse-biased p–n junctions. With the gate connected to a negative voltage relative to the source, the depletion regions expand into the channel and reduce its effective width. At sufficiently large reverse bias, the channel is fully depleted near the source or throughout much of its length, and the drain current is reduced toward zero.

For an n-channel device, the gate–source voltage is normally zero or negative. The drain–source voltage establishes the channel electric field and causes electrons to move from source to drain. When the drain voltage is increased, the channel becomes narrower near the drain because the local gate-to-channel reverse bias increases. The condition at which the channel just pinches off near the drain is called pinch-off. Increasing drain voltage beyond this point produces only a relatively modest increase in current, so the device enters its constant-current or saturation region.

The Shockley approximation for an n-channel JFET is

I_D=I_{DSS}(1-V_{GS}/V_{GS(off)})^2,

for the normal transfer characteristic, where I_DSS is the drain current at V_GS=0 and V_GS(off) is the cutoff gate voltage. This relation is useful for introductory analysis but is not sufficiently accurate for precision design because it neglects channel-length modulation, mobility variation, temperature, and device geometry.

MOSFET structure and enhancement operation

A MOSFET has a metal or polysilicon gate separated from the semiconductor by a thin insulating oxide. In an n-channel enhancement MOSFET, the source and drain are n-type regions in a p-type body. At zero gate voltage, no conducting inversion channel exists between source and drain. When the gate voltage exceeds the threshold voltage V_T, positive gate charge attracts electrons to the semiconductor surface and creates an n-type inversion layer. A drain-to-source voltage then drives current through this induced channel.

The gate current is ideally zero because the oxide blocks dc conduction. In practice, gate leakage exists because of tunneling, defects, contamination, and, in older technologies, oxide imperfections. The gate nonetheless behaves as a capacitive terminal, so charging and discharging it requires dynamic current.

A p-channel MOSFET is complementary: it is formed in an n-type body or well, conducts holes, and turns on when its gate voltage is sufficiently lower than its source voltage. The polarity conventions are reversed, but the physical principles are analogous.

Operating Regions and Large-Signal Models

For a long-channel n-channel enhancement MOSFET, define the overdrive voltage as

V_{OV}=V_{GS}-V_T.

The device is off when V_GS<V_T, although a subthreshold current may still flow. When V_GS>V_T, the region is determined by V_DS:

• Linear or triode region: 0≤V_DS<V_OV.
• Saturation region: V_DS≥V_OV.

In the linear region, the gradual-channel approximation gives

I_D=μ_n C_{ox}(W/L)[(V_{GS}-V_T)V_{DS}-V_{DS}^2/2].

The transistor behaves approximately as a voltage-controlled resistor for small V_DS. Its conductance is controlled by overdrive voltage and by the geometry ratio W/L.

In saturation,

I_D=1/2 μ_n C_{ox}(W/L)(V_{GS}-V_T)^2,

where μ_n is carrier mobility and C_ox is oxide capacitance per unit area. The equation assumes a long channel, constant mobility, negligible body effect, and no channel-length modulation. For a p-channel device, it is usually clearer to use source-referenced magnitudes such as V_SG and V_SD.

The boundary between triode and saturation is physically associated with the channel voltage at the drain reaching the inversion threshold condition. Saturation does not mean that the drain current becomes completely independent of drain voltage. In a real device, the effective channel shortens as V_DS increases, producing channel-length modulation. A practical saturation equation is therefore

I_D=1/2 k_n V_{OV}^2(1+λV_{DS}),

where k_n=μ_nC_oxW/L and λ is the channel-length modulation coefficient.

Small-signal parameters

Small-signal models describe incremental behavior around a bias point. In saturation, the transconductance is

g_m=∂I_D/∂V_{GS}=k_nV_{OV}=2I_D/V_{OV}.

Thus, for a fixed drain current, smaller overdrive produces larger transconductance, but it also reduces voltage headroom and may increase sensitivity to mismatch and variation. The output conductance caused by channel-length modulation is approximately

g_o=∂I_D/∂V_{DS}=λI_D,

and the corresponding output resistance is r_o=1/g_o≈1/(λI_D). The intrinsic voltage gain of a common-source stage is approximately g_mr_o. This explains why short-channel devices, which generally exhibit stronger channel-length modulation, have lower intrinsic gain than long-channel devices.

The body terminal introduces an additional small-signal effect. If the source-to-body voltage changes, the threshold voltage changes, producing body transconductance g_mb. A common small-signal drain-current expression is

i_d=g_mv_{gs}+g_{mb}v_{bs}+g_ov_{ds},

with sign conventions determined by the selected reference directions.

Body Effect and Threshold-Voltage Control

The body effect is the change in threshold voltage caused by a source-to-body bias. For an nMOS transistor, reverse biasing the source–body junction increases the depletion charge beneath the gate and raises the threshold voltage. A commonly used relation is

V_T=V_{T0}+γ[√(2φ_F+V_{SB})−√(2φ_F)],

where V_T0 is the threshold voltage at V_SB=0, γ is the body-effect coefficient, φ_F is the Fermi potential, and V_SB is the source-to-body voltage. The exact notation varies with process conventions.

Body effect is important in source followers, transmission gates, analog switches, stacked transistors, and circuits in which source voltages are not fixed relative to the substrate. It reduces the effective gate control because a change in source voltage also changes V_T. In a source follower, for example, the output does not track the gate perfectly: the source voltage rises until the available V_GS, adjusted for body effect and current requirements, is sufficient to sustain the load current.

Integrated circuits often use wells to control the body connection. Connecting the body to the lowest potential for nMOS and highest potential for pMOS prevents forward bias of the body diode, but it may increase body effect. Triple-well and related isolation structures provide designers with additional control, at the expense of process complexity and parasitic capacitance.

Subthreshold Conduction and Leakage

When V_GS is below threshold, the MOSFET is not perfectly off. Diffusion of minority carriers produces subthreshold current, approximately described by

I_D≈I_0 exp[(V_{GS}-V_T)/(nU_T)] [1−exp(−V_{DS}/U_T)],

where U_T=kT/q is the thermal voltage and n is the subthreshold slope factor. On a logarithmic scale, the subthreshold slope indicates the gate-voltage change required for a decade change in current. At room temperature, an ideal device cannot switch arbitrarily sharply because thermal statistics impose a fundamental limit on subthreshold slope.

Other leakage components include reverse-biased junction leakage, gate-oxide tunneling, gate-induced drain leakage, and drain-induced barrier lowering. Leakage increases with temperature and is strongly affected by threshold-voltage selection. Low-V_T devices provide higher speed but substantially greater standby current; high-V_T devices reduce leakage but may be slower.

Leakage is not merely a power issue. It affects memory retention, analog bias accuracy, sensor interfaces, battery life, thermal stability, and the reliability of power-gated systems. In nanoscale circuits, standby power may become comparable to or larger than dynamic power, especially in always-on blocks.

Channel-Length Modulation and Short-Channel Behavior

In the ideal long-channel model, the saturation current is independent of V_DS. In a real transistor, the pinch-off region expands toward the source as V_DS increases, reducing the effective channel length. The resulting current increase is represented by λ. This effect gives the output characteristic a finite slope and limits voltage gain.

When channel length becomes comparable to characteristic electrostatic dimensions, the gradual-channel approximation becomes inadequate. Important short-channel effects include:

• Drain-induced barrier lowering, in which drain voltage lowers the source-channel barrier and reduces the apparent threshold voltage.
• Velocity saturation, in which carrier velocity ceases to increase linearly with electric field.
• Mobility degradation caused by strong vertical electric fields near the oxide interface.
• Channel-length-dependent threshold voltage and increased parameter variability.
• Punch-through, in which source and drain depletion regions approach one another.
• Hot-carrier effects, caused by energetic carriers near high-field regions.

For long-channel devices, increasing V_OV increases current approximately quadratically. In short-channel devices with velocity saturation, current becomes closer to proportional to V_OV over important operating ranges. Consequently, the familiar square-law model may overestimate gain, switching current, and speed when applied without qualification to modern processes.

Capacitances and High-Frequency Operation

FET speed is limited not only by transconductance but also by the capacitances that must be charged and discharged. Important intrinsic capacitances include gate–source, gate–drain, gate–body, source–body, and drain–body capacitances. Overlap capacitances arise because the gate extends slightly beyond the source and drain diffusion regions.

The gate–drain capacitance is especially significant in analog amplifiers. Through the Miller effect, a voltage gain between gate and drain can multiply the effective input capacitance. For an inverting stage, an approximate input capacitance contribution is C_gd(1+|A_v|). This can greatly reduce bandwidth and increase the time required to drive the transistor.

Capacitances depend on operating region. In saturation, the inversion channel is pinched off near the drain, so the intrinsic gate charge is distributed mainly toward the source. In triode, the channel exists along the entire source-to-drain path, and gate capacitance is distributed differently. Junction capacitances are voltage dependent because depletion width changes with reverse bias.

A first-order unity-current-gain frequency is

f_T≈g_m/[2π(C_{gs}+C_{gd})],

although practical radio-frequency models include gate resistance, induced gate noise, substrate coupling, distributed effects, and extrinsic pad capacitances. High-frequency design therefore requires a verified compact model rather than only the square-law equations.

CMOS Inverters and Complementary Design

A CMOS inverter consists of a pMOS pull-up transistor and an nMOS pull-down transistor. When the input is low, the pMOS conducts and the nMOS is off, producing a high output. When the input is high, the nMOS conducts and the pMOS is off, producing a low output. Ideally, no direct dc path exists from supply to ground in either stable logic state.

The voltage-transfer characteristic contains regions in which one transistor is saturated, both may conduct, and the other transistor is in a different operating region. The switching threshold depends on the relative strength of the two devices, their threshold voltages, supply voltage, body bias, and load. Proper sizing can make the switching point approximate mid-supply, improving noise margins.

Dynamic power is approximately

P_{dyn}=αC_LV_{DD}^2f,

where α is the activity factor, C_L is the switched capacitance, V_DD is supply voltage, and f is switching frequency. Short-circuit power occurs during input transitions when both transistors conduct simultaneously. Leakage power persists when the circuit is not switching.

CMOS logic is attractive because of high input resistance, rail-to-rail output swing, strong noise margins, and low static power under ideal assumptions. Its limitations include dynamic power, leakage, threshold variation, soft errors, process sensitivity, and reduced noise margin at low supply voltage.

Scaling and Technology Trade-offs

Scaling reduces dimensions and can improve density, switching speed, and energy per operation. However, simple geometric scaling is constrained by electric fields, leakage, variability, interconnect delay, and heat removal. Lowering supply voltage reduces dynamic power quadratically but also reduces noise margins and available overdrive. Lowering threshold voltage helps recover speed but increases leakage.

Modern transistors use structural innovations to improve electrostatic control. FinFETs employ a three-dimensional fin surrounded by the gate on multiple sides. Gate-all-around nanowire or nanosheet devices provide still stronger gate control and are used when planar structures no longer adequately suppress short-channel effects. High-k dielectrics and metal gates reduce gate leakage while preserving effective oxide capacitance and threshold-control flexibility.

At advanced nodes, interconnect resistance and capacitance may dominate system delay. Device optimization must therefore be performed with the interconnect network, packaging, thermal environment, and workload in view rather than by considering transistor dimensions alone.

Practical Design and Analysis Workflow

A reliable FET analysis normally proceeds in stages. First, establish terminal voltages and body connections using an explicit sign convention. Second, determine whether the device is off, in subthreshold, in triode, or in saturation. Third, apply the simplest model consistent with the required accuracy. Fourth, calculate the operating point and verify the assumed region. Fifth, linearize around that operating point to obtain transconductance, output resistance, and capacitance-related parameters. Finally, assess nonidealities such as body effect, channel-length modulation, leakage, temperature, and process variation.

For hand analysis, the square-law model is often appropriate for conceptual design and initial sizing. For precision analog, RF, mixed-signal, and nanoscale digital design, BSIM-type compact models and process design kits are essential. Simulation results should be checked against physical intuition and limiting cases. A simulation that produces a numerical answer but violates terminal-voltage constraints or body-diode conditions is not a valid design result.

Applied Case Study: Low-Power CMOS Sensor Interface

Background

Consider an illustrative battery-powered sensor interface requiring a CMOS input stage, a source-follower buffer, and a switched-capacitor sampling node. The supply is low, the sensor has high source resistance, and the interface must retain accuracy during long standby periods.

Situation and problem

An initial design uses minimum-size, low-threshold transistors to achieve rapid acquisition. Measurements show excessive standby current, a source-follower gain lower than expected, and substantial sampling error when the switch is turned off.

Analysis

The standby current is attributed to subthreshold leakage through low-V_T devices. The source follower is affected by body effect because its source voltage rises above the body potential; the threshold therefore increases and reduces the available V_GS. The sampling error results from charge injection and clock feedthrough through gate–source and gate–drain overlap capacitances. In addition, the sensor resistance and switch on-resistance form an RC network that limits acquisition speed.

Approach and solution

The design team replaces low-V_T devices in noncritical paths with regular- or high-V_T devices and uses power gating for blocks that do not need continuous operation. The source follower is redesigned with a separately controlled well where the process permits it, reducing body-effect variation. The sampling switch is implemented with a complementary transmission gate so that both electron and hole conduction contribute over the input range. A dummy switch and carefully balanced clock routing reduce charge injection and feedthrough. Device dimensions are then selected by jointly considering on-resistance, parasitic capacitance, leakage, and settling time rather than optimizing any one parameter alone.

Outcome

The revised design reduces standby power, improves input-range behavior, and achieves the required settling accuracy. The improvement does not come from a single transistor equation; it results from selecting threshold voltage, body connection, switch topology, geometry, and timing as a coordinated system.

Learning points

The case illustrates four general principles: the off-state is a design condition rather than an ideal zero-current state; body effect must be included whenever source and body potentials differ; capacitances can dominate switching accuracy even when dc resistance is small; and transistor sizing is a multidimensional trade-off involving speed, power, noise, area, and reliability.

Challenges, Errors, and Professional Considerations

Common analytical errors include confusing pinch-off with cutoff, assuming saturation means zero output conductance, ignoring the body terminal, using V_GS rather than V_GS−V_T in current equations, and applying long-channel square-law expressions to short-channel devices without qualification. Another frequent error is selecting a transistor region from a memorized inequality and failing to verify the resulting voltages.

Device parameters vary with manufacturing process, temperature, layout, stress, and aging. Analog designers must consider mismatch and systematic layout effects; digital designers must consider timing corners and leakage corners. Reliability concerns include oxide breakdown, bias-temperature instability, hot-carrier degradation, electromigration in associated interconnects, and soft errors caused by radiation or energetic particles.

Professional practice requires model traceability, corner analysis, design-rule compliance, and measured validation. Semiconductor process information is often proprietary, but engineering decisions must still document assumptions, model versions, operating conditions, and uncertainty. Safety-critical and regulated systems require additional verification, qualification, and change-control procedures.

Current Developments

FET development is moving toward gate-all-around architectures, backside power delivery, improved high-k/metal-gate stacks, two-dimensional channel materials, and three-dimensional integration. These technologies seek improved electrostatic control, reduced parasitic resistance, and greater energy efficiency. Their adoption is constrained by manufacturability, contact resistance, thermal management, defect density, design-tool maturity, and cost.

At the circuit level, adaptive body bias, dynamic threshold control, near-threshold computing, power gating, and energy-aware architecture continue to exploit the relationship between device physics and system requirements. Machine-learning-assisted compact-model extraction and automated transistor sizing are also emerging, but their results remain dependent on the quality of physical models, training data, constraints, and verification.

Best Practices for FET-Based Design

1. Define all terminal voltages and body connections before selecting equations.

2. Check the operating region after solving for the bias point.

3. Use overdrive voltage explicitly and preserve adequate voltage headroom.

4. Include body effect whenever source and body are not at the same potential.

5. Include channel-length modulation when estimating gain or output resistance.

6. Treat capacitances as operating-point-dependent quantities.

7. Examine leakage, temperature, process corners, and aging in addition to nominal behavior.

8. Use compact models and verified process design kits for production decisions.

9. Optimize transistor sizing at the circuit and system levels, not by current alone.

10. Validate simulations with physical constraints, sensitivity analysis, and measurement where possible.

Chapter Summary

FETs regulate channel current through an electric field and are fundamental to modern electronic systems. JFETs demonstrate depletion-controlled conduction through a reverse-biased junction, while MOSFETs use an insulated gate to create or modulate an inversion channel. Long-channel analysis distinguishes cutoff, triode, and saturation regions and provides useful expressions for current, transconductance, and output resistance.

Real devices depart from ideal models because of body effect, channel-length modulation, mobility degradation, velocity saturation, subthreshold conduction, junction and gate leakage, and voltage-dependent capacitances. These effects influence gain, linearity, switching speed, power, and reliability. CMOS uses complementary devices to obtain low static power and strong logic performance, but dynamic, short-circuit, and leakage power must all be considered.

FET design therefore requires a hierarchy of models: physical intuition, large-signal equations, small-signal models, compact simulation models, and experimental verification. Scaling improves density and energy efficiency but introduces electrostatic, thermal, interconnect, variability, and reliability challenges. Sound professional practice combines device physics with circuit-level trade-off analysis.

Key Terms

JFET: A field-effect transistor whose channel is controlled by a reverse-biased p–n junction.

MOSFET: A field-effect transistor with an insulated gate controlling a semiconductor channel.

Inversion layer: A surface region whose carrier type is opposite to that of the semiconductor body.

Threshold voltage: The approximate gate-to-source voltage at which strong inversion begins.

Overdrive voltage: The quantity V_GS−V_T for an nMOS transistor.

Cutoff: The operating condition in which no strong inversion channel exists, though leakage may remain.

Triode region: The MOSFET region in which the channel exists along the source–drain path and the device acts approximately as a voltage-controlled resistor.

Saturation region: The region in which the channel is pinched near the drain and current is primarily controlled by gate overdrive.

Pinch-off: The formation of a depleted channel end near the drain under high drain voltage.

Body effect: Threshold-voltage variation caused by source-to-body bias.

Channel-length modulation: Increase in saturation current caused by reduction of effective channel length with drain voltage.

Subthreshold conduction: Exponential drain current that flows below the nominal threshold voltage.

Transconductance: Incremental change in drain current per change in gate voltage.

Output conductance: Incremental change in drain current per change in drain voltage.

Miller effect: Apparent multiplication of a feedback capacitance by voltage gain.

Velocity saturation: Limitation of carrier velocity at high lateral electric field.

Leakage power: Power consumed by currents flowing when a circuit is nominally inactive.

CMOS: A complementary circuit technology using paired nMOS and pMOS transistors.

FinFET: A three-dimensional MOSFET in which the gate controls a fin-shaped channel from multiple sides.

Compact model: A mathematical device model used in circuit simulators to represent electrical behavior over operating conditions.

Review Questions

Short Answer Questions

1. Why does a MOSFET have very low ideal dc gate current?

2. State the region conditions for an nMOS transistor in terms of V_GS, V_T, and V_DS.

3. Define channel-length modulation and explain its effect on output resistance.

4. What is body effect, and why does it usually increase nMOS threshold voltage?

5. Name three important capacitances that influence MOSFET high-frequency behavior.

Long Answer Questions

1. Explain the physical operation of an n-channel JFET and derive the significance of its pinch-off condition.

2. Derive the long-channel MOSFET current equations for the triode and saturation regions and discuss their assumptions.

3. Explain the origin and circuit consequences of body effect, including its influence on a source follower.

4. Discuss subthreshold conduction, drain-induced barrier lowering, velocity saturation, and other short-channel effects.

5. Describe CMOS inverter operation and analyze its dynamic, short-circuit, and leakage power components.

Analytical / Application Questions

1. An nMOS transistor has V_T=0.5 V, V_GS=1.2 V, and V_DS=0.4 V. Determine its ideal long-channel operating region and explain whether the triode equation or saturation equation should be used.

2. A common-source amplifier uses a transistor with g_m=4 mS and channel-length-modulation output resistance of 25 kΩ. Estimate its intrinsic voltage gain and discuss how increasing channel length would affect the result.

3. A battery-powered CMOS sensor interface suffers from standby leakage and sampling error. Propose a device- and circuit-level redesign, identifying the roles of threshold voltage, body connection, transmission-gate operation, and parasitic capacitance.

22. Multiple Choice Questions with Answers

Question 1

For a long-channel nMOS transistor with V_GS greater than V_T, which condition places it in saturation?

A. V_DS < V_GS − V_T

B. V_DS = 0

C. V_DS ≥ V_GS − V_T

D. V_GS < V_T

Correct Answer: C. V_DS ≥ V_GS − V_T

Question 2

What is the principal circuit consequence of channel-length modulation?

A. Infinite output resistance

B. Finite output resistance in saturation

C. Zero transconductance

D. Elimination of subthreshold current

Correct Answer: B. Finite output resistance in saturation

Question 3

An nMOS source is raised above its body potential while the body remains fixed. What normally happens?

A. Threshold voltage decreases

B. Threshold voltage increases

C. Gate oxide becomes a short circuit

D. Drain current becomes independent of gate voltage

Correct Answer: B. Threshold voltage increases

Question 4

Which expression best represents the long-channel saturation transconductance of an nMOS transistor?

A. g_m = I_D/V_DS

B. g_m = 2I_D/V_OV

C. g_m = V_OV/I_D

D. g_m = λV_DS

Correct Answer: B. g_m = 2I_D/V_OV

Question 5

Why can a low-threshold-voltage MOSFET increase standby power?

A. It eliminates junction capacitance

B. It increases subthreshold leakage when nominally off

C. It prevents inversion formation

D. It removes dynamic switching current

Correct Answer: B. It increases subthreshold leakage when nominally off

Question 6

In an inverting amplifier, why is gate–drain capacitance particularly harmful to bandwidth?

A. It is multiplied by the Miller effect

B. It always becomes zero in saturation

C. It reduces the supply voltage directly

D. It prevents body-effect formation

Correct Answer: A. It is multiplied by the Miller effect

Question 7

In a CMOS inverter with a low input voltage, which device normally conducts?

A. The nMOS pull-down device

B. The pMOS pull-up device

C. Both devices equally in steady state

D. Neither device

Correct Answer: B. The pMOS pull-up device

Question 8

A transistor has V_T=0.6 V, V_GS=1.0 V, and V_DS=0.2 V. Under the long-channel model, which region applies?

A. Cutoff

B. Triode

C. Saturation

D. Breakdown

Correct Answer: B. Triode

Question 9

Which change generally improves electrostatic control in a nanoscale transistor?

A. Making the gate control only one distant surface

B. Using a gate-all-around channel structure

C. Increasing drain-induced barrier lowering

D. Removing the body connection

Correct Answer: B. Using a gate-all-around channel structure

Question 10

For a CMOS circuit, which term describes power proportional to switched capacitance, the square of supply voltage, and frequency?

A. Dynamic power

B. Subthreshold power only

C. Body-effect power

D. Avalanche power

Correct Answer: A. Dynamic power