8. Differential Amplifiers, Current Mirrors and Active Loads

Introduction and Context

Most integrated amplifiers do not rely on discrete resistors and independently biased transistors in the manner of a laboratory circuit. Instead, they use transistor pairs, current sources, current mirrors, and transistor loads to establish operating points and obtain voltage gain within a small silicon area. Three ideas are especially central: the differential pair converts a difference between two input signals into a current difference; the current mirror reproduces a reference current; and the active load converts current variations into voltage variations while often providing high resistance and high gain.

These circuits form the input and gain stages of operational amplifiers, comparators, instrumentation amplifiers, data converters, frequency synthesizers, and many analog integrated systems. Their performance is determined not only by nominal transistor parameters but also by common-mode range, output swing, mismatch, finite output resistance, noise, temperature, process variation, and loading. Consequently, analysis must combine small-signal models with large-signal operating limits and practical layout considerations.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the operation of MOS and BJT differential pairs in large-signal and small-signal modes.

2. Derive differential gain, common-mode gain, common-mode rejection ratio, and input common-mode limits.

3. Analyze basic, cascoded, and improved current mirrors, including their errors and compliance requirements.

4. Explain how active loads increase gain and convert differential currents into single-ended output signals.

5. Evaluate mismatch, finite output resistance, systematic offsets, noise, output swing, and frequency limitations.

6. Select suitable topologies for integrated amplifier and biasing applications.

The Differential Pair as a Transconductance Core

A differential pair consists of two closely matched transistors sharing a tail current source. For a MOS pair, the input voltages are usually written as

v1 = VCM + vid/2,       v2 = VCM − vid/2,

where VCM is the common-mode input voltage and vid is the differential input voltage. The output is represented by the difference between branch currents or by the voltage produced by those currents at a load.

When vid = 0, matched devices carry equal currents. If the tail current is It, each transistor carries approximately It/2. When v1 becomes greater than v2, the first transistor conducts more current and the second conducts less. The pair therefore performs a current-steering operation rather than simply acting as two independent amplifiers.

For a long-channel MOS differential pair with an ideal tail current source and both devices in saturation, the large-signal branch currents are

I1 = It/2 + (It/2)(vid/VOV)√(1 − (vid/2VOV)^2),

I2 = It/2 − (It/2)(vid/VOV)√(1 − (vid/2VOV)^2),

within the range |vid| ≤ √2 VOV. Here VOV is the input-transistor overdrive voltage. The exact expression shows that current steering is nonlinear. For small vid, the square-root term is close to unity, and the incremental differential transconductance is approximately gm/2 in each branch. For sufficiently large positive vid, nearly all tail current flows through the first transistor; for sufficiently large negative vid, it flows through the second.

The small-signal differential gain depends on how the output is taken. With resistive loads RD and an ideal tail source, a single-ended output has approximate gain

Av,se ≈ −gm RD/2,

whereas a differential output can have approximately twice this magnitude, depending on the definition of differential output polarity. In an integrated circuit, RD is frequently replaced by an active load whose small-signal resistance is much larger than a practical on-chip resistor.

Common-Mode Operation

A common-mode input changes both input voltages by the same amount. In an ideal differential pair, this does not change the differential output because both devices experience equal changes. In a real circuit, common-mode gain is produced by finite tail-source resistance, transistor mismatch, unequal loads, and body-effect or channel-length-modulation effects.

The common-mode rejection ratio is

CMRR = |Ad/Ac|,

or, in decibels,

CMRRdB = 20 log10 |Ad/Ac|,

where Ad is differential gain and Ac is common-mode gain. High CMRR requires both a large differential gain and a very small common-mode gain. An ideal tail current source improves CMRR because its large small-signal resistance suppresses changes in total tail current. If the tail source has resistance Rtail, a simplified estimate for a resistively loaded MOS pair is that common-mode gain decreases as Rtail increases, although exact expressions depend on device output resistance, source degeneration, and the output configuration.

The input common-mode range is not unlimited. For an NMOS input pair with an NMOS tail source, the lower common-mode limit must leave sufficient voltage for the tail device and the input transistors to remain in saturation. A useful approximate lower bound is

VCM,min ≈ VSS + VDS,sat,tail + VGS,in,

with refinements required for body effect and process variation. The upper limit is set by the input devices losing saturation or by the load devices reaching their required voltage. PMOS input pairs reverse many of these supply-rail constraints and are useful when input common-mode voltage must approach the lower rail.

Differential-Pair Noise and Offset

The input-referred noise of a differential pair includes channel thermal noise, flicker noise, tail-source noise, and noise from active loads. Increasing transistor area reduces flicker-noise density but increases capacitance. Increasing bias current generally raises gm and reduces voltage noise associated with a given current-noise mechanism, but it increases power consumption.

Mismatch between the pair devices produces an input offset voltage. Mismatch arises from differences in threshold voltage, mobility, oxide thickness, geometry, stress, and local temperature. Random mismatch is commonly reduced by increasing device area according to statistical mismatch relationships such as the Pelgrom model, in which threshold-voltage variance decreases approximately with transistor area. Systematic mismatch is addressed through common-centroid layout, interdigitation, dummy devices, identical orientation, and symmetrical routing.

Current Mirrors: Bias Replication and Current Conversion

A current mirror uses matched transistors so that a reference current establishes a corresponding output current. In the basic MOS mirror, the diode-connected reference transistor has its gate and drain shorted. If both transistors have equal dimensions and operate in saturation, their equal gate-source voltages produce approximately equal drain currents:

Iout ≈ Iref (W/L)out/(W/L)ref.

The mirror is therefore both a biasing element and a current-scaling circuit. It replaces large resistors, provides bias currents at several locations, and permits current-mode signal processing.

The equality is only approximate. The output current depends on output voltage because of channel-length modulation. A first-order expression is

Iout ≈ Iref [1 + λ(Vout − Vref)],

assuming equal nominal dimensions and neglecting other error sources. The output must also remain above a compliance voltage so that the output transistor remains in saturation. For a simple NMOS mirror, this compliance voltage is approximately VOV, although process, current, and accuracy requirements may impose a larger margin.

Mirror Errors

Important error mechanisms include:

• finite output resistance and channel-length modulation;
• threshold-voltage and mobility mismatch;
• unequal drain or source voltages in the two devices;
• finite output resistance of the reference-current generator;
• body-effect differences when source potentials are not identical;
• finite gain and offset of auxiliary amplifiers in regulated mirrors;
• temperature gradients and self-heating.

A designer must distinguish ratio accuracy from absolute accuracy. A mirror may reproduce a current ratio accurately while both currents vary substantially with temperature or supply voltage. Conversely, a bandgap-referenced current can be stable in absolute terms but still suffer from local mismatch between mirror devices.

Improved Mirror Structures

The cascode mirror adds transistors that keep the drain voltages of the mirroring devices relatively constant. This substantially increases output resistance and reduces the effect of channel-length modulation. Its disadvantages are increased voltage headroom, greater area, additional parasitic capacitance, and reduced output swing.

The Wilson mirror uses feedback through an additional transistor to improve output resistance and current accuracy. It can provide high output resistance with less simple dependence on matching of drain voltages than the basic mirror, but it requires additional devices and may introduce signal-path poles.

Wide-swing cascode mirrors rearrange the cascode biasing so that the output compliance voltage is lower than in conventional cascodes. They are valuable in low-voltage CMOS, although the minimum voltage still depends on the required saturation overdrives and device operating conditions.

BJT mirrors have an analogous structure. If the transistors are matched and operate at equal collector-emitter voltages, equal base-emitter voltages produce nearly equal collector currents. Base currents cause a finite error in the simple two-transistor mirror. For a mirror with finite transistor current gain β, the reference current must supply the output current and the base currents, so the output is smaller than the reference current. Wilson and related configurations reduce this error.

Active Loads and High-Gain Stages

An active load is a transistor or transistor network used in place of a resistor. Its small-signal output resistance can be much larger than the resistance obtainable from a practical integrated resistor at the same voltage drop. Since voltage gain is approximately transconductance multiplied by output resistance, active loading is a principal method of obtaining high gain on an integrated circuit.

A differential pair with a current-mirror active load performs two operations simultaneously. First, the mirror copies one branch current into the opposite output branch. Second, the differential current is summed at a single output node. Thus a two-input differential signal can be converted into a single-ended current with an effective transconductance close to gm under suitable matching and polarity conventions. The output resistance is approximately the parallel combination of the output resistances of the input and load transistors, often enhanced by cascoding.

For a simple common-source gain stage,

Av ≈ −gm Rout,

where Rout may include the parallel output resistances of the amplifying transistor and active load. In a cascoded stage, Rout can increase approximately by a factor related to gmro, where ro is the intrinsic transistor output resistance. This gives high gain but consumes voltage headroom and adds poles due to internal high-impedance nodes.

Folded and Telescopic Cascode Stages

Telescopic cascodes stack transistors in the same current path. They offer high gain, low power, and often good speed because fewer current branches are required. Their major limitation is restricted input and output common-mode range due to stacked saturation voltages.

Folded cascodes route signal current into transistors of the opposite polarity rather than stacking all devices directly above the input pair. This improves input common-mode flexibility and can be used with either NMOS or PMOS input devices. The price is additional current consumption, more noise sources, and more internal nodes.

The choice between telescopic, folded, two-stage, and current-mirror-loaded structures is a system-level decision. Gain, speed, output swing, input range, noise, power, stability, and process technology must be considered together rather than optimized independently.

A Structured Analysis Method

A reliable analysis proceeds in stages. First, identify the DC operating point and verify that every transistor assumed to be in saturation, active, or cutoff actually satisfies its region conditions. Second, determine the large-signal current-steering behavior and output swing. Third, replace each transistor by its small-signal model and calculate gm, ro, and any body-effect transconductance. Fourth, derive differential gain, common-mode gain, and output resistance. Finally, check nonidealities, frequency response, mismatch, noise, and worst-case corners.

For a differential amplifier, the following questions are particularly useful:

1. Is the tail source sufficiently ideal over the signal frequency range?

2. What is the input common-mode range at process, voltage, and temperature extremes?

3. Does the output remain within the compliance range of every load and cascode device?

4. Is the output single-ended or differential, and how does that affect gain and CMRR?

5. How are offset and mismatch controlled by sizing and layout?

6. Are internal high-impedance nodes introducing unacceptable poles?

This method prevents a common design error: calculating a large small-signal gain at a bias point that cannot support the required signal swing.

Applied Case: A Low-Voltage CMOS Differential Front End

Background

Consider an illustrative 1.2-V CMOS sensor interface requiring a differential input stage, a single-ended output, moderate bandwidth, and high common-mode rejection. The available voltage is too small for a conventional stack of an input transistor, a tail device, and a high-voltage cascode at both rails.

Situation and Analysis

A PMOS differential input pair is selected because the sensor common-mode voltage is near the lower supply rail. Its tail current is generated by a mirrored bias source. An NMOS current-mirror active load converts the differential branch currents into a single-ended output. The design target is high low-frequency gain, but the output must swing sufficiently to drive a following switched-capacitor stage.

A simple mirror would provide inadequate output resistance and would make gain sensitive to output voltage. A conventional cascode would improve gain but consume too much headroom. The design therefore uses a wide-swing cascode bias arrangement, accepting a modest reduction in output range in exchange for improved gain and CMRR. Devices in the input pair and mirror are laid out with common-centroid symmetry, dummy transistors, and matched source routing.

Approach and Solution

The input-pair overdrive is selected as a compromise: reducing overdrive increases gm for a given current but reduces large-signal differential range and may increase sensitivity to mismatch. The tail source is given sufficient compliance at the lowest supply corner. The active-load mirror is sized so that mismatch-induced current error is small compared with the minimum signal current.

Simulation and measurement planning include supply and temperature sweeps, Monte Carlo mismatch analysis, common-mode sweeps, differential large-signal sweeps, and transient tests with capacitive loading. The gain is checked not only at nominal bias but also at the minimum output voltage, where one of the load devices may approach the edge of saturation.

Outcome

The topology provides high gain in a compact area while preserving more input common-mode flexibility than a simple NMOS input stage. Its principal remaining risks are flicker noise from the relatively large input devices, reduced output swing caused by the wide-swing cascodes, and gain variation caused by finite mirror output resistance.

Learning Points

The case illustrates that no individual topology is universally superior. The input-device polarity, mirror structure, cascode arrangement, and device overdrive must be chosen from the required signal range and supply voltage. Layout symmetry and corner analysis are part of the circuit design, not post-design corrections.

Practical Applications and Industry Relevance

Differential pairs are used in operational-amplifier input stages, comparators, clock receivers, data-converter front ends, sense amplifiers, and phase detectors. Current mirrors establish bias currents in analog and mixed-signal blocks, implement current-steering DACs, and form active loads in gain stages. Cascoded mirrors are used where supply variation and output-voltage dependence must be minimized, whereas low-voltage mirrors are preferred in deeply scaled technologies.

In professional design flows, schematic analysis is followed by process-corner simulation, statistical mismatch analysis, parasitic extraction, layout-versus-schematic verification, and post-layout simulation. Automated sizing tools can search transistor dimensions and bias currents, but the designer must define meaningful objectives and constraints. Optimization based only on nominal gain may produce a circuit with unacceptable yield, swing, or stability.

Limitations, Risks, and Common Design Errors

A frequent mistake is to treat a current mirror as an ideal current source without checking compliance voltage. Another is to calculate differential gain using a resistor-like load while ignoring the signal dependence of a diode-connected or mirror transistor. Assuming perfect matching also leads to unrealistic predictions of offset and CMRR.

High output resistance is not automatically beneficial. It increases gain but creates high-impedance nodes with longer time constants, possibly reducing bandwidth and phase margin. Cascode devices improve gain but reduce swing. Increasing transistor area improves matching and flicker noise but increases capacitance. Increasing current improves speed and often gm, but raises power and may reduce allowable signal range for a fixed supply.

At low supply voltage, stacked devices may leave insufficient voltage for saturation. At high frequency, gate-drain capacitance, mirror internal nodes, and bias-network poles can dominate. At high temperature, mobility generally decreases while leakage and threshold-related behavior change. These effects must be included in design margins.

Professional and Ethical Considerations

Analog integrated-circuit design is safety-relevant when used in medical, automotive, industrial-control, or power-management systems. Claims about gain, accuracy, or common-mode range should be supported by defined test conditions, tolerances, and corner results. Designers should document assumptions, distinguish simulation from measurement, and report failures such as saturation or offset rather than presenting only nominal performance. Reproducible verification, traceable models, and conservative derating are essential professional practices.

Emerging Directions and Best Practices

Modern low-voltage technologies increasingly use inverter-based amplifiers, bulk-driven or body-driven techniques, digitally assisted calibration, and digitally trimmed current references. Calibration can reduce systematic offset and mirror error, but it introduces memory, test-time, power, and reliability considerations. Advanced processes also require attention to layout-dependent effects, well proximity, stress, self-heating, and statistical variation.

Good practice can be summarized as follows:

• establish the DC operating point before performing small-signal analysis;
• verify saturation and compliance at every relevant corner;
• separate differential, common-mode, and large-signal specifications;
• use cascodes only when their gain benefit justifies headroom and poles;
• design for matching through both geometry and symmetry;
• evaluate gain, noise, offset, bandwidth, swing, power, and yield together;
• include extracted parasitics and realistic loading before final judgment.

Chapter Summary

Differential amplifiers translate input voltage differences into controlled current differences and reject signals common to both inputs. Their quality is described by differential gain, common-mode gain, CMRR, input common-mode range, noise, offset, and large-signal linearity. Current mirrors replicate and scale bias currents, but their accuracy is limited by finite output resistance, mismatch, body effect, temperature, and compliance voltage. Active loads replace integrated resistors with high-resistance transistor structures, enabling high gain and single-ended conversion of differential currents. Cascoding improves output resistance but costs voltage headroom, bandwidth, and complexity. Successful design requires simultaneous consideration of operating regions, output swing, frequency response, mismatch, layout, process corners, and application requirements.

Key Terms

Differential pair: Two matched transistors sharing a bias path and responding primarily to the difference between their input voltages.

Tail current: The common bias current supplied to or drawn from a differential pair.

Differential gain: Gain from differential input voltage to differential or specified single-ended output voltage.

Common-mode gain: Gain from a voltage applied equally to both inputs to the output.

CMRR: Ratio of differential gain magnitude to common-mode gain magnitude.

Input common-mode range: Range of average input voltage for which the circuit meets its operating-region requirements.

Current mirror: A transistor network that copies or scales a reference current.

Compliance voltage: Minimum or maximum output voltage required to keep a current-source device in its intended operating region.

Active load: A transistor load used to obtain high small-signal resistance and gain.

Channel-length modulation: Dependence of transistor current on drain voltage in saturation.

Output resistance: Small-signal resistance looking into a circuit output node.

Cascode: A transistor arrangement that increases output resistance by suppressing voltage variation at an internal device terminal.

Wilson mirror: A feedback current mirror that improves output resistance and reduces some mirroring errors.

Overdrive voltage: Gate-source voltage above threshold for a MOS transistor, VGS − VTH.

Input offset voltage: Differential input voltage required to force the nominally zero-differential output condition.

Random mismatch: Device-parameter variation arising from local statistical fabrication differences.

Common-centroid layout: Symmetrical device arrangement used to reduce systematic gradients and mismatch.

Flicker noise: Low-frequency semiconductor noise that is significant in MOS devices and often reduced by increasing area.

Output swing: Permissible output-voltage range before a device leaves its required operating region.

Review Questions

Short Answer Questions

1. Why does a differential pair steer tail current between its two branches?

2. Define CMRR and state why a finite tail-source resistance reduces it.

3. What is the purpose of a current mirror in an integrated circuit?

4. Why does a cascode increase output resistance?

5. State two sources of offset in a differential pair.

Long Answer Questions

1. Derive the small-signal differential gain of a MOS differential pair with resistive loads and explain the difference between single-ended and differential outputs.

2. Explain the operation, errors, and compliance requirements of a basic MOS current mirror.

3. Compare simple, cascode, Wilson, and wide-swing cascode mirrors.

4. Explain how a current-mirror active load converts a differential signal into a single-ended output and increases gain.

5. Discuss the trade-offs among gain, output swing, bandwidth, noise, power, and mismatch in cascoded amplifier stages.

Analytical / Application Questions

1. A differential pair has a tail current of 200 µA and matched devices at zero differential input. Determine the ideal current in each branch. Explain qualitatively what happens as the differential input becomes sufficiently positive.

2. A mirror is required to operate with a low output voltage but high output resistance. Select a suitable mirror topology and justify the choice, including its principal disadvantage.

3. A measured amplifier has high differential gain but poor CMRR and large input offset. Identify likely circuit and layout causes and propose a verification and improvement plan.

22. Multiple Choice Questions with Answers

Question 1

For a matched differential pair with zero differential input and tail current It, the ideal current in each branch is:

A. It

B. It/2

C. 2It

D. Zero

Correct Answer: B. It/2

Question 2

Which change most directly improves the CMRR of a differential pair?

A. Reducing tail-source output resistance

B. Increasing tail-source output resistance

C. Reducing transistor matching

D. Increasing common-mode gain

Correct Answer: B. Increasing tail-source output resistance

Question 3

The principal function of a current mirror is to:

A. Convert voltage directly into frequency

B. Copy or scale a reference current

C. Eliminate all transistor noise

D. Provide infinite output swing

Correct Answer: B. Copy or scale a reference current

Question 4

A simple MOS current mirror deviates from an ideal current source mainly because of:

A. Channel-length modulation and mismatch

B. The absence of gate terminals

C. Infinite output resistance

D. Perfectly equal drain voltages

Correct Answer: A. Channel-length modulation and mismatch

Question 5

The main advantage of an active load over a compact integrated resistor is generally:

A. Lower transistor count

B. Higher small-signal load resistance and gain

C. Zero voltage headroom requirement

D. Complete immunity to mismatch

Correct Answer: B. Higher small-signal load resistance and gain

Question 6

A conventional cascode mirror is often unsuitable in a very low-voltage circuit because it:

A. Requires additional voltage headroom

B. Has no output resistance

C. Cannot mirror DC current

D. Always operates in cutoff

Correct Answer: A. Requires additional voltage headroom

Question 7

If a differential amplifier has high differential gain but also appreciable common-mode gain, its CMRR will be:

A. Improved

B. Unaffected

C. Reduced

D. Infinite

Correct Answer: C. Reduced

Question 8

Which layout technique is especially useful for reducing systematic mismatch in a matched transistor pair?

A. Random placement without symmetry

B. Common-centroid placement with dummy devices

C. Using different orientations and routing lengths

D. Placing one device near a hot digital block

Correct Answer: B. Common-centroid placement with dummy devices

Question 9

Increasing transistor area in a MOS differential pair generally tends to:

A. Reduce flicker noise and random mismatch but increase capacitance

B. Increase mismatch while eliminating capacitance

C. Remove the need for bias current

D. Guarantee infinite bandwidth

Correct Answer: A. Reduce flicker noise and random mismatch but increase capacitance

Question 10

A designer obtains high simulated gain but the output clips for a small signal. The most likely neglected issue is:

A. Output swing and device compliance

B. The definition of resistance

C. The existence of differential input voltage

D. The use of matched devices

Correct Answer: A. Output swing and device compliance