12. CMOS Digital and Mixed-Signal Circuits

Introduction and Context

Complementary metal–oxide–semiconductor (CMOS) technology is the dominant implementation platform for contemporary digital integrated circuits and an important technology for mixed-signal systems. Its success follows from the complementary use of n-channel and p-channel MOSFETs, which enables logic networks with very low static power consumption, high noise immunity, and excellent scalability. Microprocessors, memories, image sensors, communication interfaces, data converters, and system-on-chip devices all depend on CMOS circuit principles.

At postgraduate level, CMOS logic should not be viewed merely as a collection of logic gates. A CMOS circuit is an electrical system whose behavior is determined by transistor sizing, parasitic capacitance, threshold voltage, resistance, supply voltage, loading, process variation, and the interaction between analog and digital signals. A gate that is logically correct may nevertheless be unsuitable because it is too slow, consumes excessive dynamic power, has inadequate noise margin, or injects unacceptable interference into a sensitive analog block.

This chapter develops transistor-level CMOS logic, switching behavior, noise margins, delay, power, fan-out, interfacing, and mixed-signal integration as connected design problems.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain the operation of CMOS inverters and complementary logic networks at transistor level.

2. Derive and interpret voltage-transfer characteristics and noise margins.

3. Estimate propagation delay using resistance–capacitance models.

4. Analyze dynamic, short-circuit, and leakage power.

5. Relate fan-out and capacitive loading to speed and energy.

6. Design and evaluate CMOS NAND, NOR, transmission-gate, tri-state, and sequential interfaces.

7. Identify mixed-signal interference mechanisms and appropriate mitigation methods.

8. Apply these concepts to practical CMOS design decisions and system-level trade-offs.

The CMOS Inverter as the Fundamental Electrical Model

A CMOS inverter contains a pMOS transistor connected between the positive supply, VDD, and the output, and an nMOS transistor connected between the output and ground. Their gates are tied together as the input. When the input is low, the pMOS is on and the nMOS is off, so the output is pulled toward VDD. When the input is high, the pMOS is off and the nMOS is on, so the output is pulled toward ground.

Ideally, one transistor is off in each stable logic state. Consequently, the inverter draws almost no direct current from VDD except during transitions or because of leakage. This distinguishes CMOS from ratioed logic families in which a dc current may flow continuously in one or more logic states.

The voltage-transfer characteristic (VTC) relates output voltage to input voltage. It normally contains five regions: a low-input region in which the pMOS dominates, a transition region in which both devices conduct, a high-input region in which the nMOS dominates, and the limiting regions near the two supply rails. The switching threshold, VM, is approximately the input voltage at which VIN = VOUT. For long-channel devices, a first-order estimate is obtained by equating the drain currents of the two transistors. Device mobility, width-to-length ratio, threshold voltage, and supply voltage influence VM. Increasing the nMOS strength tends to move VM lower, while increasing pMOS strength tends to move it higher.

The slope of the VTC in the transition region is negative. A large magnitude of slope provides regeneration: a moderately degraded logic level is converted into a voltage close to a supply rail. The points at which the magnitude of the slope equals one define the input-low and input-high transition limits, VIL and VIH. The corresponding output limits are VOL and VOH. Noise margins are

NM_L = VIL − VOL

NM_H = VOH − VIH.

For a well-designed inverter, VOH is close to VDD and VOL is close to zero. Large noise margins reduce the probability that coupled noise or supply disturbance will cause an incorrect logic interpretation. However, increasing noise margin, speed, area, and energy efficiency simultaneously is not always possible; transistor sizing and supply selection create trade-offs.

Complementary Logic Networks

A CMOS gate is constructed from a pull-up network (PUN) of pMOS transistors and a pull-down network (PDN) of nMOS transistors. The networks are duals. The PDN conducts when the output Boolean function is true, pulling the output low; the PUN conducts for the complementary condition, pulling the output high.

In a two-input NAND gate, the nMOS devices are in series and the pMOS devices are in parallel. The output is low only when both inputs are high. In a two-input NOR gate, the nMOS devices are in parallel and the pMOS devices are in series. The output is high only when both inputs are low. Series devices increase effective resistance and therefore affect delay. A NOR gate generally has a weaker pull-up path because of series pMOS devices, while a NAND gate generally has a weaker pull-down path because of series nMOS devices.

Transistor sizing compensates partially for these differences. Since hole mobility is lower than electron mobility in typical CMOS processes, pMOS devices are often made wider than nMOS devices to obtain comparable drive strength. The appropriate ratio depends on the process, layout, voltage range, and performance target. Excessive sizing reduces resistance but increases gate and diffusion capacitance, which can slow preceding stages and increase dynamic power.

Complex gates can be designed directly from Boolean expressions. A product term is represented naturally by series nMOS transistors, while a sum of terms is represented by parallel branches. The complementary pMOS network is then constructed by applying the dual transformation: series in one network corresponds to parallel in the other. Logic factoring is valuable because it can reduce transistor count, internal capacitance, and delay.

Switching Characteristics and Propagation Delay

A CMOS output drives capacitance arising from transistor gates in the next stage, interconnect, source and drain junctions, and measurement or package structures. During a transition, this capacitance must be charged or discharged. A first-order delay model is

t_p ≈ 0.69 R_eq C_L,

where R_eq is the effective resistance of the conducting network and C_L is the total load capacitance. The low-to-high and high-to-low delays need not be equal because pMOS and nMOS networks have different resistances. The average propagation delay is commonly approximated as

t_p = (t_PLH + t_PHL)/2.

The output transition time, or rise/fall time, is related to the same resistance–capacitance process. A long interconnect can dominate C_L, making physical design as important as transistor sizing. A gate may therefore become slower even when its schematic has not changed.

The logical-effort viewpoint provides a useful higher-level method. A gate’s delay can be represented approximately as the sum of an intrinsic parasitic delay and a load-dependent effort delay. When a large load must be driven, several progressively larger inverters may be inserted. The optimum number of stages balances the extra parasitic capacitance against the reduction in effort per stage. In practice, buffering is selected using timing constraints, area limits, power budgets, and library characterization rather than a single universal factor.

Input transition time also matters. If an input changes slowly, both the pMOS and nMOS may remain partially on for a significant interval. This increases short-circuit current and can produce timing uncertainty. Therefore, a digital interface must be evaluated not only by logic levels but also by signal slew.

Power Consumption and Energy Efficiency

CMOS power has three principal components. Dynamic switching power results from charging and discharging capacitance:

P_dynamic = α C_L VDD² f,

where α is the activity factor, C_L is switched capacitance, VDD is supply voltage, and f is the switching frequency. A complete charge–discharge cycle dissipates approximately C_LVDD² from the supply, although only part of that energy is stored at any instant.

Short-circuit power occurs during an input transition when both pull-up and pull-down networks conduct simultaneously. It increases with slow input edges, large device widths, high supply voltage, and unsuitable threshold-voltage relationships. Good input slew control and balanced transistor sizing reduce it.

Leakage power is increasingly important in scaled technologies. Subthreshold conduction occurs when a transistor is nominally off; gate leakage can arise through a thin dielectric; and reverse-biased junctions contribute additional leakage. Lowering threshold voltage improves speed but increases subthreshold leakage. High-threshold devices, power gating, body biasing, transistor stacking, and state-retention methods are used to manage standby power.

Energy per operation and average power are not identical design objectives. A circuit may reduce active energy while increasing wake-up time, or reduce leakage while increasing switching energy. Low-power design therefore begins with architectural activity reduction, followed by voltage scaling, capacitance reduction, controlled clocking, and device-level optimization.

Fan-Out, Loading, and Signal Integrity

Fan-out is often described as the number of standard logic inputs driven by one output. This definition is convenient for a logic family, but the physically meaningful quantity is capacitive load. Each receiving gate contributes input capacitance, while interconnect contributes distributed capacitance and resistance.

A high fan-out increases delay because the driver must charge and discharge more capacitance. It also increases dynamic power. A heavily loaded node may require a buffer tree, careful wire planning, or a change in logic partitioning. The buffer tree itself consumes area and power, so it should be introduced only when its timing benefit justifies its cost.

Signal integrity problems include crosstalk, ground bounce, supply droop, ringing, and simultaneous-switching noise. Wider wires reduce resistance but increase coupling area; shielding reduces coupling but consumes routing resources. Decoupling capacitors stabilize local supplies, although they must be placed and sized with package and interconnect inductance in mind.

Transmission Gates, Tri-State Drivers, and Sequential Elements

A single nMOS passes a strong zero but a degraded one because its output cannot rise above approximately VDD − VTN. A single pMOS exhibits the complementary limitation for a low output. A transmission gate uses parallel nMOS and pMOS devices controlled by complementary signals. It passes both logic levels with substantially reduced threshold loss and is useful in multiplexers, sample-and-hold circuits, bus switches, and latch structures.

A tri-state driver adds a high-impedance state, allowing several devices to share a bus provided that only one driver is enabled at a time. Bus contention can produce large current, signal distortion, and reliability stress. Modern systems often replace shared tri-state buses with multiplexed or point-to-point interconnects, but tri-state structures remain important in memory and interface circuits.

A static CMOS latch or flip-flop stores information using feedback inverters. Its design must satisfy setup time, hold time, clock-to-Q delay, and recovery/removal constraints. A violation can cause metastability, in which the stored node remains temporarily between valid logic levels. Synchronizer chains reduce the probability that metastability propagates into a receiving clock domain, although they cannot eliminate the underlying physical phenomenon.

CMOS Mixed-Signal Interfaces

Mixed-signal systems combine analog blocks—such as amplifiers, oscillators, sensors, and data converters—with digital processing and control. The principal difficulty is that digital circuits generate large, fast current transients while analog circuits are sensitive to small voltage and substrate disturbances.

Important coupling paths include:

• shared supply and ground impedance;
• capacitive and inductive coupling through interconnect;
• substrate and well coupling;
• clock feedthrough and charge injection;
• electromagnetic radiation and package coupling; and
• reference-voltage disturbance caused by converter switching.

A robust design separates noisy and sensitive regions physically while maintaining a deliberate grounding and return-current strategy. Separate analog and digital supply domains may be used, but they must be connected in a controlled manner; simply naming supplies “analog” and “digital” does not prevent coupling. Guard rings, deep-well structures, differential signaling, shielding, common-centroid layout for matched devices, local decoupling, low-noise references, and clock isolation are common techniques.

Digital control of analog circuits introduces additional concerns. A digital code may change several bits simultaneously, producing transient glitches at a resistor-string DAC or capacitor DAC. Gray coding, thermometer coding, synchronized updates, and output registers can reduce code-transition errors. In ADCs, aperture uncertainty, comparator kickback, reference noise, and digital return currents influence effective resolution.

The signal-to-noise-and-distortion ratio (SNDR), effective number of bits (ENOB), spurious-free dynamic range, and total harmonic distortion are system-level measures that connect transistor behavior to converter performance. For an ideal N-bit ADC, quantization-limited SNDR is approximately 6.02N + 1.76 dB, but practical CMOS systems are usually limited by thermal noise, clock jitter, nonlinearity, reference error, and interference before reaching this ideal value.

An Illustrative Design Case: Low-Power Sensor Interface

Background

Consider an illustrative CMOS sensor node containing a low-noise analog front end, a successive-approximation ADC, and a digital controller. The system operates from a low supply and spends most of its time in standby.

Situation and Problem

Initial prototypes meet the functional specification, but the measured ADC performance varies whenever the digital controller changes state. The degradation is greatest during conversion, when the SAR logic switches rapidly. Standby current is also higher than expected.

Analysis

The digital transitions produce supply and substrate disturbances that couple into the comparator and reference network. The ADC’s capacitive switching generates transient reference current, while the controller’s clock drives a large load. In standby, leakage through always-on logic and an insufficiently isolated analog bias circuit dominate consumption. The problem is therefore not a single faulty transistor; it is an interaction among switching activity, impedance, layout, clocking, and power management.

Approach

The design team adopts several measures. The SAR logic is placed away from the comparator and reference circuits, with guard rings and separate local supply filtering. The reference network receives dedicated decoupling and a controlled return path. Digital activity is reduced through clock gating, and a smaller, staged clock driver replaces a single oversized driver. The ADC output is registered so that code transitions do not directly disturb the analog sampling interval. High-threshold devices are used in noncritical always-on logic, while power gating disables inactive blocks.

Outcome

The revised architecture reduces switching disturbance and standby current while preserving conversion speed. The result illustrates an important engineering principle: mixed-signal performance is determined by circuit topology, physical implementation, timing strategy, and power architecture together.

Learning Points

1. Logic correctness does not guarantee analog compatibility.

2. Reducing activity can be more effective than merely reducing transistor size.

3. Supply, substrate, clock, and reference networks must be analyzed as coupled systems.

4. Power gating and threshold selection must account for wake-up and retention requirements.

Design Challenges, Risks, and Common Mistakes

A frequent mistake is to treat a logic-1 or logic-0 as an ideal voltage independent of load. Real outputs have finite resistance and transition time. Another mistake is to use only nominal simulation results. Process, voltage, and temperature corners can alter delay, leakage, switching threshold, and noise margin substantially.

Designers should also avoid indiscriminate transistor upsizing. Larger devices improve drive capability but increase input capacitance, internal capacitance, area, clock load, and short-circuit current. Floating CMOS inputs are another serious hazard: they can assume unpredictable voltages, increase static current, and make the circuit susceptible to noise. Unused inputs should be tied to defined logic levels or handled using an appropriate termination strategy.

Dynamic logic, pass-transistor logic, and aggressively reduced-voltage operation can provide speed or area advantages, but they require careful treatment of charge sharing, leakage, clock sequencing, degraded levels, and noise sensitivity. Reliability issues include electromigration, hot-carrier effects, bias-temperature instability, dielectric breakdown, and latch-up. Design-rule checking, electrical-rule checking, layout-versus-schematic verification, parasitic extraction, and corner-based sign-off are essential professional practices.

Professional and Governance Considerations

CMOS design is subject to product reliability, safety, electromagnetic-compatibility, and quality requirements. In automotive, medical, aerospace, and industrial applications, verification must address fault behavior, operating extremes, lifetime degradation, and traceability. A designer should document assumptions about voltage domains, reset behavior, clock-domain crossings, power sequencing, and undefined states.

Security is also relevant. Power and electromagnetic signatures may reveal information about cryptographic operations. Countermeasures include balanced logic, masking, controlled routing, noise generation, and careful physical isolation, although each introduces area, power, or verification costs. Design decisions should be evaluated not only for nominal performance but also for unintended information leakage and failure modes.

Current Developments and Best Practices

Modern CMOS systems increasingly use three-dimensional integration, chiplets, advanced packaging, near-threshold operation, nonvolatile embedded memory, and digitally assisted analog calibration. Machine-learning accelerators depend on massive parallel switching and therefore emphasize data movement, clock distribution, and energy per operation as much as arithmetic throughput. FinFET and gate-all-around transistor structures improve electrostatic control, but they do not remove the fundamental relationships among capacitance, voltage, resistance, noise, and power.

Useful best practices include:

• define logic thresholds and voltage domains explicitly;
• characterize delay, power, and noise over process, voltage, and temperature corners;
• minimize unnecessary switching activity;
• use staged drivers for large capacitive loads;
• control input slew and avoid floating nodes;
• verify clock-domain and power-domain crossings;
• plan analog/digital floorplanning before detailed layout;
• extract parasitics before final timing and noise assessment; and
• treat verification, reliability, and documentation as parts of design rather than afterthoughts.

Chapter Summary

CMOS circuits implement logic through complementary pMOS pull-up and nMOS pull-down networks. The CMOS inverter establishes the essential relationships among voltage transfer, switching threshold, noise margin, resistance, capacitance, and delay. NAND and NOR structures follow dual-network principles, while transistor sizing determines drive strength and loading.

Propagation delay is governed approximately by effective resistance and load capacitance. Power consists chiefly of dynamic switching power, short-circuit power, and leakage power. Fan-out, interconnect, signal slew, and supply integrity strongly affect practical behavior. Transmission gates, tri-state drivers, and sequential circuits extend CMOS logic into multiplexing, buses, storage, and clocked systems.

Mixed-signal integration requires control of supply, substrate, clock, reference, and interconnect coupling. Successful designs combine transistor-level optimization with architectural activity reduction, physical separation, power management, verification across corners, and reliability-aware implementation.

Key Terms

CMOS: Logic technology using complementary pMOS and nMOS transistors.

Pull-up network: pMOS network that connects an output to VDD.

Pull-down network: nMOS network that connects an output to ground.

Voltage-transfer characteristic: Relationship between a gate’s input and output voltages.

Switching threshold: Input voltage near which the inverter changes logic state.

Noise margin: Allowable noise voltage before a valid logic level is misinterpreted.

Fan-out: Electrical loading imposed by receiving gates and interconnect on a driver.

Propagation delay: Time between a specified input transition and corresponding output transition.

Dynamic power: Power associated with charging and discharging capacitances.

Short-circuit power: Power conducted while pull-up and pull-down devices overlap in conduction.

Leakage power: Power consumed by currents when transistors are intended to be off.

Transmission gate: Complementary nMOS–pMOS switch that passes both logic levels effectively.

Tri-state driver: Driver capable of producing logic low, logic high, or high impedance.

Metastability: Temporarily unresolved state caused by violation of storage timing conditions.

Clock-domain crossing: Transfer of signals between circuits using different clocks.

Substrate coupling: Noise transfer through the semiconductor substrate or wells.

Charge injection: Unwanted charge transferred when a switching transistor changes state.

ENOB: Effective number of bits representing practical ADC resolution.

Power gating: Technique that disconnects inactive circuitry from a supply or ground path.

Parasitic capacitance: Unintended capacitance arising from devices, junctions, and interconnect.

Review Questions

Short Answer Questions

1. Why does a static CMOS inverter ideally consume negligible dc power in a stable logic state?

2. Define high and low noise margins for a CMOS inverter.

3. Why are pMOS transistors commonly wider than nMOS transistors?

4. What physical factors contribute to the load capacitance of a CMOS gate?

5. State the three principal components of CMOS power consumption.

Long Answer Questions

1. Explain the operation of a CMOS inverter and discuss how transistor sizing affects its voltage-transfer characteristic.

2. Derive the qualitative delay behavior of a CMOS gate using the resistance–capacitance model.

3. Compare CMOS NAND and NOR gates with respect to transistor arrangement, drive strength, and delay.

4. Explain the sources of interference in mixed-signal CMOS systems and describe suitable layout and circuit remedies.

5. Discuss the operation and applications of transmission gates, tri-state drivers, and CMOS storage elements.

Analytical / Application Questions

1. A CMOS output must drive a large capacitive load at high frequency. Explain the trade-offs between using one large driver and a multistage buffer chain.

2. An ADC shows degraded performance whenever a digital controller changes state. Analyze at least four possible coupling mechanisms and propose a verification plan.

3. A battery-operated sensor spends 99% of its time asleep. Recommend circuit- and architecture-level techniques to reduce both standby leakage and wake-up energy, explaining their trade-offs.

22. Multiple Choice Questions with Answers

Question 1

In a static CMOS inverter with a stable low input, which condition is correct?

A. The nMOS is on and the pMOS is off.

B. Both transistors are permanently on.

C. The pMOS is on and the nMOS is off.

D. Both transistors are off and the output floats.

Correct Answer: C. The pMOS is on and the nMOS is off.

Question 2

For a CMOS inverter, increasing the strength of the nMOS relative to the pMOS generally causes the switching threshold to:

A. Move toward a lower input voltage

B. Move toward a higher input voltage

C. Become exactly equal to VDD

D. Become independent of transistor sizing

Correct Answer: A. Move toward a lower input voltage

Question 3

Which expression is the usual first-order estimate for CMOS propagation delay?

A. tp = VDD/(RC)

B. tp ≈ 0.69 ReqCL

C. tp = αCLVDD²f

D. tp = CL/(ReqVDD)

Correct Answer: B. tp ≈ 0.69 ReqCL

Question 4

A two-input CMOS NAND gate uses which transistor arrangement in its pull-down network?

A. Two nMOS transistors in parallel

B. Two pMOS transistors in series

C. Two nMOS transistors in series

D. One nMOS and one pMOS in parallel

Correct Answer: C. Two nMOS transistors in series

Question 5

If the switched capacitance and frequency remain constant while VDD is reduced by 20%, dynamic power approximately becomes:

A. 80% of its original value

B. 64% of its original value

C. 20% of its original value

D. 125% of its original value

Correct Answer: B. 64% of its original value

Question 6

Why is a transmission gate preferable to a single nMOS transistor for passing a full logic swing?

A. It eliminates all leakage current.

B. It uses complementary devices to reduce threshold-voltage signal loss.

C. It operates without a control signal.

D. It always provides infinite output resistance.

Correct Answer: B. It uses complementary devices to reduce threshold-voltage signal loss.

Question 7

Which condition most directly increases short-circuit power in a CMOS gate?

A. A very fast input transition

B. A slow input transition causing simultaneous conduction

C. A completely static input at ground

D. Removal of all load capacitance

Correct Answer: B. A slow input transition causing simultaneous conduction

Question 8

A high fan-out primarily increases a driver’s:

A. Threshold voltage only

B. Load capacitance and dynamic delay

C. Logical function

D. Noise margin to an unlimited value

Correct Answer: B. Load capacitance and dynamic delay

Question 9

Which technique is most directly useful for reducing digital switching interference in a sensitive analog block?

A. Placing the clock driver beside the comparator

B. Increasing simultaneous switching activity

C. Using physical isolation, controlled returns, and local decoupling

D. Leaving analog inputs electrically floating

Correct Answer: C. Using physical isolation, controlled returns, and local decoupling

Question 10

A setup or hold-time violation in a flip-flop can produce:

A. Metastability

B. Guaranteed zero delay

C. Permanent short-circuit isolation

D. An increase in ideal ADC quantization resolution

Correct Answer: A. Metastability