6. Biasing, Thermal Stability and Device Variability

Introduction and Context

A transistor amplifier is not defined only by its small-signal gain. Its operating point determines whether amplification is linear, whether the device remains within safe operating limits, and how reliably the circuit performs when temperature, manufacturing process, supply voltage, and component values change. Biasing is therefore the bridge between a transistor’s device physics and its practical circuit function.

For a BJT, the collector current depends strongly on base-emitter voltage, current gain, and temperature. For a MOSFET, the drain current depends on threshold voltage, mobility, geometry, and bias conditions. These parameters are neither perfectly constant nor identical from one device to another. A bias network that works only for nominal parameter values is not a robust design.

This chapter develops a systematic approach to bias design. It begins with load-line analysis and operating-point selection, then examines thermal runaway, stabilization techniques, sensitivity and tolerance analysis, and Monte Carlo methods. The discussion applies particularly to discrete transistor circuits, but the reasoning also supports integrated-circuit bias design and analog system verification.

Learning Objectives

After completing this chapter, the reader should be able to:

1. Explain the purpose of biasing and identify the quiescent operating point.

2. Construct and interpret DC load lines for BJT and MOSFET circuits.

3. Compare common biasing arrangements using sensitivity and stability criteria.

4. Explain thermal runaway and calculate temperature-related changes in operating point.

5. Design emitter, source, collector-feedback, and current-source compensation networks.

6. Distinguish temperature variation, process variation, mismatch, and component tolerance.

7. Use sensitivity coefficients, worst-case analysis, and Monte Carlo simulation to assess robustness.

8. Select practical bias strategies subject to performance, power, area, and reliability constraints.

The Operating Point as a Design Decision

Biasing establishes the quiescent or Q-point: the DC values of currents and voltages when no signal is applied. When an AC signal is superimposed on this point, the instantaneous operating point moves along the transistor characteristics. A satisfactory Q-point must provide sufficient signal swing, acceptable distortion, and operation inside the device’s safe operating area.

For a common-emitter BJT stage with collector resistance \(R_C\), emitter resistance \(R_E\), and supply \(V_{CC}\), the approximate DC relationship is

\[

V_{CC}=I_C R_C+V_{CE}+I_E R_E.

\]

Since \(I_E\approx I_C\) for a transistor with large current gain,

\[

V_{CE}\approx V_{CC}-I_C(R_C+R_E).

\]

This equation is the DC load line. Its intercepts are approximately \(V_{CE}=V_{CC}\) when \(I_C=0\), and \(I_C=V_{CC}/(R_C+R_E)\) when \(V_{CE}=0\). The actual transistor characteristic intersects this line at the Q-point.

For a MOSFET drain circuit with source resistance \(R_S\),

\[

V_{DD}=I_D R_D+V_{DS}+I_D R_S,

\]

so that

\[

V_{DS}=V_{DD}-I_D(R_D+R_S).

\]

The load line is independent of the detailed MOSFET current equation, whereas the characteristic curves depend on threshold voltage, transconductance parameter, channel-length modulation, and operating region.

A midpoint Q-point is often selected for approximately symmetrical voltage swing, but this is not a universal rule. If the output is transformer-coupled, resistively loaded, or required to deliver asymmetric signal excursions, the optimum point may differ from the geometric midpoint. Bias design must therefore begin with the required signal range and device limits rather than with a memorized voltage rule.

Biasing Arrangements and Their Stabilizing Mechanisms

Fixed Bias and Its Limitations

In fixed-bias BJT circuits, a resistor supplies base current from a voltage source. The approximate collector current is

\[

I_C=\beta I_B.

\]

This relation exposes the weakness of the arrangement: any change in current gain \(\beta\) produces a proportional change in collector current. The base-emitter voltage also varies with temperature, and transistor leakage contributes additional current. Fixed bias is useful for illustrating transistor operation and for some switching circuits, but it is rarely satisfactory for a precision amplifier.

Collector-to-Base Feedback Bias

Connecting the bias resistor from collector to base introduces negative feedback. If collector current rises, collector voltage falls; the reduced collector voltage lowers base current and opposes the original change. This arrangement is more stable than fixed bias, although the feedback also couples signal voltage into the bias node and can reduce gain unless carefully designed.

Voltage-Divider Bias with Emitter Degeneration

A widely used BJT network derives base voltage from a resistor divider and places an emitter resistor in series with the emitter. Replacing the divider by its Thévenin equivalent gives

\[

V_{TH}=V_{CC}\frac{R_2}{R_1+R_2}, \qquad R_{TH}=R_1\parallel R_2.

\]

The base current is approximately

\[

I_B=\frac{V_{TH}-V_{BE}}{R_{TH}+(\beta+1)R_E},

\]

and

\[

I_C=\beta I_B.

\]

The term \((\beta+1)R_E\) in the denominator is central. If it is much larger than \(R_{TH}\), variations in \(\beta\) have a reduced effect on current. The emitter voltage rises when current rises, increasing the voltage across the base-emitter junction in the opposing direction and thereby providing local negative feedback.

The price of stabilization is reduced voltage gain. In a common-emitter stage, the unbypassed emitter resistance approximately contributes to the small-signal degeneration factor

\[

A_v\approx -\frac{g_m R_C}{1+g_m R_E},

\]

subject to loading and hybrid-pi effects. An emitter bypass capacitor can restore AC gain while retaining DC stabilization, but its finite impedance, tolerance, leakage, and frequency dependence must be considered.

A practical divider must also be designed so that its Thévenin resistance is not excessively large compared with \((\beta+1)R_E\). Making divider current unnecessarily high improves bias stiffness but increases power dissipation. The design is therefore a trade-off between stability, loading, noise, power, and component size.

MOSFET Bias and Source Degeneration

The apparent advantage of MOSFET biasing is that gate current is ideally zero. However, gate-source voltage and threshold voltage vary significantly between devices, so a fixed gate voltage does not guarantee a fixed drain current. A source resistor provides feedback. If drain current increases, source voltage increases, reducing \(V_{GS}\) and opposing the increase.

For a divider-biased NMOS,

\[

V_{GS}=V_G-I_D R_S,

\]

and the Q-point is found by intersecting this relation with the MOSFET transfer characteristic. In saturation, a simplified long-channel model is

\[

I_D=\frac{1}{2}k_n(V_{GS}-V_{TH})^2,

\]

although real devices require allowance for channel-length modulation, mobility variation, body effect, and process-dependent parameters.

Current-Mirror and Active Bias Networks

Integrated circuits commonly use current mirrors, beta multipliers, bandgap references, and cascode structures to establish bias currents. These circuits can achieve good supply rejection and compact implementation, but they introduce systematic error, mismatch, start-up requirements, compliance-voltage limits, and sensitivity to process corners. A current mirror that is accurate at one output voltage may exhibit substantial error when finite output resistance is included.

Thermal Stability and Thermal Runaway

Transistor temperature affects both the device parameters and the surrounding resistive network. In a BJT, increasing temperature generally reduces \(V_{BE}\) at a specified current and increases reverse saturation current. If the bias network allows collector current to rise, transistor power \(P_D\approx V_{CE}I_C\) may rise, increasing junction temperature further. This positive feedback is thermal runaway.

A useful first-order thermal model is

\[

T_J=T_A+\theta_{JA}P_D,

\]

where \(T_J\) is junction temperature, \(T_A\) ambient temperature, and \(\theta_{JA}\) the junction-to-ambient thermal resistance. For packaged devices, a more detailed model may include junction-to-case and case-to-heatsink resistances.

Thermal stability can be expressed through a loop-gain idea. Let a temperature increase produce a current change \(\partial I_C/\partial T\), and let current change produce power change \(\partial P_D/\partial I_C\). The thermal feedback magnitude is approximately

\[

L_T=\theta_{JA}\frac{\partial P_D}{\partial I_C}\frac{\partial I_C}{\partial T}.

\]

A stable operating point requires the effective positive feedback to remain below unity after electrical feedback is included. This expression is approximate, but it encourages the correct design question: how strongly does temperature-induced current change increase dissipated power, and how effectively does the bias network oppose it?

Emitter resistance is particularly effective because the temperature-induced increase in current causes an additional emitter voltage drop. Thermal compensation may also use diodes or transistor junctions mounted near the power device, thermistors, active feedback, or regulated current sources. Compensation components must track the transistor thermally; a diode located far from the transistor may have the correct nominal temperature coefficient but poor dynamic tracking.

The safe operating area must be checked in addition to average power. Bipolar power transistors can exhibit secondary breakdown, and semiconductor junctions have maximum voltage, current, and temperature ratings. A bias network that is mathematically stable may still violate transient or long-term reliability limits.

Device Variability: Temperature, Process, Tolerance and Mismatch

Variability has several distinct sources. Temperature variation occurs during operation and may be predictable over the rated ambient range. Process variation arises from wafer fabrication and is often represented by slow, typical, and fast corners. Component tolerance describes resistor, capacitor, and reference-value uncertainty. Mismatch is the random difference between nominally identical nearby devices and is especially important in integrated circuits.

For BJTs, \(\beta\), \(V_{BE}\), leakage, and saturation parameters vary. For MOSFETs, threshold voltage \(V_{TH}\), mobility, oxide-related parameters, channel dimensions, and output resistance vary. In discrete circuits, resistor tolerance and supply tolerance may dominate; in integrated circuits, mismatch and process corners are often more influential.

Sensitivity quantifies how strongly an output responds to a parameter. The normalized sensitivity of quantity \(Y\) to parameter \(X\) is

\[

S_X^Y=\frac{X}{Y}\frac{\partial Y}{\partial X}.

\]

A value of 0.2 means that a 1% change in \(X\) produces approximately a 0.2% change in \(Y\), locally. Sensitivity is a local measure and should not be confused with a guaranteed worst-case bound.

For independent small variations, the variance of an output can be approximated by

\[

\sigma_Y^2\approx \sum_i\left(\frac{\partial Y}{\partial X_i}\right)^2\sigma_{X_i}^2.

\]

This root-sum-square approach is useful for statistical prediction. Worst-case analysis instead adds appropriately signed maximum deviations and is more conservative, though often pessimistic because all extremes rarely occur simultaneously.

A Structured Bias-Design Workflow

A robust design process begins by specifying the required quiescent current, voltage swing, gain, bandwidth, noise, power dissipation, and operating temperature range. The designer then selects a nominal Q-point using load-line analysis and checks cutoff, saturation, pinch-off, or compliance limits.

Next, the bias equations are solved with nonideal device parameters. The design should not rely on a single nominal value of \(\beta\) or \(V_{TH}\). Sensitivity calculations identify which parameters dominate uncertainty. Feedback resistors, emitter or source degeneration, regulated references, or servo loops can then be introduced where needed.

The design is subsequently tested under:

• supply-voltage minimum and maximum;
• resistor and reference tolerances;
• temperature extremes;
• semiconductor process corners;
• device mismatch, where relevant;
• startup and power-down conditions;
• load changes and signal transients.

Simulation should be followed by measurement. A useful laboratory plan measures Q-point current and voltage at several ambient temperatures and supply values, then compares the results with predicted tolerances. Correlation often reveals wiring resistance, thermal coupling, model limitations, or component-temperature effects that a schematic-only analysis misses.

Worked Example: Stabilized BJT Bias

Consider an NPN common-emitter stage with \(V_{CC}=12\text{ V}\), \(R_C=2.2\text{ k}\Omega\), \(R_E=1.0\text{ k}\Omega\), \(R_1=82\text{ k}\Omega\) from supply to base, and \(R_2=18\text{ k}\Omega\) from base to ground. Assume \(V_{BE}=0.70\text{ V}\) and nominal \(\beta=100\).

The Thévenin voltage and resistance are

\[

V_{TH}=12\frac{18}{100}=2.16\text{ V},

\]

\[

R_{TH}=82\parallel18\approx14.76\text{ k}\Omega.

\]

Thus,

\[

I_B=\frac{2.16-0.70}{14.76\text{ k}\Omega+101(1.0\text{ k}\Omega)}\approx12.6\ \mu\text{A},

\]

so \(I_C\approx1.26\text{ mA}\), \(I_E\approx1.27\text{ mA}\), and

\[

V_{CE}\approx12-(1.26\text{ mA})(2.2\text{ k}\Omega)-(1.27\text{ mA})(1.0\text{ k}\Omega)\approx7.95\text{ V}.

\]

The stage is therefore in the active region with useful voltage headroom. If \(\beta\) falls to 50, the collector current decreases, but the change is moderated by the emitter resistor. The exact result should be recalculated rather than estimated solely from the proportional relation \(I_C=\beta I_B\), because base current itself changes through the feedback network.

Illustrative Case Study: Bias Drift in an Industrial Sensor Amplifier

Background

An illustrative industrial sensor interface uses a discrete BJT differential preamplifier followed by a voltage-gain stage. The circuit must operate from a 15 V supply over an ambient range of 0°C to 60°C. Initial prototypes meet gain specifications at room temperature but show output offset drift and occasional clipping after prolonged operation.

Situation and Analysis

Measurements show that one transistor’s collector current increases as the enclosure warms. The original design uses a high-value base-bias resistor and no emitter degeneration. Device samples with higher \(\beta\) draw substantially more current, and the resulting dissipation raises junction temperature. The output stage then approaches saturation on positive signal peaks.

A load-line plot confirms that the nominal Q-point is too close to the saturation boundary. Temperature measurements reveal that the transistor junction is considerably warmer than the enclosure, so using ambient temperature alone underestimates the thermal effect. A tolerance analysis identifies the base-bias resistor and transistor \(\beta\) as dominant contributors to current variation.

Strategy and Solution

The engineering team replaces the fixed-bias network with a voltage divider and emitter resistor. The divider is made sufficiently stiff for the chosen emitter resistance without imposing excessive current. A bypass capacitor is added only to the AC path required for gain, and its low-temperature capacitance is included in the bandwidth check. The Q-point is moved toward the centre of the usable load line, increasing saturation margin.

A thermal simulation is performed at low, nominal, and high transistor parameter corners. A Monte Carlo run includes resistor tolerances and statistical device variation. Finally, prototypes are tested in a temperature chamber while collector current, junction-proxy temperature, gain, and output headroom are recorded.

Outcome

The revised circuit exhibits lower Q-point spread, improved output symmetry, and reduced temperature-dependent offset. The design still requires production screening because the application has a narrow calibration budget, but screening is now correcting small residual errors rather than compensating for an unstable bias architecture.

Learning Points

The case demonstrates that bias stability is a system property. It depends on electrical feedback, thermal resistance, parameter distributions, signal headroom, and measurement conditions. A nominally correct operating point is not sufficient evidence of robust design.

Monte Carlo Analysis and Digital Design Tools

Monte Carlo analysis assigns probability distributions to uncertain parameters and repeatedly solves the circuit. The resulting histogram of collector current, gain, offset, or power dissipation estimates yield and statistical spread. It is particularly useful when several moderate uncertainties interact nonlinearly.

A sound Monte Carlo study requires justified distributions. A resistor specified at ±1% should not automatically be assigned a Gaussian distribution with unlimited tails; the manufacturer’s tolerance definition and production data should guide the model. Correlations must also be considered. For example, parameters on the same die may vary together, whereas independent discrete resistors may be approximately uncorrelated.

Corner analysis and Monte Carlo serve different purposes. Corners test deliberate combinations of extreme process and environmental conditions. Monte Carlo estimates statistical behaviour around distributions. Neither replaces physical understanding. Simulation results are only as credible as the transistor models, thermal model, parameter distributions, and circuit assumptions.

Modern electronic-design-automation tools can automate DC operating-point sweeps, temperature sweeps, sensitivity calculations, mismatch analysis, and yield estimation. Optimization routines may adjust resistor values to maximize yield subject to gain and power constraints. Automation is valuable, but engineering judgement remains necessary when choosing objective functions and rejecting solutions that are fragile, noisy, difficult to manufacture, or thermally unsafe.

Common Design Errors and Practical Best Practices

A frequent error is selecting a Q-point from a nominal transistor characteristic and ignoring parameter spread. Another is treating \(V_{BE}=0.7\text{ V}\) or a fixed MOSFET threshold as a universal constant. These values are useful starting approximations, not guaranteed design parameters.

Designers also sometimes increase divider current indefinitely to improve stiffness. This reduces sensitivity but wastes power and can load a preceding reference. Conversely, excessively large resistors make the bias node vulnerable to leakage, noise, contamination, and measurement loading.

Thermal analysis is often performed only after electrical design. It should be included from the beginning, particularly when the transistor dissipates significant power or when the enclosure has restricted airflow. The thermal path, mounting arrangement, heat sink, and nearby heat sources matter as much as the semiconductor’s nominal rating.

Best practice includes:

• design from required signal limits and safe operating area;
• use negative feedback to reduce dependence on uncertain parameters;
• calculate sensitivity before selecting compensation components;
• check minimum and maximum supply conditions;
• separate ambient, case, and junction temperature in analysis;
• verify startup, shutdown, and fault conditions;
• distinguish guaranteed limits from typical datasheet values;
• use corner and statistical simulation appropriately;
• validate simulations with temperature and production measurements.

Professional and Ethical Considerations

Bias design affects product safety, reliability, energy consumption, and maintenance cost. A designer must not use typical transistor characteristics as if they were guaranteed limits, nor report a nominal simulation as evidence of production yield. Datasheet maximum ratings are not normal operating targets; appropriate derating and documented verification are required.

In regulated products, traceability of component ratings, thermal assumptions, test conditions, and change control may be mandatory. If a bias circuit can enter an unsafe state after a sensor failure or supply transient, fault analysis and protective design are part of professional responsibility. Transparent reporting of uncertainty is preferable to presenting an unjustifiably precise operating-point prediction.

Current Developments

Contemporary analog design increasingly combines device-level biasing with digitally assisted calibration. On-chip sensors can estimate temperature, while trimming adjusts reference currents or offset after fabrication. Background calibration can compensate slow drift without interrupting operation, although it adds circuit complexity, memory, verification requirements, and possible interaction with signal paths.

Advanced process technologies also rely on statistical compact models that represent mismatch and correlated process variation. Reliability-aware design may include electromigration, bias-temperature instability, hot-carrier effects, and long-term parameter drift. Consequently, robust biasing now extends beyond obtaining a correct DC solution: it includes lifetime behaviour, manufacturability, calibration strategy, and verification across the complete operating envelope.

Chapter Summary

Biasing establishes the transistor’s quiescent operating point and determines signal headroom, distortion, power dissipation, and reliability. DC load-line analysis provides a graphical and analytical method for selecting and checking the Q-point. Fixed bias is highly sensitive to transistor parameters, whereas emitter or source degeneration and collector feedback introduce negative feedback that improves stability.

Temperature changes transistor parameters and can create thermal runaway through positive electrothermal feedback. Thermal resistance, power dissipation, compensation tracking, and safe operating area must therefore be included in design. Device variability arises from temperature, process, mismatch, supply variation, and component tolerance. Sensitivity analysis identifies dominant parameters; worst-case analysis checks guaranteed limits; Monte Carlo analysis estimates statistical spread and yield.

Robust design combines suitable bias topology, feedback, thermal management, load-line margin, simulation, and measurement. The best solution is not necessarily the one with the smallest nominal error, but the one that maintains acceptable performance across the complete specified operating envelope.

Key Terms

Biasing: Establishing DC voltages and currents in an electronic device.

Q-point: Quiescent operating point of a transistor with no applied signal.

DC load line: Relationship between device voltage and current imposed by the external circuit.

Emitter degeneration: Use of emitter resistance to provide negative feedback in a BJT.

Source degeneration: Use of source resistance to provide negative feedback in a MOSFET.

Thermal runaway: Uncontrolled increase in device current caused by reinforcing temperature and power changes.

Thermal resistance: Temperature rise per unit dissipated power, expressed in °C/W.

Safe operating area: Permitted combinations of voltage, current, power, and time for a device.

Parameter variation: Change in device or circuit parameters from nominal values.

Process corner: Model representing an extreme or representative fabrication condition.

Mismatch: Difference between nominally identical devices or components.

Sensitivity: Measure of output response to a change in an input parameter.

Worst-case analysis: Evaluation using specified extreme parameter combinations.

Monte Carlo analysis: Repeated random simulation using assumed parameter distributions.

Yield: Fraction of manufactured circuits meeting specified requirements.

Thévenin equivalent: Voltage-source and series-resistance representation of a linear network.

Negative feedback: Feedback that opposes changes in the controlled quantity.

Thermal compensation: Circuit technique that offsets temperature-induced parameter changes.

Compliance voltage: Voltage range required for a current source or mirror to operate correctly.

Review Questions

Short Answer Questions

1. What is the purpose of selecting a Q-point in a transistor amplifier?

2. Why does an emitter resistor reduce BJT bias sensitivity to \(\beta\)?

3. Define thermal runaway and identify its electrothermal feedback path.

4. Distinguish process variation from device mismatch.

5. What information does a Monte Carlo histogram provide in bias analysis?

Long Answer Questions

1. Derive the voltage-divider BJT bias equation using the Thévenin equivalent of the base network and explain the role of emitter resistance.

2. Explain how DC load-line analysis is used to select a Q-point and verify signal headroom.

3. Compare fixed bias, collector-feedback bias, and voltage-divider bias with respect to stability, power, and complexity.

4. Discuss the thermal model of a transistor amplifier and methods for preventing thermal runaway.

5. Explain how sensitivity analysis, worst-case analysis, corner analysis, and Monte Carlo analysis complement one another.

Analytical / Application Questions

1. For a 12 V BJT amplifier with \(R_C=2.2\text{ k}\Omega\), \(R_E=1\text{ k}\Omega\), and the divider values given in the worked example, calculate the Q-point for \(\beta=50\) and compare it with the nominal result.

2. A MOSFET drain current rises when the circuit warms, causing the source voltage to rise. Explain quantitatively how source degeneration opposes this change and identify conditions under which it may be insufficient.

3. A production circuit fails its collector-current specification only at high temperature and low supply voltage. Propose a verification plan using load-line analysis, sensitivity calculations, corner simulations, Monte Carlo analysis, and laboratory testing.

22. Multiple Choice Questions with Answers

Question 1

In a voltage-divider biased BJT, which term most directly reduces sensitivity of collector current to beta?

A. The collector supply voltage

B. The emitter resistance reflected as (beta + 1)RE

C. The collector-emitter saturation voltage

D. The transistor output resistance

Correct Answer: B. The emitter resistance reflected as (beta + 1)RE

Question 2

The DC load line of a common-emitter stage is determined primarily by:

A. The transistor current gain alone

B. The small-signal transconductance

C. The supply voltage and external resistances

D. The base-emitter diffusion capacitance

Correct Answer: C. The supply voltage and external resistances

Question 3

If collector current increases in a collector-to-base feedback bias circuit, the immediate feedback action is that:

A. Collector voltage rises and base current rises

B. Collector voltage falls and base current is reduced

C. Emitter resistance becomes zero

D. The supply voltage increases

Correct Answer: B. Collector voltage falls and base current is reduced

Question 4

Which condition most directly promotes thermal runaway in a BJT?

A. A rise in temperature that causes current and power to increase further

B. A fall in temperature that reduces leakage current

C. A decrease in collector resistance with constant current

D. A reduction in junction-to-ambient thermal resistance

Correct Answer: A. A rise in temperature that causes current and power to increase further

Question 5

For a MOSFET with source degeneration, an increase in drain current tends to:

A. Lower source voltage and increase VGS

B. Raise source voltage and reduce VGS

C. Leave source voltage unchanged

D. Force the gate current to increase substantially

Correct Answer: B. Raise source voltage and reduce VGS

Question 6

Which analysis is most appropriate for estimating the statistical distribution of Q-point current when resistor and device parameters are random?

A. Single nominal DC analysis

B. Small-signal frequency analysis

C. Monte Carlo analysis

D. Only a worst-case corner calculation

Correct Answer: C. Monte Carlo analysis

Question 7

A normalized sensitivity of 0.3 of output Y to parameter X means approximately that:

A. A 1% change in X produces a 3% change in Y

B. A 3% change in X produces a 1% change in Y

C. A 1% change in X produces a 0.3% change in Y

D. Y is independent of X

Correct Answer: C. A 1% change in X produces a 0.3% change in Y

Question 8

Why can a nominal midpoint Q-point still be a poor practical design?

A. The load line is unrelated to signal swing

B. Parameter, temperature, and supply variations can move the point toward cutoff or saturation

C. Midpoint bias always causes thermal runaway

D. The transistor cannot operate in the active region at midpoint

Correct Answer: B. Parameter, temperature, and supply variations can move the point toward cutoff or saturation

Question 9

Which statement correctly distinguishes worst-case and Monte Carlo analysis?

A. Worst-case analysis estimates probability distributions, while Monte Carlo uses only guaranteed limits

B. Both methods always produce identical results

C. Worst-case analysis tests specified extremes, while Monte Carlo estimates statistical spread from distributions

D. Monte Carlo analysis cannot include component tolerances

Correct Answer: C. Worst-case analysis tests specified extremes, while Monte Carlo estimates statistical spread from distributions

Question 10

A thermal-compensation diode is most effective when it:

A. Is placed far from the transistor to avoid interaction

B. Has no temperature coefficient

C. Tracks the transistor’s temperature reasonably well

D. Is operated beyond its maximum current rating

Correct Answer: C. Tracks the transistor’s temperature reasonably well