Digital Measurement and Data Conversion

Introduction

Digital measurement converts a physical electrical quantity into numerical data suitable for display, storage, communication and computation. Modern digital multimeters, protection relays, power-quality analysers, oscilloscopes and industrial data-acquisition systems all combine analogue signal conditioning, sampling, quantisation, conversion and digital processing.

Conversion does not eliminate measurement uncertainty. Instead, analogue errors are joined by quantisation, aliasing, clock jitter, converter nonlinearity, reference drift, numerical processing and data-integrity risks. A defensible system must therefore be designed as a complete measurement chain rather than selected solely by converter bit count.

Learning Objectives

After completing this chapter, the reader should be able to:

• explain sampling, quantisation, encoding and reconstruction;
• derive and apply resolution, quantisation-noise and signal-to-noise relationships;
• distinguish ADC and DAC architectures;
• analyse aliasing, aperture uncertainty, nonlinearity and missing-code behaviour;
• design anti-alias and reconstruction filters from explicit specifications;
• interpret SINAD, ENOB, SNR, THD, INL and DNL;
• develop uncertainty-aware digital measurement systems; and
• evaluate calibration, traceability, cybersecurity and contemporary intelligent instrumentation.

1. Digital Measurement Chain

A digital measurement system normally contains a sensor or electrical input interface, protection, analogue conditioning, an anti-alias filter, a sample-and-hold circuit, an analogue-to-digital converter (ADC), digital processing and an output interface.

Figure: Functional chain for digital acquisition and optional analogue reconstruction.

Signal conditioning may provide attenuation, amplification, isolation, impedance conversion, level shifting and common-mode rejection. The ADC reference establishes the scale relating input voltage to code; its uncertainty and temperature coefficient directly affect gain accuracy.

2. Sampling and Aliasing

2.1 Uniform sampling

For uniform sampling at interval T_s, the sampling frequency is

where f_s is in hertz and T_s is in seconds. Samples of a continuous-time signal x(t) are x[n]=x(nT_s).

For a strictly band-limited baseband signal with no spectral content at or above bandwidth B, unique ideal reconstruction requires

The strict inequality provides separation between repeated spectra. Equality is not a robust engineering design because realizable filters require transition bandwidth and clocks are imperfect. The quantity f_s/2 is the Nyquist frequency.

A frequency component f_in sampled at f_s may appear in the first Nyquist zone at

where integer k is selected to place the alias frequency f_a in the stated interval.

Example. A 10 kHz sinusoid sampled at 8 kS/s appears at |10-8|=2 kHz. Subsequent digital filtering cannot determine whether the samples originated from 2 kHz or 10 kHz; analogue anti-alias filtering is therefore essential.

Bandpass sampling can use rates below twice the highest signal frequency, but only when the occupied band, image placement and filter selectivity satisfy the relevant bandpass-sampling constraints. The baseband Nyquist rule must not be applied to such systems without qualification.

2.2 Aperture time and clock jitter

A sample-and-hold requires finite acquisition time. Inadequate settling after multiplexer switching causes channel-dependent errors. Random sampling-time uncertainty σ_t creates an approximately jitter-limited SNR for a sinusoidal input of frequency f_in:

This expression assumes small, independent, root-mean-square timing jitter and a sinusoidal input. High-frequency precision measurements may therefore be clock-limited even when ADC resolution is high.

3. Quantisation and Coding

3.1 Ideal quantiser

For an ideal n-bit unipolar ADC with input interval 0 ≤ V_in < V_FS, the number of codes is 2ⁿ and the ideal code width is

Here q is one least significant bit (LSB) in volts and V_FS is the full input span. An ideal straight-binary output is

Inputs outside the conversion range saturate. Some manufacturers define endpoint scaling using 2ⁿ-1 rather than 2ⁿ; data-sheet conventions must therefore be checked before code-to-voltage conversion.

Worked example. A 12-bit ADC has a 0–4.096 V range:

An ideal input of 2.500 V produces code 2500 under the stated floor-based convention.

Bipolar converters commonly use offset binary or two's-complement coding. Coding changes numerical interpretation, not analogue resolution.

3.2 Quantisation error and noise

For rounding to the nearest level, ideal quantisation error lies approximately within

If the error is approximately uniform, uncorrelated with the signal and spans many codes, its variance and RMS value are

These are statistical noise-model results, not universal bounds for deterministic low-amplitude or coherent signals. Dither can decorrelate quantisation error by adding controlled noise, trading increased noise floor for reduced tonal distortion.

For an ideal ADC driven by a full-scale sinusoid, with quantisation noise distributed over the Nyquist band,

The formula does not represent DC accuracy and does not include thermal noise, harmonics, jitter or reference error.

4. Static and Dynamic Converter Performance

4.1 Static characteristics

Offset error shifts the transfer characteristic. Gain error changes its slope after offset removal. Integral nonlinearity (INL) is the deviation of code-transition locations from a specified straight-line reference, usually expressed in LSB. Differential nonlinearity (DNL) for code k is

where W_k is the actual code width and q_ideal is the ideal width. A converter is monotonic if increasing input never decreases output code. The condition DNL_k > -1 LSB for every code guarantees positive code widths and hence no missing codes; equality corresponds to zero code width.

Resolution must not be confused with accuracy. A 24-bit converter may have only 18 noise-free bits and may still possess substantial gain or reference uncertainty.

4.2 Dynamic characteristics

Important frequency-domain metrics include:

• SNR: signal power relative to noise, normally excluding DC and harmonics;
• THD: harmonic power relative to fundamental power;
• SINAD: fundamental signal power relative to noise plus distortion;
• SFDR: ratio of the fundamental to the largest unwanted spectral component;
• ENOB: resolution inferred from measured SINAD.

For a near-full-scale sinusoidal test under the conventional ideal-ADC normalization,

If SINAD is 74 dB, ENOB=(74-1.76)/6.02≈12.0 bits. ENOB is frequency- and amplitude-dependent and should be reported with test conditions.

5. ADC Architectures

A dual-slope integrating ADC first integrates the unknown voltage for fixed time T₁, then integrates an opposite-polarity reference until the integrator returns to zero. For ideal components,

Thus V_in=V_refT₂/T₁. Because the same resistor and capacitor participate in both phases, their absolute values largely cancel. Choosing T₁ as an integer number of power-line periods strongly rejects 50 or 60 Hz interference.

Delta–sigma converters oversample and shape quantisation noise toward higher frequencies before digital low-pass filtering and decimation. Their quoted output data rate is not the modulator clock frequency. Settling time, filter passband and latency must be assessed in multiplexed or control applications.

6. Digital-to-Analogue Conversion

For an ideal unipolar n-bit DAC using straight-binary code D,

The maximum output is one LSB below V_ref under this convention. Common implementations include binary-weighted resistor networks, R–2R ladders, current-steering DACs and delta–sigma DACs.

Practical DAC properties include settling time, monotonicity, glitch impulse, zero-scale error, gain error and output-drive capability. A zero-order-hold output produces spectral images around multiples of the update frequency. A reconstruction low-pass filter suppresses these images and smooths the staircase waveform.

7. Anti-Alias Filter Design

For an Nth-order Butterworth low-pass filter,

where f_c is the −3.0103 dB cutoff frequency. Suppose the required magnitude is at least H_p at passband edge f_p, and at most H_s at stopband edge f_st, with 0 < H_s < H_p < 1 and f_st>f_p. The minimum order satisfies

Here H_p and H_s are dimensionless magnitude limits, not ambiguously defined loss parameters.

Worked filter-order calculation

Let H_p=0.99, H_s=0.01 and f_st/f_p=3. Then

Therefore,

The required integer order is consequently sixth order. For N=6, the cutoff must satisfy

and

A nominal value near 1.388f_p satisfies both ideal-magnitude constraints. Component tolerances, operational-amplifier bandwidth and process variation require additional design margin. Elliptic filters can meet steep transitions with lower order but introduce passband ripple, stronger phase distortion and greater sensitivity.

8. Oversampling, Averaging and Digital Filtering

For white, uncorrelated noise, averaging M independent samples reduces the standard deviation to

A fourfold increase in independent samples ideally improves SNR by 6.02 dB, equivalent to approximately one bit. This conclusion fails for drift, periodic interference and correlated noise. Oversampling alone does not remove aliases already folded into the sampled band.

Digital filters provide repeatable responses and can implement finite-impulse-response linear-phase filtering, infinite-impulse-response filtering, decimation and interference rejection. Nevertheless, coefficient quantisation, arithmetic overflow, group delay and startup transients must be considered.

9. Digital Instruments and Data Acquisition

A digital multimeter typically includes protection, range switching, precision resistive networks, current shunts, integrating or delta–sigma conversion, calibration coefficients and a display processor. Specifications often use the form

where E is absolute error, R is the reading, F is selected-range full scale, a and b are dimensionless coefficients, and c is an absolute term in measurement units. Temperature and time since calibration may add further terms.

A statement such as “error below 0.5% of reading over 0–400 V” is ill-defined at zero because its allowed error becomes zero. A defensible specification must include a range-based or absolute-error term and state confidence, environmental conditions and bandwidth.

In multichannel acquisition, one ADC may be preceded by a multiplexer. Designers must account for source impedance, charge injection, channel settling and skew. Simultaneous-sampling ADCs are preferable for phase, power and transient measurements where interchannel timing matters.

10. Measurement Uncertainty and Calibration

A measurement result should be reported with an uncertainty statement rather than only a nominal code. For uncorrelated standard uncertainty components u_i, the combined standard uncertainty is

This root-sum-square rule applies only after uncertainties are expressed as standard uncertainties and correlations are negligible. With sensitivity coefficients c_i and correlated inputs, the general first-order law is

where u_ij is covariance. Expanded uncertainty is often U=ku_c, where coverage factor k is selected for the stated coverage basis.

Calibration compares the system with traceable standards and estimates corrections. Verification tests conformance; adjustment changes the instrument. Good practice includes preserving raw data, calibration history, firmware version, environmental records and uncertainty budgets.

11. Applied Case: Isolated 0–400 V RMS Monitor

Background

This is an illustrative case involving an industrial monitor required to measure a 50/60 Hz supply and harmonics to 10 kHz. The maximum input is 400 V RMS, corresponding to approximately 566 V peak for a sinusoid.

Problem

The required accuracy is specified as

This produces a finite zero-input allowance of 0.08 V. At 400 V the limit is 0.20+0.08=0.28 V; at 10 V it is 0.005+0.08=0.085 V. Unlike a percentage-of-reading-only specification, the requirement is meaningful across the complete range.

Analysis and Approach

An isolated input module uses overvoltage protection, a precision divider, reinforced isolation and an 18-bit simultaneous-sampling ADC with a ±4.096 V input span. A nominal 150:1 divider maps 566 V peak to 3.77 V peak.

The ADC span is 8.192 V, so its ideal code width is

Referred to the high-voltage input, one LSB is 31.25 μV×150=4.6875 mV. Quantisation is therefore much smaller than the stated range-based error, although this alone does not prove compliance.

A 64 kS/s rate gives a 32 kHz Nyquist frequency. The analogue filter passes 0–10 kHz and strongly attenuates content above the transition band. Divider tolerance, isolation-amplifier gain, ADC reference, filter response, clock error, noise and RMS algorithm bias are included in the uncertainty budget. Simultaneous sampling enables voltage-current phase measurement if a current channel is added.

RMS is calculated over a defined observation interval using

The discrete expression estimates RMS when the samples represent the observation interval adequately. Window length, DC content, bandwidth and nonsynchronous sampling affect the result.

Outcome

Calibration at zero, intermediate levels and near full scale determines offset and gain corrections. Frequency-response calibration verifies harmonic measurements. Compliance is accepted only when expanded uncertainty plus correction residual remains within the specified error limit under stated temperature and frequency conditions.

Learning Points

• Converter resolution is only one part of system accuracy.
• Peak input and safety ratings must be derived from the waveform, not RMS alone.
• Anti-alias filtering must precede conversion.
• Range-based or absolute-error terms are indispensable near zero.
• Traceability and an uncertainty budget convert a design claim into defensible measurement evidence.

12. Implementation Challenges and Best Practices

Principal difficulties include reference drift, grounding, electromagnetic interference, thermal gradients, dielectric absorption, clock coupling and digital feedthrough. Printed-circuit layout should separate sensitive analogue return paths from switching currents while preserving a controlled reference connection. Decoupling must follow converter-manufacturer guidance.

Recommended practices are to:

1. derive sampling rate from signal bandwidth and filter transition requirements;
2. provide input protection without compromising leakage or bandwidth;
3. verify settling for worst-case source impedance and channel step;
4. select the reference for noise, drift and load regulation—not nominal voltage alone;
5. test static and dynamic performance over temperature;
6. retain unprocessed samples where auditability is important; and
7. validate firmware calculations using known waveforms and boundary cases.

13. Governance and Contemporary Developments

Networked instruments introduce cybersecurity and data-governance risks. Authentication, signed firmware, role-based configuration, time synchronisation and tamper-evident records may be necessary in regulated or safety-critical installations. Automated correction must preserve the original data and calibration provenance.

Contemporary systems increasingly combine precision converters with FPGA processing, time-sensitive networking, edge analytics and machine-learning diagnostics. AI can identify sensor drift or anomalous waveforms, but it does not replace metrological traceability. Training-data bias, false alarms, model updates and unexplained corrections require governance. Self-calibrating converters, digitally assisted analogue circuits and distributed synchronized acquisition are important continuing developments.

Chapter Summary

Digital measurement integrates analogue conditioning, sampling, quantisation, conversion and computation. The sampling theorem establishes the minimum rate for strictly band-limited signals, while practical systems require anti-alias filters and transition margins. Quantisation determines ideal resolution and, under stated statistical assumptions, quantisation noise and ideal SNR.

ADC architectures trade speed, resolution, power, latency and rejection of interference. Static metrics such as INL and DNL differ fundamentally from dynamic metrics such as SINAD and ENOB. DAC systems additionally require attention to settling, glitches and reconstruction filtering. Reliable instruments combine converter analysis with explicit error specifications, uncertainty evaluation, calibration, traceability, safety and secure data governance.

Key Terms

Aliasing: Indistinguishable spectral folding caused by sampling inadequately filtered frequency content.

Anti-alias filter: Analogue filter used before sampling to attenuate frequencies that would fold into the measurement band.

Aperture jitter: Random uncertainty in the instant at which a sample is acquired.

Code width: Input interval associated with one output code.

Decimation: Reduction of sample rate after suitable digital low-pass filtering.

Differential nonlinearity: Deviation of an actual code width from one ideal LSB.

Dither: Deliberately added noise used to decorrelate quantisation error.

Effective number of bits: Resolution inferred from measured SINAD under specified test conditions.

Integral nonlinearity: Deviation of the converter transfer characteristic from a reference straight line.

LSB: Least significant bit; commonly the ideal smallest code increment.

Monotonicity: Property that output code never decreases as input increases.

Nyquist frequency: Half the sampling frequency.

Quantisation: Mapping a continuous-amplitude input to a finite set of levels.

Reconstruction filter: Analogue filter that suppresses DAC images and smooths the output.

Sample-and-hold: Circuit that acquires and retains an input value during conversion.

SINAD: Ratio of signal power to total noise-plus-distortion power.

Traceability: Documented calibration chain linking a result to recognized references.

Uncertainty: Parameter characterising dispersion reasonably attributable to a measurement result.

Review Questions

Short Answer Questions

1. Distinguish resolution from accuracy in an ADC.
2. Why can digital filtering not remove an alias after sampling?
3. Define INL and DNL.
4. State the conditions underlying the ideal quantisation-noise model.
5. Why is an absolute or range-based error term necessary near zero input?

Long Answer Questions

1. Explain the complete digital measurement chain and identify major error sources at each stage.
2. Compare flash, SAR, pipeline, integrating and delta–sigma ADC architectures.
3. Derive the ideal ADC SNR relationship for a full-scale sinusoid from quantisation-noise assumptions.
4. Discuss the design and practical limitations of anti-alias and reconstruction filters.
5. Explain how calibration, uncertainty analysis and traceability support defensible digital measurements.

Analytical / Application Questions

1. Design a sampling and filtering strategy for a 15 kHz measurement band when the available ADC operates at 100 kS/s. State transition-band and attenuation assumptions.
2. An ADC has 80 dB SINAD at 20 kHz input frequency. Calculate its ENOB and assess whether timing jitter of 2 ps RMS is likely to be the dominant limitation.
3. Construct an uncertainty budget for a voltage channel containing a divider, isolation amplifier, voltage reference and ADC, identifying possible correlations.

Multiple Choice Questions with Answers

Question 1

An ideal 12-bit ADC has a unipolar 0–4.096 V input span. What is one LSB under the q=V_FS/2ⁿ convention?

A. 0.5 mV

B. 1 mV

C. 2 mV

D. 4 mV

Correct Answer: B. 1 mV

Question 2

A 10 kHz sinusoid is uniformly sampled at 8 kS/s. What alias appears in the first Nyquist zone?

A. 1 kHz

B. 2 kHz

C. 4 kHz

D. 18 kHz

Correct Answer: B. 2 kHz

Question 3

What is the ideal quantisation-limited SNR of a 10-bit ADC driven by a full-scale sinusoid?

A. 49.9 dB

B. 60.2 dB

C. 62.0 dB

D. 74.0 dB

Correct Answer: C. 62.0 dB

Question 4

For a Butterworth filter with H_p=0.99, H_s=0.01 and f_st/f_p=3, what minimum integer order is required?

A. Third order

B. Fourth order

C. Fifth order

D. Sixth order

Correct Answer: D. Sixth order

Question 5

A 0–400 V instrument has an error limit of ±(0.05% of reading + 0.02% of range). What is the error limit at a 100 V reading?

A. ±0.05 V

B. ±0.08 V

C. ±0.13 V

D. ±0.28 V

Correct Answer: C. ±0.13 V

Question 6

For fixed RMS clock jitter, increasing sinusoidal input frequency has what effect on jitter-limited SNR?

A. It increases by 6.02 dB per octave

B. It remains constant

C. It decreases by approximately 6.02 dB per octave

D. It becomes independent of the clock

Correct Answer: C. It decreases by approximately 6.02 dB per octave

Question 7

Which DNL condition for every code guarantees positive code width and no missing codes?

A. DNL> -1 LSB

B. DNL< -1 LSB

C. DNL=+1 LSB

D. DNL<+2 LSB

Correct Answer: A. DNL> -1 LSB

Question 8

Which ADC architecture performs conversion through a binary search using an internal DAC and comparator?

A. Flash

B. Successive approximation

C. Dual-slope integrating

D. Delta–sigma

Correct Answer: B. Successive approximation

Question 9

Which ADC architecture characteristically combines oversampling, noise shaping and digital decimation?

A. Pipeline

B. Flash

C. Delta–sigma

D. Tracking

Correct Answer: C. Delta–sigma

Question 10

For an ideal 12-bit unipolar DAC with V_ref=5.0 V, what output corresponds to code D=2048 under V_out=V_refD/2ⁿ?

A. 1.25 V

B. 2.00 V

C. 2.50 V

D. 4.096 V

Correct Answer: C. 2.50 V