Material Processing, Fabrication and Packaging

Introduction

Electrical and electronic materials rarely achieve their useful properties in the as-extracted or as-synthesized state. A semiconductor must be purified and crystallized; a metal contact may require alloying and heat treatment; an insulator may be shaped, sintered, or coated; and an integrated circuit must be interconnected and protected by a package. Processing therefore forms the bridge between material structure and engineering performance.

The central principle of this chapter is the process–structure–property relationship:

processing → microstructure and interfaces → properties → device performance and reliability

For example, reducing metallic impurity concentration increases carrier lifetime in silicon, while excessive thermal treatment can cause dopant diffusion and destroy a desired junction profile. Similarly, a solder joint is not characterized only by its alloy composition: intermetallic layers, voids, grain structure, wetting, and thermal history strongly influence its reliability.

Learning Objectives

After studying this chapter, the reader should be able to:

1. Explain purification and crystal-growth methods used for electronic materials.
2. Relate alloying and heat treatment to electrical, mechanical, and thermal properties.
3. Describe thin-film deposition, lithography, sintering, and polymer-processing methods.
4. Compare subtractive, formative, and additive manufacturing approaches.
5. Explain soldering, adhesive bonding, wire bonding, and electronic packaging.
6. Analyze how defects, interfaces, residual stress, contamination, and thermal mismatch affect performance.
7. Select suitable fabrication processes for practical electrical-engineering applications.

1. Purification of Electronic Materials

Electronic materials often require much greater purity than structural materials. A small concentration of electrically active impurities can substantially change conductivity, carrier lifetime, breakdown voltage, or optical absorption. Commercial silicon for integrated circuits is commonly specified in terms of extremely low impurity concentrations, often approaching parts per billion for critical contaminants.

1.1 Chemical and physical purification

Common purification operations include:

• Chemical conversion: The raw material is converted into a volatile compound that can be distilled or purified. Silicon may be converted to chlorosilanes, purified by fractional distillation, and decomposed to deposit high-purity silicon.
• Zone refining: A narrow molten zone travels through a solid bar. Most impurities preferentially remain in the liquid and are swept toward one end. Repeated passes increase purity.
• Electrorefining: An impure metal is the anode, a pure sheet is the cathode, and ions move through an electrolyte. Insoluble impurities form anode sludge.
• Gettering: A reactive region captures mobile impurities during later thermal processing. In silicon, gettering may use a damaged backside region or phosphorus-rich layers.
• Vacuum melting and inert-atmosphere processing: These reduce oxidation, gas absorption, and contamination.

The effectiveness of zone refining can be described approximately using the equilibrium distribution coefficient:

where C_s is the impurity concentration in the solid at the solid–liquid interface and C_l is its concentration in the liquid. The expression assumes local equilibrium at a planar interface. When k₀ < 1, the impurity prefers the liquid and zone refining is effective. A coefficient greater than one indicates preferential incorporation into the solid.

Purification must be designed around the impurity’s chemical behavior. Oxygen, carbon, metallic contaminants, and electrically active dopants require different removal strategies. Purity alone is not sufficient: impurity location, chemical state, and activation are equally important.

2. Crystal Growth and Wafer Preparation

Single crystals provide uniform crystallographic orientation and controlled electrical properties. Important growth methods include the Czochralski method, float-zone growth, Bridgman growth, and epitaxy.

2.1 Czochralski growth

In Czochralski growth, a seed crystal is dipped into molten material and slowly withdrawn while rotating. The melt temperature, pulling speed, rotation, and atmosphere are controlled to produce a cylindrical boule. Silicon wafers for many integrated circuits are made this way.

Advantages include large crystal diameter, high throughput, and the ability to add dopants to the melt. A limitation is contamination from the crucible, particularly oxygen from silica crucibles. Oxygen can be harmful or beneficial depending on concentration and subsequent thermal treatment.

2.2 Float-zone growth

Float-zone growth uses a localized molten zone supported without a crucible. It provides very high purity and low oxygen concentration, making it valuable for power devices and high-resistivity applications. However, large-diameter production is more difficult than with Czochralski growth.

2.3 Defects in crystals

Crystal defects include vacancies, interstitials, dislocations, stacking faults, and grain boundaries. Point defects influence diffusion and carrier concentration. Dislocations can act as recombination centers or leakage paths. Grain boundaries interrupt periodicity and often degrade carrier mobility, so single-crystal material is preferred for high-performance semiconductor devices.

After growth, wafers are sliced, edge-rounded, lapped, chemically etched, polished, cleaned, and inspected. Surface roughness is important because it affects gate-oxide quality, thin-film uniformity, contact resistance, and lithographic resolution.

3. Alloying and Heat Treatment

3.1 Alloying

Alloying introduces one or more elements into a base material to modify properties. In electrical engineering, alloying can:

• increase strength and hardness;
• control resistivity and temperature coefficient;
• improve oxidation or corrosion resistance;
• adjust melting and wetting behavior;
• modify magnetic permeability and coercivity;
• create solder and brazing compositions.

Solid solutions form when solute atoms occupy normal lattice sites or interstitial positions. Intermetallic compounds form ordered phases with specific stoichiometry. Both can be useful, but brittle intermetallic phases may reduce mechanical reliability.

A simple dilute-alloy approximation for resistivity is often written as:

where ρ is resistivity, ρ₀ is the resistivity of the pure host at the specified temperature, and Δρ_imp is the impurity contribution. This is an approximation for dilute alloys; it does not describe concentrated alloys or phase-transforming systems accurately.

3.2 Heat-treatment operations

Heat treatment changes phase distribution, defect density, residual stress, and precipitate size. Major operations are:

• Annealing: Heating followed by controlled cooling to reduce defects, relieve stress, and improve ductility.
• Normalizing: Heating and air cooling, commonly used in steels to refine grain structure.
• Quenching: Rapid cooling to retain a high-temperature phase or create supersaturation.
• Tempering: Reheating a quenched material to improve toughness and reduce brittleness.
• Solution treatment and aging: Dissolving alloying elements at high temperature, quenching, then holding at a lower temperature so strengthening precipitates form.
• Diffusion annealing: Heating to redistribute dopants or reduce concentration gradients.

Diffusion is commonly modeled by Fick’s first law under steady-state conditions:

where J is atomic flux in mol·m⁻²·s⁻¹, D is the diffusion coefficient in m²·s⁻¹, and dc/dx is the concentration gradient in mol·m⁻⁴. The negative sign indicates transport down the concentration gradient. The equation assumes one-dimensional steady diffusion and constant D.

For many solids, the diffusion coefficient follows an Arrhenius relationship:

where D₀ is a pre-exponential factor, Q is activation energy in J·mol⁻¹, R is the gas constant, and T is absolute temperature in kelvin. The strong temperature dependence explains why a small increase in process temperature can greatly increase dopant diffusion or oxidation rate.

Heat treatment must consider thermal budget. In a semiconductor process, thermal budget means the combined effect of time and temperature on diffusion, defect reactions, film stress, and phase changes. Excessive thermal budget can blur junctions, increase interface roughness, or cause metallization reactions.

4. Thin-Film Deposition

Thin films provide conductors, resistors, dielectric layers, barriers, passivation, optical coatings, and active semiconductor layers. Film properties depend on substrate preparation, deposition rate, temperature, pressure, chemistry, and post-deposition treatment.

4.1 Physical vapor deposition

In physical vapor deposition (PVD), material is physically vaporized and transported to a substrate. Thermal evaporation is simple and provides high deposition rates, but line-of-sight geometry can produce poor coverage. Sputtering accelerates ions into a target, ejecting target atoms toward the substrate. It provides good adhesion and can deposit metals, alloys, and compounds.

Important sputtering variables include gas pressure, target power, substrate bias, and substrate temperature. Excessive ion bombardment may create defects or compressive stress; insufficient energy may produce porous films.

4.2 Chemical vapor deposition

Chemical vapor deposition (CVD) forms a film by chemical reactions of gaseous precursors at or near a heated substrate. It provides conformal coverage over three-dimensional features. Plasma-enhanced CVD lowers the substrate temperature by using a plasma to activate reactions, which is useful for temperature-sensitive structures.

4.3 Atomic layer deposition

Atomic layer deposition (ALD) uses sequential, self-limiting surface reactions. A precursor pulse, purge, reactant pulse, and second purge form approximately one molecular layer per cycle. ALD offers excellent thickness control and conformality, although it is slower than many PVD and CVD processes.

4.4 Film properties and characterization

Important properties include thickness, sheet resistance, adhesion, stress, roughness, dielectric strength, composition, and pinhole density. For a uniform conducting film, sheet resistance is:

where R_s is sheet resistance in ohms per square, ρ is resistivity in Ω·m, and t is film thickness in metres. The unit “ohms per square” is independent of the square size for a uniform film of constant thickness.

Film stress can arise from lattice mismatch, thermal-expansion mismatch, intrinsic growth processes, and chemical reactions. High tensile stress may cause cracking; high compressive stress may cause buckling or delamination. Adhesion testing, profilometry, ellipsometry, four-point probing, microscopy, and X-ray diffraction are commonly used for evaluation.

5. Lithography and Pattern Transfer

Lithography transfers a geometric pattern to a substrate. In photolithography, the wafer is coated with photoresist, soft-baked, aligned with a mask, exposed, developed, and hard-baked or otherwise stabilized. Positive resist becomes soluble in exposed regions; negative resist becomes insoluble in exposed regions.

Pattern transfer may use wet etching, dry plasma etching, ion milling, or lift-off. Wet etching can be highly selective but may be isotropic. Plasma etching provides directional profiles and fine features but may cause charging, radiation damage, or polymer residues.

Resolution is affected by wavelength, numerical aperture, focus, resist properties, vibration, contamination, and process variation. A simplified optical-resolution relationship is often expressed as:

where R is the minimum printable feature scale, k₁ is a process-dependent factor, λ is exposure wavelength, and NA is numerical aperture. This is a practical scaling relation, not a universal exact law. It assumes a specified imaging system and process window.

Cleanroom control is essential. Particles can cause open circuits, short circuits, pinholes, and fatal defects. Control measures include filtered air, controlled humidity, appropriate garments, chemical segregation, and disciplined wafer handling.

6. Sintering and Ceramic Processing

Ceramic electrical materials such as alumina, barium titanate, ferrites, and zirconia are commonly manufactured by powder processing. Typical steps are powder synthesis, milling, mixing, binder addition, forming, drying, binder removal, sintering, and finishing.

Sintering heats a compact below its melting point so that diffusion reduces pore volume and bonds particles. Densification generally improves dielectric strength, mechanical strength, thermal conductivity, and hermeticity. Grain growth, however, may reduce dielectric performance or create nonuniform properties.

The linear shrinkage of a compact can be estimated by:

where L₀ is the initial dimension and L_f is the final dimension after sintering. This expression assumes measurements are made along the same direction and that dimensional change is the quantity of interest. Designers must compensate mould dimensions for shrinkage.

Sintering atmosphere is important. Reducing atmospheres can change the valence state of transition-metal ions; oxygen partial pressure can change conductivity, defect chemistry, and dielectric loss. Binder burnout must be slow enough to prevent internal gas pressure and cracking.

7. Polymer Processing and Encapsulation Materials

Polymers are used as cable insulation, printed-circuit-board laminates, adhesives, encapsulants, photoresists, and flexible substrates. Thermoplastics soften on heating and can be remelted; thermosets form cross-linked networks and do not melt after curing; elastomers undergo large reversible deformation.

Processing methods include injection molding, extrusion, compression molding, transfer molding, calendaring, casting, and lamination. Process temperature and shear rate influence molecular orientation, crystallinity, void content, and residual stress.

Thermoset encapsulants are mixed with fillers and cured around an electronic assembly. Silica fillers reduce coefficient of thermal expansion, but high filler loading increases viscosity and may complicate mold filling. Moisture absorption can lower insulation resistance and contribute to delamination during solder reflow.

Polymer selection must consider dielectric loss, breakdown strength, glass-transition temperature, moisture uptake, flame behavior, chemical compatibility, and long-term aging. Electrical insulation should not be judged solely by its initial resistivity; tracking, partial discharge, thermal aging, and environmental exposure may dominate service life.

8. Additive Manufacturing

Additive manufacturing creates components layer by layer from digital models. Methods relevant to electrical engineering include fused-filament fabrication, stereolithography, selective laser sintering, powder-bed fusion, aerosol jet printing, inkjet printing, and direct-write conductive printing.

Advantages include rapid prototyping, geometric freedom, low material waste, and integration of channels or embedded conductors. Limitations include anisotropic properties, stair-step surface texture, porosity, dimensional variation, limited material choices, and lower throughput for mass production.

For conductive printing, inks may contain metallic nanoparticles, flakes, conductive polymers, or carbon materials. Printed tracks often require drying, photonic curing, thermal sintering, or chemical treatment. The final conductivity depends on particle packing, neck formation, residual solvent, oxidation, and substrate compatibility.

Process qualification should measure resistance, adhesion, dimensional accuracy, bending durability, thermal cycling, and electromigration where applicable. A printed circuit that works electrically immediately after fabrication may fail after repeated flexing or humidity exposure.

9. Joining and Interconnection

9.1 Soldering

Soldering joins metals using a filler alloy whose melting temperature is below that of the components. The joint depends on surface cleanliness, flux chemistry, wetting, thermal profile, pad geometry, and intermetallic-compound formation.

Lead-free tin-based solders are widely used because of environmental regulations and health concerns associated with lead. Common families include tin–silver–copper alloys. Flux removes oxides and promotes wetting, but ionic residues can reduce insulation resistance or cause corrosion.

A solder joint may fail by fatigue under repeated thermal cycling. A simplified strain-range relation used in fatigue analysis is often written:

where N_f is cycles to failure, ∆ε_p is plastic strain range, and C and m are experimentally determined constants for a particular alloy, geometry, temperature, and failure criterion. It must not be used outside its calibrated conditions.

9.2 Brazing, welding, and bonding

Brazing uses a filler metal above 450 °C but below the melting point of the base materials. Welding generally melts and fuses the base materials. Conductive adhesives use polymer matrices containing silver, copper, or other conductive particles and are valuable for low-temperature assembly or heat-sensitive substrates.

Wire bonding uses fine gold, aluminum, or copper wire to connect semiconductor pads to package leads. Ball bonding and wedge bonding require controlled force, ultrasonic energy, and temperature. Bond quality depends on pad metallurgy, contamination, loop geometry, and heel strength.

Flip-chip bonding places solder bumps or conductive pillars between a die and substrate. It provides short interconnects, low parasitic inductance, and high input/output density. Underfill is often added to distribute stress caused by thermal-expansion mismatch.

10. Electronic Packaging

Packaging performs several functions:

1. provides mechanical protection;
2. supports electrical interconnection;
3. removes heat;
4. protects against moisture, chemicals, particles, and radiation;
5. enables testing, handling, and system integration.

Package forms include through-hole packages, leaded surface-mount packages, ball-grid arrays, chip-scale packages, ceramic packages, metal hermetic packages, and three-dimensional stacked packages.

10.1 Thermal design

A basic steady-state thermal model is:

where T_j is junction temperature, T_a is ambient temperature, P is dissipated power in watts, and θ_ja is junction-to-ambient thermal resistance in °C·W⁻¹. The model assumes steady state, approximately linear heat flow, and a defined mounting and airflow condition. Actual systems may require a thermal-resistance network containing junction-to-case, case-to-sink, and sink-to-ambient terms.

For a package with several thermal interfaces, contact resistance, voids, surface roughness, and interface-material aging may dominate. Thermal vias, heat spreaders, copper planes, forced air, and liquid cooling improve heat removal.

10.2 Electrical parasitics and signal integrity

Package leads and bond wires introduce resistance, capacitance, and inductance. At high switching speeds, these parasitics cause voltage overshoot, ringing, delay, crosstalk, and electromagnetic radiation. Shorter interconnects and controlled-impedance substrates reduce these effects. Power packages additionally require low-resistance current paths and effective electrical isolation where necessary.

10.3 Reliability mechanisms

Important package failure mechanisms include:

• solder fatigue and creep;
• wire-bond lift-off and heel cracking;
• die cracking;
• delamination and moisture-induced damage;
• corrosion and electrochemical migration;
• electromigration in fine conductors;
• thermal runaway or excessive junction temperature;
• intermetallic growth and brittle-interface formation.

Reliability testing may include temperature cycling, thermal shock, high-temperature operating life, humidity-bias testing, vibration, mechanical shock, and accelerated aging. Qualification tests should represent realistic use conditions and failure physics rather than merely applying arbitrary severe conditions.

11. Process–Property Relationships and Process Selection

Process selection should begin with required properties and constraints, not with a favorite manufacturing method. A useful sequence is:

1. define electrical, thermal, mechanical, dimensional, and environmental requirements;
2. identify allowable materials and compatibility limits;
3. select a process capable of producing the required geometry and microstructure;
4. identify critical process parameters;
5. characterize properties and defects;
6. validate reliability under service conditions.

Examples illustrate the relationship:

Statistical process control is useful for monitoring thickness, line width, sheet resistance, bond strength, void fraction, and defect density. However, statistical control cannot replace physical understanding. A process may remain statistically stable while producing unacceptable parts if the target or specification is wrong.

12. Illustrative Case Study: Reliability of a Power Module

Background

Consider an illustrative 1.2 kV power module containing silicon-carbide switching dies attached to a copper-based substrate. The module must conduct high current, dissipate heat, and survive thousands of temperature cycles.

Problem

Prototype modules show increasing thermal resistance and intermittent electrical failure after temperature cycling. Microscopy reveals voids beneath the die attach and cracks near the bond-wire heel.

Analysis

The die attach contains voids that interrupt heat flow and concentrate mechanical stress. During operation, the die temperature rises and falls. Copper, semiconductor, ceramic, and solder or sintered-silver layers have different coefficients of thermal expansion. Repeated mismatch produces shear strain. Bond wires experience current heating and cyclic mechanical deformation.

Approach

The engineering team:

• replaces uncontrolled solder attachment with pressure-assisted sintered silver;
• improves substrate flatness and surface cleanliness;
• establishes controlled pressure, temperature, and dwell time;
• uses X-ray inspection to quantify voids;
• replaces a vulnerable wire geometry with shorter, thicker copper bonds;
• adds thermal simulation and temperature-cycle validation;
• monitors die-attach thickness and bond pull strength as process-control variables.

Outcome

Void fraction decreases, thermal resistance becomes more consistent, and the dominant bond-wire failure is reduced. The improvement does not arise from one material change alone; it results from coordinating material selection, surface preparation, joining conditions, thermal design, inspection, and reliability testing.

Learning Points

1. Interfaces can dominate system reliability.
2. A process parameter may affect several properties simultaneously.
3. Non-destructive inspection is valuable when hidden defects control failure.
4. Reliability testing should be linked to a physical failure mechanism.
5. Design for manufacture and design for reliability must be considered together.

13. Environmental, Safety, and Professional Considerations

Fabrication uses solvents, acids, bases, photoresists, metal salts, pressurized gases, high temperatures, lasers, plasmas, and fine powders. Engineering practice requires chemical labeling, ventilation, personal protective equipment, waste segregation, emergency procedures, and documented process controls.

Lead, mercury, certain flame retardants, and some solvents present environmental and health concerns. Regulations such as restrictions on hazardous substances influence material and solder selection, although compliance requirements vary by jurisdiction and product category. Engineers must verify current legal requirements rather than relying on informal assumptions.

Manufacturing decisions also have lifecycle implications. Energy-intensive purification, water consumption in wafer cleaning, rare-material supply chains, recycling difficulty, and electronic waste should be considered. Design choices that improve repairability, material separation, and component longevity can reduce environmental impact.

Automation and machine learning can assist defect classification, predictive maintenance, process-window optimization, and visual inspection. These tools require representative data, traceability, validation, and human oversight. A model trained on one product or lighting condition may fail when materials, equipment, or environments change.

Contemporary Developments and Best Practices

Current directions include wafer-scale integration, heterogeneous integration, chiplets, advanced fan-out packaging, low-temperature sintering, printed electronics, wide-bandgap semiconductor processing, and three-dimensional interconnects. These developments increase performance but make thermal management, metrology, materials compatibility, and reliability more challenging.

Best practices include:

• control contamination from incoming material through final assembly;
• record complete thermal, chemical, and mechanical process histories;
• design experiments to separate interacting process variables;
• characterize both average properties and defect distributions;
• use interface analysis when failure occurs near a boundary;
• match accelerated tests to real service mechanisms;
• include manufacturability and end-of-life considerations early in design;
• maintain calibration, traceability, and change control.

Chapter Summary

Electronic-material performance is created through controlled processing. Purification removes electrically harmful contaminants, while crystal growth establishes orientation, defect population, and dopant distribution. Alloying changes phase constitution and properties; heat treatment controls diffusion, residual stress, grain structure, and precipitation.

Thin-film deposition by PVD, CVD, and ALD enables conductors, dielectrics, barriers, and active layers. Lithography and etching transfer patterns, with contamination and process variation limiting yield. Powder processing and sintering produce dense ceramic components, while polymer processing supplies insulation, encapsulation, substrates, and adhesives. Additive manufacturing offers geometric freedom but requires attention to anisotropy, porosity, and post-processing.

Soldering, bonding, and wire or flip-chip interconnection create the electrical and mechanical paths between components. Packaging protects devices, removes heat, controls parasitics, and determines much of the final reliability. Across all processes, interfaces, defects, thermal mismatch, contamination, and residual stress connect manufacturing conditions to field performance. Effective engineering therefore combines material science, process control, characterization, reliability analysis, safety, and lifecycle responsibility.

Key Terms

Purification: Removal of chemical and electrically active impurities from a material.

Zone refining: Purification using a traveling molten zone that transports impurities.

Czochralski growth: Single-crystal growth by pulling and rotating a seed from a melt.

Float-zone growth: Crucible-free crystal growth using a localized molten zone.

Dopant: An intentionally introduced impurity that controls semiconductor properties.

Alloying: Addition of elements to modify a base material’s properties.

Annealing: Heat treatment used to relieve stress and reduce defects.

Diffusion: Thermally activated movement of atoms caused by concentration gradients.

Thin film: A layer of material whose thickness is small relative to its lateral dimensions.

Sputtering: PVD process in which energetic ions eject atoms from a target.

CVD: Deposition formed by chemical reactions of gaseous precursors.

ALD: Sequential, self-limiting deposition process providing precise thickness control.

Lithography: Pattern-transfer process used to define device features.

Sintering: Thermal densification of a powder compact below its melting point.

Thermoplastic: Polymer that can be softened and reshaped repeatedly by heating.

Thermoset: Cross-linked polymer that does not remelt after curing.

Soldering: Joining using a filler alloy with a lower melting point than the components.

Intermetallic compound: Ordered compound formed between metallic elements at an interface or within an alloy.

Underfill: Polymer placed beneath a flip-chip die to distribute stress and improve reliability.

Thermal resistance: Temperature rise per unit heat flow, commonly expressed in °C·W⁻¹.

Review Questions

5 Short Answer Questions

1. Why is impurity control particularly important in semiconductor materials?
2. Distinguish Czochralski growth from float-zone growth.
3. What is the purpose of annealing?
4. State two differences between PVD and CVD.
5. Identify three functions of an electronic package.

5 Long Answer Questions

1. Explain the complete sequence from purified semiconductor feedstock to a polished wafer, including major defect sources.
2. Discuss how heat-treatment temperature and time influence diffusion, residual stress, and phase structure.
3. Compare sputtering, CVD, and ALD in terms of mechanism, conformality, temperature, and production rate.
4. Describe ceramic powder processing and explain how sintering affects density and electrical properties.
5. Explain the major electrical, thermal, mechanical, and environmental requirements of an electronic package.

3 Analytical / Application Questions

1. A thin metallic film has resistivity 2.0 × 10⁻⁸ Ω·m and thickness 200 nm. Calculate its sheet resistance using R_s = ρ/t, and explain one assumption behind the calculation.
2. A device dissipates 8 W and is mounted in an environment at 35 °C. If the junction-to-ambient thermal resistance is 12 °C·W⁻¹, estimate the steady-state junction temperature and assess whether a 125 °C limit is exceeded.
3. A soldered power module fails after thermal cycling. Propose a structured investigation covering materials, process parameters, non-destructive inspection, failure analysis, and corrective action.

Multiple Choice Questions with Answers

Question 1

Which purification method uses a moving molten zone to concentrate impurities at one end of a bar?

A. Zone refining

B. Injection molding

C. Photolithography

D. Sintering

Correct Answer: A. Zone refining

Question 2

What is a major advantage of float-zone crystal growth?

A. It requires a silica crucible

B. It produces very low oxygen contamination

C. It always produces polycrystalline material

D. It eliminates the need for a seed crystal

Correct Answer: B. It produces very low oxygen contamination

Question 3

In the relation J = −D(dc/dx), what does J represent?

A. Electrical current density

B. Atomic flux

C. Heat capacity

D. Film stress

Correct Answer: B. Atomic flux

Question 4

Which deposition method uses sequential, self-limiting surface reactions?

A. Thermal evaporation

B. Ion milling

C. Atomic layer deposition

D. Screen printing

Correct Answer: C. Atomic layer deposition

Question 5

For a uniform conducting film, sheet resistance is given by:

A. R_s = ρt

B. R_s = t/ρ

C. R_s = ρ/t

D. R_s = ρ + t

Correct Answer: C. R_s = ρ/t

Question 6

What is the principal purpose of sintering a ceramic powder compact?

A. To increase pore volume

B. To densify and bond particles

C. To convert every ceramic into a metal

D. To remove all grain boundaries

Correct Answer: B. To densify and bond particles

Question 7

Which polymer type forms a cross-linked network and generally cannot be remelted?

A. Thermoplastic

B. Thermoset

C. Elastomeric melt

D. Photoresist developer

Correct Answer: B. Thermoset

Question 8

Why is flux used in soldering?

A. To increase semiconductor bandgap

B. To remove oxides and promote wetting

C. To prevent all intermetallic formation

D. To replace the solder alloy

Correct Answer: B. To remove oxides and promote wetting

Question 9

A package dissipates 5 W with a junction-to-ambient thermal resistance of 10 °C·W⁻¹ in a 30 °C ambient. What is the estimated junction temperature?

A. 35 °C

B. 50 °C

C. 80 °C

D. 150 °C

Correct Answer: C. 80 °C

Question 10

Which packaging technique places a die directly onto a substrate using bumps or pillars?

A. Flip-chip bonding

B. Zone refining

C. Float-zone growth

D. Compression molding

Correct Answer: A. Flip-chip bonding