Digital Logic, HDL and Programmable Hardware

Introduction

Digital systems represent information using discrete logic levels. Their functions range from simple Boolean decisions to processors, communication controllers and safety-critical state machines. In laboratory work, a circuit must not only produce the correct logical result; it must also satisfy electrical, timing, initialization and implementation constraints.

Hardware description languages (HDLs), such as SystemVerilog and VHDL, describe concurrent hardware structures. Simulation verifies behavior before physical realization, while synthesis translates synthesizable HDL into gates and programmable resources. Field-programmable gate arrays (FPGAs) provide configurable logic blocks, registers, memories, clock networks and interconnect, allowing designs to be implemented and tested rapidly.

This chapter integrates manual logic design, HDL modeling, simulation, timing analysis and FPGA realization. The emphasis is on reproducible laboratory practice and on recognizing the difference between functional correctness and reliable physical operation.

Learning Objectives

After completing this chapter, students should be able to:

• derive and implement combinational logic from specifications and truth tables;
• construct adders, converters, multiplexers and decoders;
• implement registers, counters and finite-state machines;
• write synthesizable SystemVerilog using appropriate combinational and sequential constructs;
• create self-checking testbenches and interpret simulation waveforms;
• analyze propagation delay, setup time, hold time and clock-domain crossing constraints;
• compare major digital logic families and FPGA I/O requirements;
• follow a correct simulation, synthesis, implementation and programming workflow;
• validate an FPGA design using both simulation and physical measurements.

1. Digital Logic Foundations

1.1 Logic levels and Boolean variables

A Boolean variable has two abstract values, 0 and 1. Physical circuits represent these values by voltage ranges rather than exact voltages. A receiving device interprets an input as low when its voltage is below the specified maximum low-input voltage V_IL(max), and as high when it exceeds the minimum high-input voltage V_IH(min). Voltages between these limits may be indeterminate.

The static noise margins are

where V_OH(min) and V_OL(max) are guaranteed output levels. These equations apply when the output and input specifications refer to compatible operating voltage, current, temperature and loading conditions.

For example, if a device guarantees V_OH(min) = 2.4\ V and the receiver requires V_IH(min) = 2.0\ V, the high-level noise margin is NM_H = 0.4\ V.

1.2 Boolean operations

The fundamental operations are NOT, AND and OR. XOR produces 1 when an odd number of its inputs are 1. Important identities include

These are De Morgan’s laws. They support implementation conversion between NAND-based and NOR-based structures.

Boolean simplification can reduce gate count, power and delay. Karnaugh maps are effective for small functions, whereas synthesis tools use algorithmic optimization for larger designs. Designers should nevertheless preserve behavior for all input combinations. Unused combinations may be treated as “don’t care” conditions only when the specification guarantees that they cannot occur or when any resulting output is acceptable.

2. Combinational Logic

A combinational circuit’s output depends only on its present inputs. Ideally it has no stored state, although physical gate delays can produce temporary glitches.

2.1 Multiplexers, decoders and priority encoders

A 2-to-1 multiplexer with data inputs D₀, D₁ and select input S implements

A decoder activates one output corresponding to a binary input. An encoder performs the reverse operation. If multiple inputs may be active, a priority rule must be defined; otherwise the encoded result is ambiguous.

2.2 Adders

A full adder adds bits A_i, B_i and carry-in C_i. Its outputs are

For unsigned n-bit operands A and B, an n-bit sum vector S and a one-bit carry output satisfy

The braces denote concatenation. The left side is n+1 bits wide, so unsigned overflow is retained rather than discarded.

Worked example: four-bit addition

Let A=1101₂=13, B=0110₂=6 and C_in=1. Then

Thus C_out=1 and S=0100₂. If only the four-bit vector were observed, it would appear to equal 4; the carry is required to represent the complete unsigned result.

For two’s-complement addition, carry-out is not itself the signed-overflow indicator. Signed overflow occurs when operands with the same sign produce a result with the opposite sign:

2.3 Converters: hexadecimal to seven-segment display

A code converter maps one representation into another. The following combinational SystemVerilog module converts a four-bit hexadecimal input into active-low segment outputs ordered as abcdefg:

module hex7seg (
    input  logic [3:0] hex,
    output logic [6:0] seg_n
);
    always_comb begin
        unique case (hex)
            4'h0: seg_n = 7'b0000001;
            4'h1: seg_n = 7'b1001111;
            4'h2: seg_n = 7'b0010010;
            4'h3: seg_n = 7'b0000110;
            4'h4: seg_n = 7'b1001100;
            4'h5: seg_n = 7'b0100100;
            4'h6: seg_n = 7'b0100000;
            4'h7: seg_n = 7'b0001111;
            4'h8: seg_n = 7'b0000000;
            4'h9: seg_n = 7'b0000100;
            4'hA: seg_n = 7'b0001000;
            4'hB: seg_n = 7'b1100000;
            4'hC: seg_n = 7'b0110001;
            4'hD: seg_n = 7'b1000010;
            4'hE: seg_n = 7'b0110000;
            4'hF: seg_n = 7'b0111000;
            default: seg_n = 7'b1111111;
        endcase
    end
endmodule

The physical board manual must be checked because segment order and active polarity vary. A common-anode display commonly uses active-low segment controls; a common-cathode display commonly uses active-high controls.

2.4 Hazards

Different path delays can create a transient incorrect output even when the final Boolean result is correct. A static-1 hazard occurs when an output intended to remain at 1 briefly becomes 0. In synchronous systems, hazards are usually tolerated if outputs settle before the capturing clock edge. They remain important for asynchronous controls, clocks, resets and external interfaces. A combinational signal should not be used as a clock merely because it resembles a pulse.

3. Sequential Logic

Sequential circuits contain state. Their outputs depend on present inputs and stored information.

3.1 Flip-flops and registers

An edge-triggered D flip-flop samples input D at a clock edge and stores it as Q. A register is a collection of flip-flops sharing control signals.

A parameterized register with synchronous enable and asynchronous active-low reset is:

module register_en #(parameter int W = 8) (
    input  logic         clk,
    input  logic         rst_n,
    input  logic         en,
    input  logic [W-1:0] d,
    output logic [W-1:0] q
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= '0;
        else if (en)
            q <= d;
    end
endmodule

Nonblocking assignment (<=) models simultaneous register updates. Reset style must match the target device and project requirements. Excessive asynchronous resetting can complicate reset release and timing closure.

3.2 Counters

A modulo-N counter traverses N states. The minimum register width is

For a modulo-10 counter, W=4 because three bits represent only eight states.

module mod_counter #(
    parameter int N = 10,
    parameter int W = $clog2(N)
) (
    input  logic         clk,
    input  logic         rst_n,
    input  logic         en,
    output logic [W-1:0] count,
    output logic         terminal
);
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            count <= '0;
        else if (en) begin
            if (count == N-1)
                count <= '0;
            else
                count <= count + 1'b1;
        end
    end

    assign terminal = en && (count == N-1);
endmodule

This parameterization assumes N\ge2. The terminal output indicates that the enabled counter is about to wrap.

3.3 Frequency division versus clock enable

A binary counter bit can divide a clock frequency, but routing such a bit as a new clock may bypass dedicated clock networks. Within an FPGA, it is usually preferable to retain one global clock and generate a one-cycle clock-enable pulse.

If an input clock of frequency f_clk drives a divider that emits one enable pulse every D cycles, then

For f_clk=100\ MHz and D=100{,}000{,}000, one enable pulse occurs each second.

4. Finite-State Machines

A finite-state machine (FSM) consists of a state register, next-state logic and output logic. In a Moore machine, outputs depend only on state. In a Mealy machine, outputs depend on state and current inputs. Mealy outputs can respond sooner but may be more susceptible to input glitches.

A robust FSM design process is:

1. define states and externally observable behavior;
2. draw a state-transition diagram;
3. specify reset and abnormal-input behavior;
4. choose Moore or Mealy outputs;
5. code state storage and transition logic;
6. provide default assignments to avoid unintended latches;
7. verify legal transitions and recovery behavior.

4.1 Complete pedestrian-crossing FSM

The following synthesizable Moore FSM remains in CARS_GREEN until a request is captured. Durations are measured in one-cycle tick pulses. Requests occurring during a crossing sequence are retained for the next cycle.

module crossing_fsm #(
    parameter int YELLOW_TICKS = 3,
    parameter int ALLRED_TICKS = 1,
    parameter int PED_TICKS    = 6
) (
    input  logic       clk,
    input  logic       rst_n,
    input  logic       tick,
    input  logic       request,
    output logic       car_green,
    output logic       car_yellow,
    output logic       car_red,
    output logic       ped_walk,
    output logic [1:0] state_code
);
    typedef enum logic [1:0] {
        CARS_GREEN, CARS_YELLOW, ALL_RED, PED_GREEN
    } state_t;

    state_t state, next_state;
    logic [31:0] elapsed;
    logic pending;

    always_comb begin
        next_state = state;
        unique case (state)
            CARS_GREEN:  if (pending) next_state = CARS_YELLOW;
            CARS_YELLOW: if (elapsed == YELLOW_TICKS-1)
                             next_state = ALL_RED;
            ALL_RED:     if (elapsed == ALLRED_TICKS-1)
                             next_state = PED_GREEN;
            PED_GREEN:   if (elapsed == PED_TICKS-1)
                             next_state = CARS_GREEN;
            default:     next_state = CARS_GREEN;
        endcase
    end

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state   <= CARS_GREEN;
            elapsed <= 0;
            pending <= 1'b0;
        end else begin
            if (request)
                pending <= 1'b1;

            if (tick) begin
                if (next_state != state) begin
                    state   <= next_state;
                    elapsed <= 0;
                    if (state == CARS_GREEN)
                        pending <= 1'b0;
                end else if (state != CARS_GREEN) begin
                    elapsed <= elapsed + 1'b1;
                end
            end
        end
    end

    always_comb begin
        car_green  = 1'b0;
        car_yellow = 1'b0;
        car_red    = 1'b0;
        ped_walk   = 1'b0;
        state_code = state;

        unique case (state)
            CARS_GREEN:  car_green  = 1'b1;
            CARS_YELLOW: car_yellow = 1'b1;
            ALL_RED:     car_red    = 1'b1;
            PED_GREEN: begin
                car_red  = 1'b1;
                ped_walk = 1'b1;
            end
            default:     car_red = 1'b1;
        endcase
    end
endmodule

The duration parameters must be positive integers. In a production design, parameter checks and safety requirements would be added. Because a request is retained as a single pending bit, multiple requests before service are intentionally coalesced into one event.

5. HDL Modeling and Verification

5.1 Synthesizable and simulation-only constructs

Synthesis maps an HDL description into hardware. Common synthesizable constructs include continuous assignments, bounded combinational logic, registers and statically determinable loops. Testbench constructs such as arbitrary # delays, file-driven stimulus and many system tasks are generally not synthesized.

Use always_comb for combinational processes and always_ff for clocked storage. In a combinational process, assign every output on every execution path. Omitting an assignment may infer a latch.

5.2 Self-checking FSM testbench

A testbench is simulated but is not sent through hardware synthesis. The following testbench checks reset behavior, initiates a request and verifies output safety throughout the sequence:

`timescale 1ns/1ps
module crossing_fsm_tb;
    logic clk = 0, rst_n = 0, tick = 0, request = 0;
    logic car_green, car_yellow, car_red, ped_walk;
    logic [1:0] state_code;

    crossing_fsm #(.YELLOW_TICKS(3), .ALLRED_TICKS(1),
                   .PED_TICKS(6)) dut (.*);

    always #5 clk = ~clk;

    task automatic send_tick;
        begin
            @(negedge clk); tick = 1;
            @(negedge clk); tick = 0;
        end
    endtask

    always @(posedge clk) begin
        if (rst_n) begin
            assert (!(car_green && car_red))
                else $fatal("Conflicting car lamps");
            assert (!(ped_walk && !car_red))
                else $fatal("Pedestrian walk without car red");
        end
    end

    initial begin
        repeat (2) @(negedge clk);
        rst_n = 1;
        @(posedge clk);
        assert (car_green && !ped_walk);

        @(negedge clk); request = 1;
        @(negedge clk); request = 0;
        send_tick();
        @(posedge clk); #1 assert (car_yellow);

        repeat (3) send_tick();
        @(posedge clk); #1 assert (car_red && !ped_walk);

        send_tick();
        @(posedge clk); #1 assert (car_red && ped_walk);

        repeat (6) send_tick();
        @(posedge clk); #1 assert (car_green && !ped_walk);

        $display("FSM test passed");
        $finish;
    end
endmodule

The #1 sampling delay occurs only in the testbench. It allows nonblocking assignments to update before assertions inspect outputs. A broader verification plan should also test reset during every state, back-to-back requests and parameter boundary conditions.

6. FPGA Design Flow

Figure: The testbench participates in functional simulation but is not synthesized. Arrowheads show progression and iterative debugging.

A sound FPGA workflow includes:

1. specification and interface definition;
2. synthesizable HDL development;
3. testbench development and functional simulation;
4. synthesis of the design HDL only;
5. pin, clock and I/O constraint definition;
6. placement and routing;
7. static timing analysis;
8. bitstream generation;
9. programming and physical verification.

Post-synthesis or post-route simulation may be added where gate-level behavior or timing back-annotation is required, but static timing analysis is the primary method for exhaustive timing-path verification.

7. Complete FPGA Laboratory Realization

The following top-level design connects the crossing FSM to board LEDs and the seven-segment converter. It assumes that request_db is already synchronized and debounced by board circuitry or a validated input-conditioning module.

module fpga_top #(
    parameter int CLK_HZ  = 100_000_000,
    parameter int TICK_HZ = 1,
    parameter int DIV     = CLK_HZ / TICK_HZ,
    parameter int CW      = $clog2(DIV)
) (
    input  logic       clk,
    input  logic       rst_n,
    input  logic       request_db,
    output logic       led_green,
    output logic       led_yellow,
    output logic       led_red,
    output logic       led_walk,
    output logic [6:0] seg_n
);
    logic [CW-1:0] divider;
    logic tick;
    logic request_d, request_pulse;
    logic [1:0] state_code;

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            divider <= '0;
            tick    <= 1'b0;
        end else if (divider == DIV-1) begin
            divider <= '0;
            tick    <= 1'b1;
        end else begin
            divider <= divider + 1'b1;
            tick    <= 1'b0;
        end
    end

    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            request_d <= 1'b0;
        else
            request_d <= request_db;
    end

    assign request_pulse = request_db & ~request_d;

    crossing_fsm fsm (
        .clk(clk), .rst_n(rst_n), .tick(tick),
        .request(request_pulse),
        .car_green(led_green), .car_yellow(led_yellow),
        .car_red(led_red), .ped_walk(led_walk),
        .state_code(state_code)
    );

    hex7seg display (
        .hex({2'b00, state_code}),
        .seg_n(seg_n)
    );
endmodule

This implementation assumes CLK\_HZ is exactly divisible by TICK\_HZ, DIV\ge2, and the clock frequency parameter matches the physical oscillator. For other ratios, a phase-accumulator enable generator can provide a more accurate average rate.

A board-specific constraints file must associate ports with physical pins and define electrical standards. Illustrative XDC syntax is:

set_property PACKAGE_PIN <clock_pin> [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -period 10.000 [get_ports clk]
set_property PACKAGE_PIN <green_led_pin> [get_ports led_green]
set_property IOSTANDARD LVCMOS33 [get_ports led_green]

The 10 ns period corresponds to 100 MHz. Placeholder pin names must be replaced using the board’s official master constraints file. Applying an incompatible I/O voltage can damage hardware.

Laboratory procedure

1. Simulate crossing_fsm_tb and confirm that all assertions pass.
2. Synthesize fpga_top; inspect warnings, inferred registers and resource use.
3. enter verified board pin, I/O-standard and clock constraints;
4. run implementation and confirm that setup and hold timing pass;
5. program the FPGA and reset the design;
6. press the conditioned request button and record lamp-state durations;
7. compare measured timing with the parameterized design;
8. document discrepancies, warnings and corrective actions.

8. Timing and Reliable Operation

8.1 Setup and hold constraints

For a register-to-register path in one clock domain, a conservative setup requirement is

Here t_cq,max is the source register’s maximum clock-to-output delay, t_pd,comb,max is maximum combinational and routing delay, t_setup is the destination setup requirement, and t_uncertainty accounts for clock uncertainty under the analysis convention.

The corresponding maximum clock frequency is bounded by

Worked example: If the four terms are 0.35 ns, 5.10 ns, 0.40 ns and 0.25 ns, respectively, the required period is at least 6.10 ns. Therefore,

A conservative hold requirement is

where t_cd,comb,min is the minimum contamination delay. Increasing the clock period does not normally fix a same-edge hold violation; routing delay or dedicated hold correction is required.

8.2 Metastability and asynchronous inputs

An asynchronous input may change near a sampling edge and violate setup or hold time, causing metastability. A two-flip-flop synchronizer greatly reduces the probability that metastability propagates into downstream logic, but it does not make the probability exactly zero.

A single-bit level can usually be synchronized directly. Multi-bit buses, pulses and data streams require protocols such as handshakes, toggle synchronizers or asynchronous FIFOs. Push buttons additionally require debouncing because contact bounce is not solved by synchronization alone.

8.3 Timing simulation versus static timing analysis

Functional simulation checks logical behavior under modeled stimulus. Static timing analysis evaluates implementation paths against timing constraints over specified process, voltage and temperature corners without requiring input vectors. Both are necessary: simulation cannot exhaustively cover every timing path, and timing analysis cannot establish that the intended algorithm is correct.

9. Logic Families and Electrical Constraints

Fan-out is not simply the number of connected loads. At low frequency it may be limited by output current and input leakage. At high frequency, total capacitance, edge rate and signal integrity often dominate. FPGA pins also have limits on drive strength, slew rate, simultaneous switching and bank voltage.

Outputs must not be connected together unless the interface explicitly supports tri-state, open-drain or open-collector operation. Internal FPGA tri-states are generally synthesized as multiplexers; true tri-state behavior normally exists only at I/O pins.

10. Illustrative Case: Campus Crossing Demonstrator

Background

A university laboratory wishes to develop a tabletop pedestrian-crossing demonstrator using an FPGA board. This is an illustrative educational case, not a certified road controller.

Problem

An initial student design uses a push button as a generated clock, includes no default FSM recovery behavior and displays the correct sequence only intermittently. Multiple transitions occur after one press.

Analysis

The button exhibits contact bounce and is asynchronous to the FPGA clock. Using it as a clock introduces an uncontrolled clock domain and bypasses the global clock network. The state logic also lacks complete assignments, causing unintended storage. Finally, the simulation tested only one ideal button pulse.

Approach and solution

The redesigned system uses one board clock, synchronizes and debounces the button, detects one rising-edge request, and generates a one-cycle timing enable rather than a derived internal clock. A Moore FSM controls the lamps. Safety assertions prohibit simultaneous car green and car red and prohibit pedestrian walk unless car red is active. Functional simulation precedes synthesis, while board-specific timing and I/O constraints are applied before implementation.

Outcome

Simulation covers reset, normal requests and requests during an active crossing. Static timing analysis passes at 100 MHz. Hardware tests produce repeatable state durations and no longer respond multiple times to ordinary button bounce.

Learning points

Correct Boolean logic alone does not ensure reliable hardware. Clock architecture, input conditioning, default behavior, constraints and verification must be treated as parts of the design rather than as afterthoughts.

11. Challenges, Governance and Contemporary Practice

HDL designs may fail because of incomplete specifications, mismatches between simulation and synthesis, unconstrained paths, clock-domain errors, incorrect pin assignments or assumptions about reset state. Good practice includes linting, version control, peer review, automated regression testing and retention of tool reports.

Programmable hardware used in transport, medical, industrial or infrastructure applications may be subject to functional-safety, electromagnetic-compatibility and cybersecurity requirements. Educational prototypes must not be represented as certified equipment. Designers should use legitimate tool licenses, protect third-party intellectual property, document reused HDL and avoid embedding sensitive keys in easily readable bitstreams.

Contemporary FPGA development increasingly uses formal property checking, high-level synthesis, soft processors, reusable IP blocks and partial reconfiguration. AI-assisted coding can suggest HDL, but generated designs require human review, simulation, synthesis-warning analysis and physical validation. Plausible HDL can still infer unintended hardware or violate timing and safety requirements.

Chapter Summary

Digital design combines Boolean function, stored state, timing and electrical behavior. Combinational circuits include multiplexers, decoders, adders and code converters, while sequential circuits include registers, counters and finite-state machines. For an unsigned n-bit adder, the complete result is represented by \{C_out,S\}=A+B+C_in.

SystemVerilog supports clear separation between combinational and clocked logic. Testbenches verify behavior through simulation but are not synthesized. A correct FPGA workflow performs functional simulation before synthesis, then applies constraints, implementation, timing analysis, bitstream generation and hardware testing.

Reliable realization requires setup and hold compliance, controlled clocking, synchronization of asynchronous inputs, button debouncing and compatible I/O standards. The complete register, counter, converter, FSM and top-level examples illustrate how these concerns are combined in laboratory practice.

Key Terms

Boolean algebra: Mathematical system for variables having logic values 0 and 1.

Combinational logic: Logic whose output depends only on present inputs.

Sequential logic: Logic whose behavior depends on present inputs and stored state.

Propagation delay: Maximum time for an input change to produce a valid output change.

Contamination delay: Minimum time after an input change at which an output may begin changing.

Noise margin: Tolerable difference between guaranteed output and required input logic levels.

Register: Group of flip-flops used to store a multi-bit value.

Counter: Sequential circuit that advances through a defined state sequence.

Finite-state machine: Sequential model consisting of states, transitions and outputs.

Moore machine: FSM whose outputs depend only on current state.

Mealy machine: FSM whose outputs depend on state and current inputs.

Setup time: Minimum interval for which data must be stable before a sampling clock edge.

Hold time: Minimum interval for which data must remain stable after a sampling edge.

Metastability: Temporary indeterminate behavior caused by violating a storage element’s timing requirements.

Clock-domain crossing: Transfer of information between circuits driven by different or asynchronous clocks.

Synthesis: Translation of synthesizable HDL into a hardware netlist.

Static timing analysis: Vector-independent verification of implementation timing paths.

Testbench: Simulation environment that applies stimulus and checks design responses.

FPGA: Reconfigurable integrated circuit containing programmable logic and interconnect.

Review Questions

Short Answer Questions

1. Distinguish combinational logic from sequential logic.
2. Why is carry-out required to represent a complete unsigned n-bit addition result?
3. What is the purpose of a two-flip-flop synchronizer?
4. Why should a push button not be used directly as an FPGA clock?
5. State one difference between functional simulation and static timing analysis.

Long Answer Questions

1. Explain the complete FPGA development flow from specification to hardware testing.
2. Derive the full-adder sum and carry equations and explain ripple-carry operation.
3. Compare Moore and Mealy machines with respect to response time and output stability.
4. Explain setup time, hold time, clock uncertainty and their influence on reliable operation.
5. Discuss logic-family compatibility, noise margins, fan-out and FPGA I/O-bank constraints.

Analytical / Application Questions

1. Design and write synthesizable HDL for a modulo-12 counter with enable, reset and terminal-count output. Determine the required register width.
2. A register path has t_cq,max=0.5\ ns, t_pd,comb,max=7.2\ ns, t_setup=0.4\ ns and t_uncertainty=0.3\ ns. Calculate the conservative maximum clock frequency.
3. Extend the crossing controller to include a flashing pedestrian warning state. Define the revised states, transitions, outputs and verification properties.

Multiple Choice Questions with Answers

Question 1

For unsigned n-bit operands with an n-bit sum vector S, which equation preserves the complete addition result?

A. S=A+B+C_in with carry discarded

B. \{C_out,S\}=A+B+C_in

C. C_out=A+B

D. \{S,C_out\}=A-B-C_in

Correct Answer: B. \{C_out,S\}=A+B+C_in

Question 2

Which HDL artifact participates in functional simulation but normally is not synthesized into FPGA hardware?

A. Testbench

B. State register

C. Combinational decoder

D. Clock-enable counter

Correct Answer: A. Testbench

Question 3

How many flip-flops are minimally required to represent a modulo-10 counter state?

A. 2

B. 3

C. 4

D. 10

Correct Answer: C. 4

Question 4

A 100 MHz clock produces one enable pulse every 25,000,000 cycles. What is the enable-pulse frequency?

A. 0.25 Hz

B. 4 Hz

C. 25 Hz

D. 40 Hz

Correct Answer: B. 4 Hz

Question 5

Which assignment type is normally used for register updates inside an always_ff process?

A. Continuous assignment

B. Blocking assignment only

C. Nonblocking assignment

D. Preprocessor assignment

Correct Answer: C. Nonblocking assignment

Question 6

Which statement about a Moore FSM is correct?

A. Its outputs depend only on the current state.

B. It cannot contain a state register.

C. Its outputs depend only on current inputs.

D. It must use asynchronous clocks.

Correct Answer: A. Its outputs depend only on the current state.

Question 7

A synchronous path has maximum delays of 0.35 ns clock-to-output, 5.10 ns combinational delay, 0.40 ns setup time and 0.25 ns uncertainty. What is the conservative minimum clock period?

A. 5.10 ns

B. 5.50 ns

C. 6.10 ns

D. 6.35 ns

Correct Answer: C. 6.10 ns

Question 8

What problem is specifically addressed by debouncing a mechanical push button?

A. Clock skew within a global clock tree

B. Multiple transitions caused by contact bounce

C. Unsigned arithmetic overflow

D. Insufficient FPGA configuration memory

Correct Answer: B. Multiple transitions caused by contact bounce

Question 9

Which technique is generally preferred over creating a fabric-derived clock for a slow FPGA process?

A. Generate a one-cycle clock-enable pulse

B. Route an XOR output as a clock

C. Leave the clock input floating

D. Use a seven-segment output as a clock

Correct Answer: A. Generate a one-cycle clock-enable pulse

Question 10

Which verification method evaluates implementation timing paths without requiring functional input vectors?

A. Boolean minimization

B. Static timing analysis

C. Source-code formatting

D. Truth-table encoding

Correct Answer: B. Static timing analysis