Circuit Topology and Fundamental Laws

Introduction

Electrical circuit analysis begins with two complementary descriptions. Topology describes how elements are connected, independent of their physical arrangement. Circuit laws describe the relationships among current, voltage, resistance and power. Together, these ideas allow an engineer to replace a complicated schematic with equations that preserve its electrical behavior.

This chapter assumes a lumped-parameter circuit model: element dimensions are sufficiently small relative to relevant electromagnetic wavelengths, connecting wires are ideal unless assigned resistance, and energy storage or dissipation is represented by explicit circuit elements. Under these assumptions, Ohm’s law and Kirchhoff’s laws provide the foundation for DC and later AC analysis.

Learning Objectives

After studying this chapter, students should be able to:

• distinguish branches, nodes, paths, loops and meshes;
• determine the number of independent loops in a connected circuit;
• apply Ohm’s law using consistent voltage and current references;
• formulate Kirchhoff’s current law (KCL) and voltage law (KVL) equations;
• verify conservation of charge, energy and power;
• identify valid series and parallel connections;
• perform series–parallel reduction;
• apply voltage-divider and current-divider relationships under their stated conditions;
• combine compatible ideal sources and perform source transformations; and
• evaluate circuit solutions using physical and engineering checks.

1. Circuit Models and Reference Conventions

A circuit is an interconnection of electrical elements such as sources, resistors, capacitors and inductors. This chapter concentrates primarily on resistive DC circuits, although the topological laws apply more broadly.

1.1 Current and voltage

Electric current is the rate of flow of charge:

Here, i is current in amperes (A), q is charge in coulombs (C), and t is time in seconds (s). One ampere equals one coulomb per second.

Voltage is electric potential difference, or energy transferred per unit charge:

Here, v is voltage in volts (V) and w is energy in joules (J). One volt equals one joule per coulomb.

Current directions and voltage polarities shown on a schematic are reference choices, not advance claims about actual behavior. A negative calculated value means the physical direction or polarity is opposite to the selected reference.

1.2 Passive sign convention

Under the passive sign convention, current enters the terminal marked positive. The instantaneous power absorbed by an element is then

where p is power in watts (W), v is voltage in volts and i is current in amperes. If p > 0, the element absorbs power; if p < 0, it delivers power. If current is referenced as entering the negative terminal, absorbed power is instead p = -vi.

2. Circuit Topology

Topology concerns connectivity rather than component position, drawing scale or wire shape. Schematics that look different may therefore represent the same circuit.

2.1 Nodes and branches

A node is a set of points joined by ideal conductors without an intervening circuit element. Every point on such an uninterrupted conductor has the same potential in the ideal-wire model.

A branch is a single two-terminal circuit element connected between two nodes. In this chapter, an ideal wire is treated as a connection forming part of a node, not as an element branch. If wire resistance is important, it must be represented explicitly as a resistor; that resistor then constitutes a branch.

An essential node is a node to which three or more branches are connected. An essential branch is commonly understood as a path between two essential nodes containing no essential node internally; this broader usage should not be confused with the single-element branch convention used for branch counting here.

Figure: A correctly connected two-mesh circuit. Nodes a, b, c and d are separated by elements; the five branches are Vₛ, R₁, R₂, R₃ and R₄.

The circuit has four nodes and five element branches. Nodes b and d are essential nodes. The source branch provides a complete return path, so the left-hand loop is closed.

2.2 Paths, loops and meshes

A path is a sequence of connected branches encountered without passing through a node more than once. A loop is a closed path whose initial and final node are the same, with no other node repeated. A mesh is a loop that contains no other loop in its interior. Meshes are defined directly only for a planar drawing—a drawing whose branches do not cross except at nodes.

In the figure, the left mesh contains V_s, R₁ and R₂. The right mesh contains R₂, R₃ and R₄. The outer path is also a loop, but it is not a mesh because it encloses both meshes.

For a connected graph with B branches and N nodes, the number of independent loops is

Thus, the figure has L = 5 - 4 + 1 = 2 independent loops. More generally, for a graph with C disconnected components,

These are topological results; they do not depend on component values.

3. Ohm’s Law and Resistive Power

For an ideal linear resistor using the passive sign convention,

where R is resistance in ohms (Ω), v is voltage in volts and i is current in amperes. This equation assumes that resistance is constant over the operating range. Real resistors may vary with temperature, frequency or applied voltage.

Conductance is the reciprocal of resistance:

Conductance G is measured in siemens (S). The reciprocal form requires R ≠ 0. An ideal short circuit has R = 0 and zero voltage for finite current; an ideal open circuit has G = 0 and zero current for finite voltage.

Combining Ohm’s law with p = vi gives the resistor power relationships

The last expression requires R > 0. A positive resistor always absorbs power.

Worked Example 1: Resistor operating point

A 6 Ω resistor carries 2 A into its positive-reference terminal. Its voltage and absorbed power are

The same power follows from i²R = (2 A)²(6 Ω) = 24 W.

4. Kirchhoff’s Laws and Conservation Principles

4.1 Kirchhoff’s current law

Kirchhoff’s current law expresses conservation of charge. If a node does not accumulate net charge, the algebraic sum of currents at that node is zero:

Each current i_k must be assigned an algebraic sign. One consistent convention is positive for currents leaving the node and negative for currents entering it. An equivalent statement is

KCL follows from charge balance:

For the ideal lumped node, stored node charge is neglected, so dq_node/dt = 0. Capacitance, when relevant, is modeled explicitly as an element rather than hidden at an ideal node.

Worked Example 2: Applying KCL

At a node, currents of 5 A and 1.5 A enter. A 2 A current leaves, together with unknown current i_x. Therefore,

so i_x = 4.5 A leaving the node.

4.2 Kirchhoff’s voltage law

Kirchhoff’s voltage law expresses conservation of energy around a closed path. The algebraic sum of voltage rises and drops around a loop is zero:

When traversing a loop, crossing an element from its negative to positive reference terminal is a voltage rise; crossing from positive to negative is a drop. Any consistent sign convention gives the same physical result.

KVL applies directly to lumped circuits when time-varying magnetic flux linking the chosen loop is negligible or represented by explicit induced-voltage elements. In extended electromagnetic structures, Faraday’s law must be considered:

Thus, ordinary zero-sum KVL is a circuit-model statement, not an unrestricted claim about every spatial electromagnetic path.

Worked Example 3: Single-loop circuit

A 24 V source supplies three series resistors of 3 Ω, 5 Ω and 4 Ω. Applying KVL in the current direction gives

Hence,

The resistor voltage drops are 6 V, 10 V and 8 V. Their sum is 24 V, confirming KVL.

4.3 Conservation of power

In any lumped circuit satisfying consistent KCL and KVL equations, total instantaneous power is conserved:

Power delivered is represented by negative absorbed power under the passive sign convention. For Worked Example 3, the source delivers 48 W. The resistors absorb

Power balance is a valuable error-detection test, although agreement alone does not prove that every branch variable is correct.

4.4 Matrix interpretation

For an oriented circuit graph, KCL can be written

where A is the node–branch incidence matrix and i is the branch-current vector. One node equation is dependent in each connected component because summing all node equations gives zero. KVL can similarly be expressed using an independent loop matrix F:

where v is the branch-voltage vector. These formulations underpin computer-based nodal and mesh analysis.

5. Series and Parallel Connections

Circuit reduction depends on connectivity, not visual alignment.

5.1 Series elements

Two elements are in series if they share a node that has no other branch connection. They must therefore carry the same current. For n series resistors,

This follows from KVL:

The formula applies only when the same current flows through every resistor.

5.2 Parallel elements

Elements are in parallel if both terminals of every element connect to the same two nodes. They therefore have the same voltage. For parallel resistors,

Equivalently,

This follows from KCL because i = ∑(v/R_k). For exactly two finite resistors,

The product-over-sum expression is a two-resistor special case, not a general formula for three or more resistors.

Worked Example 4: Series–parallel reduction

An 18 V source supplies a 3 Ω resistor in series with a parallel combination of 6 Ω and 3 Ω. The parallel equivalent is

The total resistance and source current are

The parallel-network voltage is

Thus, the 6 Ω and 3 Ω branch currents are 1.2 A and 2.4 A. Their sum is 3.6 A, satisfying KCL.

Not every circuit can be reduced solely by repeated series and parallel combinations. Bridge networks are a common counterexample and require systematic nodal, mesh or transformation methods.

6. Voltage and Current Division

6.1 Voltage division

For series resistors carrying current i,

Here, V_T is the voltage across the complete series chain and V_k is the voltage across R_k, with consistent polarities. Voltage divides in proportion to resistance.

This formula assumes that the elements form a genuine series chain. If a load is connected across one resistor, the load changes that section’s equivalent resistance and the original unloaded divider formula is no longer valid.

Example. Two series resistors, 2 kΩ and 8 kΩ, are connected across 10 V. The voltage across the 8 kΩ resistor is

If a finite load is added across the 8 kΩ resistor, 8 V is generally no longer obtained.

6.2 Current division

For parallel branches with conductances G_k, the total current I_T divides according to

This general form applies to linear resistive branches connected across the same two nodes. Because conductance is the reciprocal of resistance, lower resistance carries higher current.

For exactly two parallel resistors,

Each branch current contains the other branch’s resistance in the numerator.

Example. A total current of 9 A enters parallel resistors of 6 Ω and 3 Ω. The current through the 6 Ω resistor is

The 3 Ω branch carries 6 A, and KCL gives 3 + 6 = 9 A.

7. Combining and Transforming Sources

7.1 Voltage sources in series and parallel

Ideal voltage sources in series may be replaced at their external terminals by the algebraic sum of their voltages, provided the intermediate connection is not required as an accessible terminal:

Here, s_k = +1 for an aiding orientation and s_k = -1 for an opposing orientation.

Ideal voltage sources may be connected in parallel only when they impose exactly the same voltage with the same polarity. Unequal ideal voltage sources in parallel create contradictory constraints and imply undefined or unbounded current in the ideal model. Real sources require internal resistance and manufacturer-approved sharing controls.

7.2 Current sources in parallel and series

Ideal current sources in parallel combine algebraically:

The signs depend on source-arrow directions. Series ideal current sources are compatible only if they impose the same current in the same series direction. Unequal series current sources impose contradictory branch-current constraints.

7.3 Source transformation

A practical voltage-source model consisting of ideal voltage V_s in series with resistance R_s is terminally equivalent to an ideal current source in parallel with the same resistance:

The current-source arrow is directed from the negative toward the positive terminal of the equivalent voltage source. Conversely, V_s = I_sR_s. The transformation requires a finite, nonzero resistance and preserves terminal voltage–current behavior, not internal branch variables or internal power allocation.

For example, a 12 V source in series with 4 Ω is terminally equivalent to a 3 A source in parallel with 4 Ω.

8. Applied Case: Low-Voltage DC Distribution Feeder

Background

This illustrative case considers a 24 V DC laboratory supply feeding two resistive loads through a cable. Cable resistance is frequently omitted from elementary schematics, but it affects voltage regulation, efficiency and conductor heating.

Problem

The cable’s total outgoing-and-return resistance is 0.40 Ω. At the remote bus, 12 Ω and 8 Ω loads are connected in parallel. Determine the bus voltage, branch currents and power balance. Assess the design against an illustrative ±5% voltage criterion.

Analysis and solution

The remote load equivalent is

The source sees 0.40 Ω in series with 4.8 Ω:

The feeder current is

The remote bus voltage is

The load currents are

Their sum is 4.615 A, confirming KCL. The source power magnitude is 110.769 W. The cable loss is

The loads absorb approximately 40.899 W and 61.349 W, totaling 102.248 W. Rounding aside, cable and load absorption equal source delivery.

The voltage drop is

This exceeds the stated illustrative 5% criterion. That criterion is a project assumption, not a universal regulatory limit.

Improved approach and outcome

Reducing total cable resistance to 0.20 Ω gives a total resistance of 5.0 Ω, current of 4.8 A and bus voltage of 23.04 V. The drop becomes 4%, satisfying the assumed criterion. Cable loss becomes 4.608 W.

A professional design must also verify conductor ampacity, insulation rating, overcurrent protection, connector temperature rise, fault current and applicable electrical codes. Simply increasing conductor size without checking protection coordination is incomplete engineering.

Learning points

• Wire resistance should be represented explicitly when voltage drop matters.
• KCL checks current distribution; KVL checks source and load voltages.
• Power balance provides an independent numerical check.
• Improving voltage regulation may increase load power for fixed resistive loads because their terminal voltage rises.
• Compliance claims must cite the actual jurisdiction, standard and installation conditions.

9. Practical Limitations and Professional Practice

Ideal circuit laws are powerful, but model validity must be assessed.

• Nonideal conductors: Long or narrow conductors possess resistance and inductance.
• Source limits: Real sources have internal impedance, current limits and thermal constraints.
• Nonlinear elements: Diodes, transistors and temperature-dependent resistors do not obey a constant-resistance form of Ohm’s law over all operating conditions.
• High-frequency behavior: Parasitic capacitance, inductance, propagation delay and electromagnetic coupling can invalidate a simple lumped model.
• Measurement loading: Voltmeters and ammeters alter circuits unless their finite input or burden impedances are negligible.
• Topology errors: Misidentifying nodes is often more damaging than an arithmetic error. Redrawing a circuit while preserving node connections is good practice.
• Safety: De-energization, isolation, discharge of stored energy and verified measurement categories are required in laboratory and industrial work.

Circuit simulators automatically apply topological laws, but they do not guarantee a meaningful model. Floating nodes, incompatible ideal sources and omitted parasitics may cause singular or misleading solutions. AI-assisted schematic interpretation can support documentation and error detection, but connectivity, units, source orientations and component ratings require verification by a competent engineer.

10. A Reliable Analysis Workflow

1. Identify every uninterrupted ideal-conductor region and assign one node label to it.
2. Count element branches; do not count ideal wire segments as component branches.
3. Mark reference current directions and voltage polarities.
4. Identify genuine series and parallel relationships from node connectivity.
5. Simplify only when the external behavior of interest is preserved.
6. Apply Ohm’s law, KCL and KVL with one consistent sign convention.
7. Retain units throughout calculations.
8. Check KCL at selected nodes, KVL around independent loops and total power balance.
9. Test whether magnitudes and signs are physically plausible.
10. Reassess the model if wire resistance, loading, temperature, frequency or source limitations are significant.

Chapter Summary

Circuit topology specifies how elements are interconnected. A node is an equipotential set of points joined by ideal conductors, while a branch is a two-terminal element between nodes. Paths describe traversals through connected branches; loops are closed paths; meshes are loops containing no smaller loop. A connected circuit with B branches and N nodes has B-N+1 independent loops.

Ohm’s law relates voltage and current for a linear resistor. KCL expresses conservation of charge at nodes, while KVL expresses conservation of energy around lumped-circuit loops. With the passive sign convention, positive power denotes absorption, and total circuit power sums to zero.

Series resistors carry the same current and add directly. Parallel resistors share the same voltage and add by conductance. Voltage division applies to true series chains, while current division applies to parallel branches. Ideal sources can be combined only when their imposed constraints are compatible. Source transformations preserve external terminal behavior but not internal variables. Reliable engineering analysis combines correct topology, consistent signs, unit checks, conservation tests and awareness of model limitations.

Key Terms

Branch: A two-terminal circuit element connected between two nodes.

Circuit topology: The connectivity of circuit elements independent of physical layout.

Conductance: The reciprocal of resistance, measured in siemens.

Current division: Distribution of total current among parallel branches according to conductance.

Essential node: A node connected to three or more branches.

Ideal wire: A zero-voltage connection whose points form one node.

Kirchhoff’s current law: The algebraic sum of currents at an ideal lumped node is zero.

Kirchhoff’s voltage law: The algebraic sum of voltages around a lumped-circuit loop is zero.

Loop: A closed path with no repeated node other than the initial and final node.

Mesh: A loop that encloses no other loop in a planar circuit.

Node: A set of points connected by ideal conductors without intervening elements.

Ohm’s law: The linear resistor relationship v = Ri.

Parallel connection: A connection in which elements share the same two nodes.

Passive sign convention: A convention in which referenced current enters an element’s positive-voltage terminal.

Path: A sequence of connected branches that does not repeat a node.

Power balance: The requirement that total instantaneous power delivered equals total power absorbed.

Series connection: A connection in which elements carry the same current through an unbranched shared node.

Source transformation: Replacement of a voltage source with series resistance by a terminally equivalent current source with parallel resistance, or vice versa.

Voltage division: Distribution of voltage among series resistors in proportion to resistance.

Review Questions

Short Answer Questions

1. Define a node and explain why several separated-looking wire segments may constitute one node.
2. Distinguish a loop from a mesh.
3. State the passive sign convention and interpret negative calculated power.
4. Under what condition are two circuit elements in series?
5. Why cannot unequal ideal voltage sources be connected directly in parallel?

Long Answer Questions

1. Derive the equivalent resistance of a set of series resistors using KVL and Ohm’s law.
2. Derive the general current-divider relationship using conductance and KCL.
3. Explain the conservation principles underlying KCL, KVL and power balance, including the limits of the lumped-circuit assumptions.
4. Discuss source combination and source transformation, clearly identifying compatibility and equivalence conditions.
5. Explain how topology errors arise in schematics and propose a systematic procedure for identifying branches, nodes and independent loops.

Analytical / Application Questions

1. A 30 V source supplies a 5 Ω resistor in series with parallel resistors of 10 Ω and 15 Ω. Determine the equivalent resistance, source current, every resistor voltage and current, and the complete power balance.
2. A 12 V divider contains 2 kΩ and 4 kΩ series resistors. A 4 kΩ load is then connected across the original 4 kΩ resistor. Calculate the loaded output voltage and compare it with the unloaded value.
3. A remote 48 V load network consists of 24 Ω and 12 Ω parallel branches supplied through a cable of total resistance 0.60 Ω. Determine bus voltage, branch currents, cable loss, load power and percentage voltage drop.

Multiple Choice Questions with Answers

Question 1

Which statement correctly defines a node in the ideal lumped-circuit model?

A. Any point where exactly three resistors meet

B. A set of points joined by ideal conductors without an intervening element

C. A closed path containing a source

D. Every visible bend in a conductor

Correct Answer: B. A set of points joined by ideal conductors without an intervening element

Question 2

A connected circuit has 7 element branches and 5 nodes. How many independent loops does it have?

A. 2

B. 3

C. 5

D. 12

Correct Answer: B. 3

Question 3

A 4 Ω resistor carries 3 A into its positive-reference terminal. What power does it absorb?

A. 12 W

B. 24 W

C. 36 W

D. 48 W

Correct Answer: C. 36 W

Question 4

Currents of 7 A and 2 A enter a node. Currents of 4 A and i_x leave. What is i_x?

A. 1 A

B. 3 A

C. 5 A

D. 13 A

Correct Answer: C. 5 A

Question 5

A 20 V source supplies series resistors of 2 Ω and 8 Ω. What is the voltage across the 8 Ω resistor?

A. 4 V

B. 8 V

C. 16 V

D. 20 V

Correct Answer: C. 16 V

Question 6

A total current of 12 A enters two parallel resistors of 3 Ω and 6 Ω. What current flows through the 6 Ω resistor?

A. 4 A

B. 6 A

C. 8 A

D. 12 A

Correct Answer: A. 4 A

Question 7

Which condition is required for two resistors to be in parallel?

A. They must have equal resistance

B. They must carry equal current

C. Both terminals must connect to the same two nodes

D. They must be drawn side by side

Correct Answer: C. Both terminals must connect to the same two nodes

Question 8

What is the equivalent resistance of 4 Ω and 12 Ω connected in parallel?

A. 2 Ω

B. 3 Ω

C. 8 Ω

D. 16 Ω

Correct Answer: B. 3 Ω

Question 9

Which statement about ideal voltage sources is correct?

A. Unequal ideal voltage sources may always be connected in parallel

B. Parallel ideal voltage sources must impose the same voltage and polarity

C. Series ideal voltage sources cannot be combined

D. An ideal voltage source must have finite internal resistance

Correct Answer: B. Parallel ideal voltage sources must impose the same voltage and polarity

Question 10

A 15 V source in series with 5 Ω is transformed into its terminally equivalent current-source model. What are the current and parallel resistance?

A. 3 A in parallel with 5 Ω

B. 5 A in parallel with 3 Ω

C. 3 A in parallel with 15 Ω

D. 75 A in parallel with 5 Ω

Correct Answer: A. 3 A in parallel with 5 Ω